tc0.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_TC0_INSTANCE_
36 #define _SAME70_TC0_INSTANCE_
37 
38 /* ========== Register definition for TC0 peripheral ========== */
39 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40  #define REG_TC0_CCR0 (0x4000C000U)
41  #define REG_TC0_CMR0 (0x4000C004U)
42  #define REG_TC0_SMMR0 (0x4000C008U)
43  #define REG_TC0_RAB0 (0x4000C00CU)
44  #define REG_TC0_CV0 (0x4000C010U)
45  #define REG_TC0_RA0 (0x4000C014U)
46  #define REG_TC0_RB0 (0x4000C018U)
47  #define REG_TC0_RC0 (0x4000C01CU)
48  #define REG_TC0_SR0 (0x4000C020U)
49  #define REG_TC0_IER0 (0x4000C024U)
50  #define REG_TC0_IDR0 (0x4000C028U)
51  #define REG_TC0_IMR0 (0x4000C02CU)
52  #define REG_TC0_EMR0 (0x4000C030U)
53  #define REG_TC0_CCR1 (0x4000C040U)
54  #define REG_TC0_CMR1 (0x4000C044U)
55  #define REG_TC0_SMMR1 (0x4000C048U)
56  #define REG_TC0_RAB1 (0x4000C04CU)
57  #define REG_TC0_CV1 (0x4000C050U)
58  #define REG_TC0_RA1 (0x4000C054U)
59  #define REG_TC0_RB1 (0x4000C058U)
60  #define REG_TC0_RC1 (0x4000C05CU)
61  #define REG_TC0_SR1 (0x4000C060U)
62  #define REG_TC0_IER1 (0x4000C064U)
63  #define REG_TC0_IDR1 (0x4000C068U)
64  #define REG_TC0_IMR1 (0x4000C06CU)
65  #define REG_TC0_EMR1 (0x4000C070U)
66  #define REG_TC0_CCR2 (0x4000C080U)
67  #define REG_TC0_CMR2 (0x4000C084U)
68  #define REG_TC0_SMMR2 (0x4000C088U)
69  #define REG_TC0_RAB2 (0x4000C08CU)
70  #define REG_TC0_CV2 (0x4000C090U)
71  #define REG_TC0_RA2 (0x4000C094U)
72  #define REG_TC0_RB2 (0x4000C098U)
73  #define REG_TC0_RC2 (0x4000C09CU)
74  #define REG_TC0_SR2 (0x4000C0A0U)
75  #define REG_TC0_IER2 (0x4000C0A4U)
76  #define REG_TC0_IDR2 (0x4000C0A8U)
77  #define REG_TC0_IMR2 (0x4000C0ACU)
78  #define REG_TC0_EMR2 (0x4000C0B0U)
79  #define REG_TC0_BCR (0x4000C0C0U)
80  #define REG_TC0_BMR (0x4000C0C4U)
81  #define REG_TC0_QIER (0x4000C0C8U)
82  #define REG_TC0_QIDR (0x4000C0CCU)
83  #define REG_TC0_QIMR (0x4000C0D0U)
84  #define REG_TC0_QISR (0x4000C0D4U)
85  #define REG_TC0_FMR (0x4000C0D8U)
86  #define REG_TC0_WPMR (0x4000C0E4U)
87  #define REG_TC0_VER (0x4000C0FCU)
88 #else
89  #define REG_TC0_CCR0 (*(__O uint32_t*)0x4000C000U)
90  #define REG_TC0_CMR0 (*(__IO uint32_t*)0x4000C004U)
91  #define REG_TC0_SMMR0 (*(__IO uint32_t*)0x4000C008U)
92  #define REG_TC0_RAB0 (*(__I uint32_t*)0x4000C00CU)
93  #define REG_TC0_CV0 (*(__I uint32_t*)0x4000C010U)
94  #define REG_TC0_RA0 (*(__IO uint32_t*)0x4000C014U)
95  #define REG_TC0_RB0 (*(__IO uint32_t*)0x4000C018U)
96  #define REG_TC0_RC0 (*(__IO uint32_t*)0x4000C01CU)
97  #define REG_TC0_SR0 (*(__I uint32_t*)0x4000C020U)
98  #define REG_TC0_IER0 (*(__O uint32_t*)0x4000C024U)
99  #define REG_TC0_IDR0 (*(__O uint32_t*)0x4000C028U)
100  #define REG_TC0_IMR0 (*(__I uint32_t*)0x4000C02CU)
101  #define REG_TC0_EMR0 (*(__IO uint32_t*)0x4000C030U)
102  #define REG_TC0_CCR1 (*(__O uint32_t*)0x4000C040U)
103  #define REG_TC0_CMR1 (*(__IO uint32_t*)0x4000C044U)
104  #define REG_TC0_SMMR1 (*(__IO uint32_t*)0x4000C048U)
105  #define REG_TC0_RAB1 (*(__I uint32_t*)0x4000C04CU)
106  #define REG_TC0_CV1 (*(__I uint32_t*)0x4000C050U)
107  #define REG_TC0_RA1 (*(__IO uint32_t*)0x4000C054U)
108  #define REG_TC0_RB1 (*(__IO uint32_t*)0x4000C058U)
109  #define REG_TC0_RC1 (*(__IO uint32_t*)0x4000C05CU)
110  #define REG_TC0_SR1 (*(__I uint32_t*)0x4000C060U)
111  #define REG_TC0_IER1 (*(__O uint32_t*)0x4000C064U)
112  #define REG_TC0_IDR1 (*(__O uint32_t*)0x4000C068U)
113  #define REG_TC0_IMR1 (*(__I uint32_t*)0x4000C06CU)
114  #define REG_TC0_EMR1 (*(__IO uint32_t*)0x4000C070U)
115  #define REG_TC0_CCR2 (*(__O uint32_t*)0x4000C080U)
116  #define REG_TC0_CMR2 (*(__IO uint32_t*)0x4000C084U)
117  #define REG_TC0_SMMR2 (*(__IO uint32_t*)0x4000C088U)
118  #define REG_TC0_RAB2 (*(__I uint32_t*)0x4000C08CU)
119  #define REG_TC0_CV2 (*(__I uint32_t*)0x4000C090U)
120  #define REG_TC0_RA2 (*(__IO uint32_t*)0x4000C094U)
121  #define REG_TC0_RB2 (*(__IO uint32_t*)0x4000C098U)
122  #define REG_TC0_RC2 (*(__IO uint32_t*)0x4000C09CU)
123  #define REG_TC0_SR2 (*(__I uint32_t*)0x4000C0A0U)
124  #define REG_TC0_IER2 (*(__O uint32_t*)0x4000C0A4U)
125  #define REG_TC0_IDR2 (*(__O uint32_t*)0x4000C0A8U)
126  #define REG_TC0_IMR2 (*(__I uint32_t*)0x4000C0ACU)
127  #define REG_TC0_EMR2 (*(__IO uint32_t*)0x4000C0B0U)
128  #define REG_TC0_BCR (*(__O uint32_t*)0x4000C0C0U)
129  #define REG_TC0_BMR (*(__IO uint32_t*)0x4000C0C4U)
130  #define REG_TC0_QIER (*(__O uint32_t*)0x4000C0C8U)
131  #define REG_TC0_QIDR (*(__O uint32_t*)0x4000C0CCU)
132  #define REG_TC0_QIMR (*(__I uint32_t*)0x4000C0D0U)
133  #define REG_TC0_QISR (*(__I uint32_t*)0x4000C0D4U)
134  #define REG_TC0_FMR (*(__IO uint32_t*)0x4000C0D8U)
135  #define REG_TC0_WPMR (*(__IO uint32_t*)0x4000C0E4U)
136  #define REG_TC0_VER (*(__I uint32_t*)0x4000C0FCU)
137 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
138 
139 #endif /* _SAME70_TC0_INSTANCE_ */


inertial_sense_ros
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autogenerated on Sat Sep 19 2020 03:19:05