Go to the documentation of this file. 35 #ifndef _SAME70_MATRIX_INSTANCE_ 36 #define _SAME70_MATRIX_INSTANCE_ 39 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 40 #define REG_MATRIX_MCFG0 (0x40088000U) 41 #define REG_MATRIX_MCFG1 (0x40088004U) 42 #define REG_MATRIX_MCFG2 (0x40088008U) 43 #define REG_MATRIX_MCFG3 (0x4008800CU) 44 #define REG_MATRIX_MCFG4 (0x40088010U) 45 #define REG_MATRIX_MCFG5 (0x40088014U) 46 #define REG_MATRIX_MCFG6 (0x40088018U) 47 #define REG_MATRIX_MCFG8 (0x40088020U) 48 #define REG_MATRIX_MCFG9 (0x40088024U) 49 #define REG_MATRIX_MCFG10 (0x40088028U) 50 #define REG_MATRIX_MCFG11 (0x4008802CU) 51 #define REG_MATRIX_MCFG12 (0x40088030U) 52 #define REG_MATRIX_SCFG (0x40088040U) 53 #define REG_MATRIX_PRAS0 (0x40088080U) 54 #define REG_MATRIX_PRBS0 (0x40088084U) 55 #define REG_MATRIX_PRAS1 (0x40088088U) 56 #define REG_MATRIX_PRBS1 (0x4008808CU) 57 #define REG_MATRIX_PRAS2 (0x40088090U) 58 #define REG_MATRIX_PRBS2 (0x40088094U) 59 #define REG_MATRIX_PRAS3 (0x40088098U) 60 #define REG_MATRIX_PRBS3 (0x4008809CU) 61 #define REG_MATRIX_PRAS4 (0x400880A0U) 62 #define REG_MATRIX_PRBS4 (0x400880A4U) 63 #define REG_MATRIX_PRAS5 (0x400880A8U) 64 #define REG_MATRIX_PRBS5 (0x400880ACU) 65 #define REG_MATRIX_PRAS6 (0x400880B0U) 66 #define REG_MATRIX_PRBS6 (0x400880B4U) 67 #define REG_MATRIX_PRAS7 (0x400880B8U) 68 #define REG_MATRIX_PRBS7 (0x400880BCU) 69 #define REG_MATRIX_PRAS8 (0x400880C0U) 70 #define REG_MATRIX_PRBS8 (0x400880C4U) 71 #define REG_MATRIX_MRCR (0x40088100U) 72 #define REG_CCFG_CAN0 (0x40088110U) 73 #define REG_CCFG_SYSIO (0x40088114U) 74 #define REG_CCFG_PCCR (0x40088118U) 75 #define REG_CCFG_DYNCKG (0x4008811CU) 76 #define REG_CCFG_SMCNFCS (0x40088124U) 77 #define REG_MATRIX_WPMR (0x400881E4U) 78 #define REG_MATRIX_WPSR (0x400881E8U) 79 #define REG_MATRIX_VERSION (0x400881FCU) 81 #define REG_MATRIX_MCFG0 (*(__IO uint32_t*)0x40088000U) 82 #define REG_MATRIX_MCFG1 (*(__IO uint32_t*)0x40088004U) 83 #define REG_MATRIX_MCFG2 (*(__IO uint32_t*)0x40088008U) 84 #define REG_MATRIX_MCFG3 (*(__IO uint32_t*)0x4008800CU) 85 #define REG_MATRIX_MCFG4 (*(__IO uint32_t*)0x40088010U) 86 #define REG_MATRIX_MCFG5 (*(__IO uint32_t*)0x40088014U) 87 #define REG_MATRIX_MCFG6 (*(__IO uint32_t*)0x40088018U) 88 #define REG_MATRIX_MCFG8 (*(__IO uint32_t*)0x40088020U) 89 #define REG_MATRIX_MCFG9 (*(__IO uint32_t*)0x40088024U) 90 #define REG_MATRIX_MCFG10 (*(__IO uint32_t*)0x40088028U) 91 #define REG_MATRIX_MCFG11 (*(__IO uint32_t*)0x4008802CU) 92 #define REG_MATRIX_MCFG12 (*(__IO uint32_t*)0x40088030U) 93 #define REG_MATRIX_SCFG (*(__IO uint32_t*)0x40088040U) 94 #define REG_MATRIX_PRAS0 (*(__IO uint32_t*)0x40088080U) 95 #define REG_MATRIX_PRBS0 (*(__IO uint32_t*)0x40088084U) 96 #define REG_MATRIX_PRAS1 (*(__IO uint32_t*)0x40088088U) 97 #define REG_MATRIX_PRBS1 (*(__IO uint32_t*)0x4008808CU) 98 #define REG_MATRIX_PRAS2 (*(__IO uint32_t*)0x40088090U) 99 #define REG_MATRIX_PRBS2 (*(__IO uint32_t*)0x40088094U) 100 #define REG_MATRIX_PRAS3 (*(__IO uint32_t*)0x40088098U) 101 #define REG_MATRIX_PRBS3 (*(__IO uint32_t*)0x4008809CU) 102 #define REG_MATRIX_PRAS4 (*(__IO uint32_t*)0x400880A0U) 103 #define REG_MATRIX_PRBS4 (*(__IO uint32_t*)0x400880A4U) 104 #define REG_MATRIX_PRAS5 (*(__IO uint32_t*)0x400880A8U) 105 #define REG_MATRIX_PRBS5 (*(__IO uint32_t*)0x400880ACU) 106 #define REG_MATRIX_PRAS6 (*(__IO uint32_t*)0x400880B0U) 107 #define REG_MATRIX_PRBS6 (*(__IO uint32_t*)0x400880B4U) 108 #define REG_MATRIX_PRAS7 (*(__IO uint32_t*)0x400880B8U) 109 #define REG_MATRIX_PRBS7 (*(__IO uint32_t*)0x400880BCU) 110 #define REG_MATRIX_PRAS8 (*(__IO uint32_t*)0x400880C0U) 111 #define REG_MATRIX_PRBS8 (*(__IO uint32_t*)0x400880C4U) 112 #define REG_MATRIX_MRCR (*(__IO uint32_t*)0x40088100U) 113 #define REG_CCFG_CAN0 (*(__IO uint32_t*)0x40088110U) 114 #define REG_CCFG_SYSIO (*(__IO uint32_t*)0x40088114U) 115 #define REG_CCFG_PCCR (*(__IO uint32_t*)0x40088118U) 116 #define REG_CCFG_DYNCKG (*(__IO uint32_t*)0x4008811CU) 117 #define REG_CCFG_SMCNFCS (*(__IO uint32_t*)0x40088124U) 118 #define REG_MATRIX_WPMR (*(__IO uint32_t*)0x400881E4U) 119 #define REG_MATRIX_WPSR (*(__I uint32_t*)0x400881E8U) 120 #define REG_MATRIX_VERSION (*(__I uint32_t*)0x400881FCU)