instance/isi.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_ISI_INSTANCE_
36 #define _SAME70_ISI_INSTANCE_
37 
38 /* ========== Register definition for ISI peripheral ========== */
39 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40  #define REG_ISI_CFG1 (0x4004C000U)
41  #define REG_ISI_CFG2 (0x4004C004U)
42  #define REG_ISI_PSIZE (0x4004C008U)
43  #define REG_ISI_PDECF (0x4004C00CU)
44  #define REG_ISI_Y2R_SET0 (0x4004C010U)
45  #define REG_ISI_Y2R_SET1 (0x4004C014U)
46  #define REG_ISI_R2Y_SET0 (0x4004C018U)
47  #define REG_ISI_R2Y_SET1 (0x4004C01CU)
48  #define REG_ISI_R2Y_SET2 (0x4004C020U)
49  #define REG_ISI_CR (0x4004C024U)
50  #define REG_ISI_SR (0x4004C028U)
51  #define REG_ISI_IER (0x4004C02CU)
52  #define REG_ISI_IDR (0x4004C030U)
53  #define REG_ISI_IMR (0x4004C034U)
54  #define REG_ISI_DMA_CHER (0x4004C038U)
55  #define REG_ISI_DMA_CHDR (0x4004C03CU)
56  #define REG_ISI_DMA_CHSR (0x4004C040U)
57  #define REG_ISI_DMA_P_ADDR (0x4004C044U)
58  #define REG_ISI_DMA_P_CTRL (0x4004C048U)
59  #define REG_ISI_DMA_P_DSCR (0x4004C04CU)
60  #define REG_ISI_DMA_C_ADDR (0x4004C050U)
61  #define REG_ISI_DMA_C_CTRL (0x4004C054U)
62  #define REG_ISI_DMA_C_DSCR (0x4004C058U)
63  #define REG_ISI_WPMR (0x4004C0E4U)
64  #define REG_ISI_WPSR (0x4004C0E8U)
65  #define REG_ISI_VERSION (0x4004C0FCU)
66 #else
67  #define REG_ISI_CFG1 (*(__IO uint32_t*)0x4004C000U)
68  #define REG_ISI_CFG2 (*(__IO uint32_t*)0x4004C004U)
69  #define REG_ISI_PSIZE (*(__IO uint32_t*)0x4004C008U)
70  #define REG_ISI_PDECF (*(__IO uint32_t*)0x4004C00CU)
71  #define REG_ISI_Y2R_SET0 (*(__IO uint32_t*)0x4004C010U)
72  #define REG_ISI_Y2R_SET1 (*(__IO uint32_t*)0x4004C014U)
73  #define REG_ISI_R2Y_SET0 (*(__IO uint32_t*)0x4004C018U)
74  #define REG_ISI_R2Y_SET1 (*(__IO uint32_t*)0x4004C01CU)
75  #define REG_ISI_R2Y_SET2 (*(__IO uint32_t*)0x4004C020U)
76  #define REG_ISI_CR (*(__O uint32_t*)0x4004C024U)
77  #define REG_ISI_SR (*(__I uint32_t*)0x4004C028U)
78  #define REG_ISI_IER (*(__O uint32_t*)0x4004C02CU)
79  #define REG_ISI_IDR (*(__O uint32_t*)0x4004C030U)
80  #define REG_ISI_IMR (*(__I uint32_t*)0x4004C034U)
81  #define REG_ISI_DMA_CHER (*(__O uint32_t*)0x4004C038U)
82  #define REG_ISI_DMA_CHDR (*(__O uint32_t*)0x4004C03CU)
83  #define REG_ISI_DMA_CHSR (*(__I uint32_t*)0x4004C040U)
84  #define REG_ISI_DMA_P_ADDR (*(__IO uint32_t*)0x4004C044U)
85  #define REG_ISI_DMA_P_CTRL (*(__IO uint32_t*)0x4004C048U)
86  #define REG_ISI_DMA_P_DSCR (*(__IO uint32_t*)0x4004C04CU)
87  #define REG_ISI_DMA_C_ADDR (*(__IO uint32_t*)0x4004C050U)
88  #define REG_ISI_DMA_C_CTRL (*(__IO uint32_t*)0x4004C054U)
89  #define REG_ISI_DMA_C_DSCR (*(__IO uint32_t*)0x4004C058U)
90  #define REG_ISI_WPMR (*(__IO uint32_t*)0x4004C0E4U)
91  #define REG_ISI_WPSR (*(__I uint32_t*)0x4004C0E8U)
92  #define REG_ISI_VERSION (*(__I uint32_t*)0x4004C0FCU)
93 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
94 
95 #endif /* _SAME70_ISI_INSTANCE_ */


inertial_sense_ros
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autogenerated on Sat Sep 19 2020 03:19:04