usb_hcd_int.c
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1 
28 /* Includes ------------------------------------------------------------------*/
29 #include "usb_core.h"
30 #include "usb_defines.h"
31 #include "usb_hcd_int.h"
32 
33 #if defined (__CC_ARM)
34 #pragma O0
35 #elif defined (__GNUC__)
36 #pragma GCC optimize ("O0")
37 #elif defined (__TASKING__)
38 #pragma optimize=0
39 
40 #endif /* __CC_ARM */
41 
91 static uint32_t USB_OTG_USBH_handle_hc_ISR (USB_OTG_CORE_HANDLE *pdev);
93  uint32_t num);
95  uint32_t num);
101 
119 {
120  USB_OTG_GINTSTS_TypeDef gintsts;
121  uint32_t retval = 0;
122 
123  gintsts.d32 = 0;
124 
125  /* Check if HOST Mode */
126  if (USB_OTG_IsHostMode(pdev))
127  {
128  gintsts.d32 = USB_OTG_ReadCoreItr(pdev);
129  if (!gintsts.d32)
130  {
131  return 0;
132  }
133 
134  if (gintsts.b.sofintr)
135  {
136  retval |= USB_OTG_USBH_handle_sof_ISR (pdev);
137  }
138 
139  if (gintsts.b.rxstsqlvl)
140  {
141  retval |= USB_OTG_USBH_handle_rx_qlvl_ISR (pdev);
142  }
143 
144  if (gintsts.b.nptxfempty)
145  {
146  retval |= USB_OTG_USBH_handle_nptxfempty_ISR (pdev);
147  }
148 
149  if (gintsts.b.ptxfempty)
150  {
151  retval |= USB_OTG_USBH_handle_ptxfempty_ISR (pdev);
152  }
153 
154  if (gintsts.b.hcintr)
155  {
156  retval |= USB_OTG_USBH_handle_hc_ISR (pdev);
157  }
158 
159  if (gintsts.b.portintr)
160  {
161  retval |= USB_OTG_USBH_handle_port_ISR (pdev);
162  }
163 
164  if (gintsts.b.disconnect)
165  {
166  retval |= USB_OTG_USBH_handle_Disconnect_ISR (pdev);
167 
168  }
169 
170  if (gintsts.b.incomplisoout)
171  {
173  }
174 
175 
176  }
177  return retval;
178 }
179 
187 {
188  USB_OTG_HAINT_TypeDef haint;
189  USB_OTG_HCCHAR_TypeDef hcchar;
190  uint32_t i = 0;
191  uint32_t retval = 0;
192 
193  /* Clear appropriate bits in HCINTn to clear the interrupt bit in
194  * GINTSTS */
195 
196  haint.d32 = USB_OTG_ReadHostAllChannels_intr(pdev);
197 
198  for (i = 0; i < pdev->cfg.host_channels ; i++)
199  {
200  if (haint.b.chint & (1 << i))
201  {
202  hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[i]->HCCHAR);
203 
204  if (hcchar.b.epdir)
205  {
206  retval |= USB_OTG_USBH_handle_hc_n_In_ISR (pdev, i);
207  }
208  else
209  {
210  retval |= USB_OTG_USBH_handle_hc_n_Out_ISR (pdev, i);
211  }
212  }
213  }
214 
215  return retval;
216 }
217 
225 {
226  USB_OTG_GINTSTS_TypeDef gintsts;
227  gintsts.d32 = 0;
228 
229  USBH_HCD_INT_fops->SOF(pdev);
230 
231  /* Clear interrupt */
232  gintsts.b.sofintr = 1;
233  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
234 
235  return 1;
236 }
237 
245 {
246  USB_OTG_GINTSTS_TypeDef gintsts;
247 
248  gintsts.d32 = 0;
249 
251 
252  /* Clear interrupt */
253  gintsts.b.disconnect = 1;
254  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
255 
256  return 1;
257 }
258 #if defined ( __ICCARM__ )
259 #pragma optimize = none
260 #endif /* __CC_ARM */
261 
268 {
270  USB_OTG_HNPTXSTS_TypeDef hnptxsts;
271  uint16_t len_words , len;
272 
273  hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS);
274 
275  len_words = (pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len + 3) / 4;
276 
277  while ((hnptxsts.b.nptxfspcavail > len_words)&&
278  (pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len != 0))
279  {
280 
281  len = hnptxsts.b.nptxfspcavail * 4;
282 
283  if (len > pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len)
284  {
285  /* Last packet */
286  len = pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len;
287 
288  intmsk.d32 = 0;
289  intmsk.b.nptxfempty = 1;
290  USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0);
291  }
292 
293  len_words = (pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len + 3) / 4;
294 
295  USB_OTG_WritePacket (pdev , pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_buff, hnptxsts.b.nptxqtop.chnum, len);
296 
297  pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_buff += len;
298  pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len -= len;
299  pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_count += len;
300 
301  hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS);
302  }
303 
304  return 1;
305 }
306 #if defined ( __ICCARM__ )
307 #pragma optimize = none
308 #endif /* __CC_ARM */
309 
316 {
318  USB_OTG_HPTXSTS_TypeDef hptxsts;
319  uint16_t len_words , len;
320 
321  hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS);
322 
323  len_words = (pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len + 3) / 4;
324 
325  while ((hptxsts.b.ptxfspcavail > len_words)&&
326  (pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len != 0))
327  {
328 
329  len = hptxsts.b.ptxfspcavail * 4;
330 
331  if (len > pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len)
332  {
333  len = pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len;
334  /* Last packet */
335  intmsk.d32 = 0;
336  intmsk.b.ptxfempty = 1;
337  USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0);
338  }
339 
340  len_words = (pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len + 3) / 4;
341 
342  USB_OTG_WritePacket (pdev , pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_buff, hptxsts.b.ptxqtop.chnum, len);
343 
344  pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_buff += len;
345  pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len -= len;
346  pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_count += len;
347 
348  hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS);
349  }
350 
351  return 1;
352 }
353 
360 #if defined ( __ICCARM__ )
361 #pragma optimize = none
362 #endif /* __CC_ARM */
364 {
365  USB_OTG_HPRT0_TypeDef hprt0;
366  USB_OTG_HPRT0_TypeDef hprt0_dup;
367  USB_OTG_HCFG_TypeDef hcfg;
368  uint32_t retval = 0;
370 
371  intmsk.d32 = 0;
372  hcfg.d32 = 0;
373  hprt0.d32 = 0;
374  hprt0_dup.d32 = 0;
375 
376  hprt0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0);
377  hprt0_dup.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0);
378 
379  /* Clear the interrupt bits in GINTSTS */
380 
381  hprt0_dup.b.prtena = 0;
382  hprt0_dup.b.prtconndet = 0;
383  hprt0_dup.b.prtenchng = 0;
384  hprt0_dup.b.prtovrcurrchng = 0;
385 
386  /* Port Connect Detected */
387  if (hprt0.b.prtconndet)
388  {
389  hprt0_dup.b.prtconndet = 1;
391  retval |= 1;
392  }
393 
394  /* Port Enable Changed */
395  if (hprt0.b.prtenchng)
396  {
397  hprt0_dup.b.prtenchng = 1;
398 
399  if (hprt0.b.prtena == 1)
400  {
401  if ((hprt0.b.prtspd == HPRT0_PRTSPD_LOW_SPEED) ||
402  (hprt0.b.prtspd == HPRT0_PRTSPD_FULL_SPEED))
403  {
404  hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG);
405 
406  if (hprt0.b.prtspd == HPRT0_PRTSPD_LOW_SPEED)
407  {
408  USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HFIR, 6000 );
409  if (hcfg.b.fslspclksel != HCFG_6_MHZ)
410  {
411  if(pdev->cfg.phy_itface == USB_OTG_EMBEDDED_PHY)
412  {
413  USB_OTG_InitFSLSPClkSel(pdev , HCFG_6_MHZ);
414  }
415 
416  else
417  {
418  USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HFIR, 48000 );
419  if (hcfg.b.fslspclksel != HCFG_48_MHZ)
420  {
421  USB_OTG_InitFSLSPClkSel(pdev ,HCFG_48_MHZ );
422  }
423  }
424  }
425  }
426  }
427 
429 
430  /*unmask disconnect interrupt */
431  intmsk.d32 = 0;
432  intmsk.b.disconnect = 1;
433  USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32);
434  }
435  else
436  {
438 
439  }
440  }
441 
442  /* Overcurrent Change Interrupt */
443  if (hprt0.b.prtovrcurrchng)
444  {
445  hprt0_dup.b.prtovrcurrchng = 1;
446  retval |= 1;
447  }
448 
449  /* Clear Port Interrupts */
450  USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0_dup.d32);
451 
452  return retval;
453 }
454 #if defined ( __ICCARM__ )
455 #pragma optimize = none
456 #endif /* __CC_ARM */
457 
465 {
466 
468  USB_OTG_HCINTMSK_TypeDef hcintmsk;
469  USB_OTG_HC_REGS *hcreg;
470  USB_OTG_HCCHAR_TypeDef hcchar;
471 
472  hcreg = pdev->regs.HC_REGS[num];
473  hcint.d32 = USB_OTG_READ_REG32(&hcreg->HCINT);
474  hcintmsk.d32 = USB_OTG_READ_REG32(&hcreg->HCINTMSK);
475  hcint.d32 = hcint.d32 & hcintmsk.d32;
476 
477  hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCCHAR);
478 
479  if (hcint.b.ahberr)
480  {
481  CLEAR_HC_INT(hcreg ,ahberr);
482  UNMASK_HOST_INT_CHH (num);
483  }
484  else if (hcint.b.ack)
485  {
486  CLEAR_HC_INT(hcreg , ack);
487  }
488  else if (hcint.b.frmovrun)
489  {
490  UNMASK_HOST_INT_CHH (num);
491  USB_OTG_HC_Halt(pdev, num);
492  CLEAR_HC_INT(hcreg ,frmovrun);
493  }
494  else if (hcint.b.xfercompl)
495  {
496  pdev->host.ErrCnt[num] = 0;
497  UNMASK_HOST_INT_CHH (num);
498  USB_OTG_HC_Halt(pdev, num);
499  CLEAR_HC_INT(hcreg , xfercompl);
500  pdev->host.HC_Status[num] = HC_XFRC;
501  }
502 
503  else if (hcint.b.stall)
504  {
505  CLEAR_HC_INT(hcreg , stall);
506  UNMASK_HOST_INT_CHH (num);
507  USB_OTG_HC_Halt(pdev, num);
508  pdev->host.HC_Status[num] = HC_STALL;
509  }
510 
511  else if (hcint.b.nak)
512  {
513  pdev->host.ErrCnt[num] = 0;
514  UNMASK_HOST_INT_CHH (num);
515  if (pdev->cfg.dma_enable == 0)
516  {
517  USB_OTG_HC_Halt(pdev, num);
518  }
519  CLEAR_HC_INT(hcreg , nak);
520  pdev->host.HC_Status[num] = HC_NAK;
521  }
522 
523  else if (hcint.b.xacterr)
524  {
525  UNMASK_HOST_INT_CHH (num);
526  USB_OTG_HC_Halt(pdev, num);
527  pdev->host.HC_Status[num] = HC_XACTERR;
528  CLEAR_HC_INT(hcreg , xacterr);
529  }
530  else if (hcint.b.nyet)
531  {
532  pdev->host.ErrCnt[num] = 0;
533  UNMASK_HOST_INT_CHH (num);
534  if (pdev->cfg.dma_enable == 0)
535  {
536  USB_OTG_HC_Halt(pdev, num);
537  }
538  CLEAR_HC_INT(hcreg , nyet);
539  pdev->host.HC_Status[num] = HC_NYET;
540  }
541  else if (hcint.b.datatglerr)
542  {
543  UNMASK_HOST_INT_CHH (num);
544  USB_OTG_HC_Halt(pdev, num);
545  CLEAR_HC_INT(hcreg , nak);
546  pdev->host.HC_Status[num] = HC_DATATGLERR;
547 
548  CLEAR_HC_INT(hcreg , datatglerr);
549  }
550  else if (hcint.b.chhltd)
551  {
552  MASK_HOST_INT_CHH (num);
553 
554  if(pdev->host.HC_Status[num] == HC_XFRC)
555  {
556  pdev->host.URB_State[num] = URB_DONE;
557 
558  if (hcchar.b.eptype == EP_TYPE_BULK)
559  {
560  pdev->host.hc[num].toggle_out ^= 1;
561  }
562  }
563  else if(pdev->host.HC_Status[num] == HC_NAK)
564  {
565  pdev->host.URB_State[num] = URB_NOTREADY;
566  }
567  else if(pdev->host.HC_Status[num] == HC_NYET)
568  {
569  if(pdev->host.hc[num].do_ping == 1)
570  {
571  USB_OTG_HC_DoPing(pdev, num);
572  }
573  pdev->host.URB_State[num] = URB_NOTREADY;
574  }
575  else if(pdev->host.HC_Status[num] == HC_STALL)
576  {
577  pdev->host.URB_State[num] = URB_STALL;
578  }
579  else if(pdev->host.HC_Status[num] == HC_XACTERR)
580  {
581  {
582  pdev->host.URB_State[num] = URB_ERROR;
583  }
584  }
585  CLEAR_HC_INT(hcreg , chhltd);
586  }
587 
588 
589  return 1;
590 }
591 #if defined ( __ICCARM__ )
592 #pragma optimize = none
593 #endif /* __CC_ARM */
594 
602 {
604  USB_OTG_HCINTMSK_TypeDef hcintmsk;
605  USB_OTG_HCCHAR_TypeDef hcchar;
607  USB_OTG_HC_REGS *hcreg;
608 
609  hcreg = pdev->regs.HC_REGS[num];
610  hcint.d32 = USB_OTG_READ_REG32(&hcreg->HCINT);
611  hcintmsk.d32 = USB_OTG_READ_REG32(&hcreg->HCINTMSK);
612  hcint.d32 = hcint.d32 & hcintmsk.d32;
613  hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCCHAR);
614  hcintmsk.d32 = 0;
615 
616  if (hcint.b.ahberr)
617  {
618  CLEAR_HC_INT(hcreg ,ahberr);
619  UNMASK_HOST_INT_CHH (num);
620  }
621  else if (hcint.b.ack)
622  {
623  CLEAR_HC_INT(hcreg ,ack);
624  }
625 
626  else if (hcint.b.stall)
627  {
628  UNMASK_HOST_INT_CHH (num);
629  pdev->host.HC_Status[num] = HC_STALL;
630  CLEAR_HC_INT(hcreg , nak); /* Clear the NAK Condition */
631  CLEAR_HC_INT(hcreg , stall); /* Clear the STALL Condition */
632  hcint.b.nak = 0; /* NOTE: When there is a 'stall', reset also nak,
633  else, the pdev->host.HC_Status = HC_STALL
634  will be overwritten by 'nak' in code below */
635  USB_OTG_HC_Halt(pdev, num);
636  }
637  else if (hcint.b.datatglerr)
638  {
639  UNMASK_HOST_INT_CHH (num);
640  USB_OTG_HC_Halt(pdev, num);
641  CLEAR_HC_INT(hcreg , nak);
642  pdev->host.HC_Status[num] = HC_DATATGLERR;
643  CLEAR_HC_INT(hcreg , datatglerr);
644  }
645 
646  if (hcint.b.frmovrun)
647  {
648  UNMASK_HOST_INT_CHH (num);
649  USB_OTG_HC_Halt(pdev, num);
650  CLEAR_HC_INT(hcreg ,frmovrun);
651  }
652 
653  else if (hcint.b.xfercompl)
654  {
655  if (pdev->cfg.dma_enable == 1)
656  {
657  hctsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCTSIZ);
658  pdev->host.XferCnt[num] = pdev->host.hc[num].xfer_len - hctsiz.b.xfersize;
659  }
660 
661  pdev->host.HC_Status[num] = HC_XFRC;
662  pdev->host.ErrCnt [num]= 0;
663  CLEAR_HC_INT(hcreg , xfercompl);
664 
665  if ((hcchar.b.eptype == EP_TYPE_CTRL)||
666  (hcchar.b.eptype == EP_TYPE_BULK))
667  {
668  UNMASK_HOST_INT_CHH (num);
669  USB_OTG_HC_Halt(pdev, num);
670  CLEAR_HC_INT(hcreg , nak);
671  pdev->host.hc[num].toggle_in ^= 1;
672 
673  }
674  else if(hcchar.b.eptype == EP_TYPE_INTR)
675  {
676  hcchar.b.oddfrm = 1;
677  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[num]->HCCHAR, hcchar.d32);
678  pdev->host.URB_State[num] = URB_DONE;
679  }
680  }
681  else if (hcint.b.chhltd)
682  {
683  MASK_HOST_INT_CHH (num);
684 
685  if(pdev->host.HC_Status[num] == HC_XFRC)
686  {
687  pdev->host.URB_State[num] = URB_DONE;
688  }
689 
690  else if (pdev->host.HC_Status[num] == HC_STALL)
691  {
692  pdev->host.URB_State[num] = URB_STALL;
693  }
694 
695  else if((pdev->host.HC_Status[num] == HC_XACTERR) ||
696  (pdev->host.HC_Status[num] == HC_DATATGLERR))
697  {
698  pdev->host.ErrCnt[num] = 0;
699  pdev->host.URB_State[num] = URB_ERROR;
700 
701  }
702  else if(hcchar.b.eptype == EP_TYPE_INTR)
703  {
704  pdev->host.hc[num].toggle_in ^= 1;
705  }
706 
707  CLEAR_HC_INT(hcreg , chhltd);
708 
709  }
710  else if (hcint.b.xacterr)
711  {
712  UNMASK_HOST_INT_CHH (num);
713  pdev->host.HC_Status[num] = HC_XACTERR;
714  USB_OTG_HC_Halt(pdev, num);
715  CLEAR_HC_INT(hcreg , xacterr);
716  }
717  else if (hcint.b.nak)
718  {
719  if(hcchar.b.eptype == EP_TYPE_INTR)
720  {
721  UNMASK_HOST_INT_CHH (num);
722  if (pdev->cfg.dma_enable == 0)
723  {
724  USB_OTG_HC_Halt(pdev, num);
725  }
726  }
727 
728  pdev->host.HC_Status[num] = HC_NAK;
729  CLEAR_HC_INT(hcreg , nak);
730 
731  if ((hcchar.b.eptype == EP_TYPE_CTRL)||
732  (hcchar.b.eptype == EP_TYPE_BULK))
733  {
734  /* re-activate the channel */
735  hcchar.b.chen = 1;
736  hcchar.b.chdis = 0;
737  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[num]->HCCHAR, hcchar.d32);
738  }
739  }
740 
741 
742  return 1;
743 
744 }
745 
752 #if defined ( __ICCARM__ )
753 #pragma optimize = none
754 #endif /* __CC_ARM */
756 {
759  USB_OTG_HCTSIZn_TypeDef hctsiz;
760  USB_OTG_HCCHAR_TypeDef hcchar;
761  __IO uint8_t channelnum =0;
762  uint32_t count;
763 
764  /* Disable the Rx Status Queue Level interrupt */
765  intmsk.d32 = 0;
766  intmsk.b.rxstsqlvl = 1;
767  USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0);
768 
769  grxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRXSTSP);
770  channelnum = grxsts.b.chnum;
771  hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[channelnum]->HCCHAR);
772 
773  switch (grxsts.b.pktsts)
774  {
775  case GRXSTS_PKTSTS_IN:
776  /* Read the data into the host buffer. */
777  if ((grxsts.b.bcnt > 0) && (pdev->host.hc[channelnum].xfer_buff != (void *)0))
778  {
779 
780  USB_OTG_ReadPacket(pdev, pdev->host.hc[channelnum].xfer_buff, grxsts.b.bcnt);
781  /*manage multiple Xfer */
782  pdev->host.hc[grxsts.b.chnum].xfer_buff += grxsts.b.bcnt;
783  pdev->host.hc[grxsts.b.chnum].xfer_count += grxsts.b.bcnt;
784 
785 
786  count = pdev->host.hc[channelnum].xfer_count;
787  pdev->host.XferCnt[channelnum] = count;
788 
789  hctsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[channelnum]->HCTSIZ);
790  if(hctsiz.b.pktcnt > 0)
791  {
792  /* re-activate the channel when more packets are expected */
793  hcchar.b.chen = 1;
794  hcchar.b.chdis = 0;
795  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[channelnum]->HCCHAR, hcchar.d32);
796  }
797  }
798  break;
799 
801 
804  default:
805  break;
806  }
807 
808  /* Enable the Rx Status Queue Level interrupt */
809  intmsk.b.rxstsqlvl = 1;
810  USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, 0, intmsk.d32);
811  return 1;
812 }
813 
820 #if defined ( __ICCARM__ )
821 #pragma optimize = none
822 #endif /* __CC_ARM */
824 {
825 
826  USB_OTG_GINTSTS_TypeDef gintsts;
827  USB_OTG_HCCHAR_TypeDef hcchar;
828 
829 
830 
831 
832  hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[0]->HCCHAR);
833  hcchar.b.chen = 1;
834  hcchar.b.chdis = 1;
835  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[0]->HCCHAR, hcchar.d32);
836 
837  gintsts.d32 = 0;
838  /* Clear interrupt */
839  gintsts.b.incomplisoout = 1;
840  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
841 
842  return 1;
843 }
844 
857 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
858 
static uint32_t USB_OTG_USBH_handle_port_ISR(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_USBH_handle_port_ISR This function determines which interrupt conditions have occurred...
Definition: usb_hcd_int.c:363
#define HPRT0_PRTSPD_FULL_SPEED
Definition: usb_defines.h:165
struct _USB_OTG_HPTXSTS_TypeDef::@86 b
uint8_t phy_itface
Definition: usb_core.h:170
struct _USB_OTG_HCFG_TypeDef::@83 b
struct _USB_OTG_HAINT_TypeDef::@89 b
USBH_HCD_INT_cb_TypeDef * USBH_HCD_INT_fops
__IO uint32_t HCINT
Definition: usb_regs.h:207
uint8_t(* DevPortEnabled)(USB_OTG_CORE_HANDLE *pdev)
Definition: usb_hcd_int.h:63
uint8_t(* SOF)(USB_OTG_CORE_HANDLE *pdev)
Definition: usb_hcd_int.h:60
uint32_t fslspclksel
Definition: usb_regs.h:885
static uint32_t USB_OTG_USBH_handle_hc_n_Out_ISR(USB_OTG_CORE_HANDLE *pdev, uint32_t num)
USB_OTG_USBH_handle_hc_n_Out_ISR Handles interrupt for a specific Host Channel.
Definition: usb_hcd_int.c:464
struct _USB_OTG_GINTMSK_TypeDef::@64 b
__IO uint32_t HFIR
Definition: usb_regs.h:187
static uint32_t USB_OTG_USBH_handle_hc_ISR(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_USBH_handle_hc_ISR This function indicates that one or more host channels has a pending...
Definition: usb_hcd_int.c:186
#define EP_TYPE_CTRL
Definition: usb_defines.h:140
__IO uint32_t GINTMSK
Definition: usb_regs.h:91
struct _USB_OTG_GINTSTS_TypeDef::@65 b
static uint32_t USB_OTG_USBH_handle_ptxfempty_ISR(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_USBH_handle_ptxfempty_ISR Handles periodic tx fifo empty.
Definition: usb_hcd_int.c:315
uint8_t(* DevDisconnected)(USB_OTG_CORE_HANDLE *pdev)
Definition: usb_hcd_int.h:62
#define EP_TYPE_BULK
Definition: usb_defines.h:142
static uint32_t USB_OTG_USBH_handle_sof_ISR(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_otg_hcd_handle_sof_intr Handles the start-of-frame interrupt in host mode.
Definition: usb_hcd_int.c:224
USB_OTG_CORE_CFGS cfg
Definition: usb_core.h:289
static uint32_t USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR Handles the incomplete Periodic transfer Interrupt...
Definition: usb_hcd_int.c:823
uint32_t prtovrcurrchng
Definition: usb_regs.h:955
struct _USB_OTG_HPRT0_TypeDef::@88 b
#define HPRT0_PRTSPD_LOW_SPEED
Definition: usb_defines.h:166
static uint32_t USB_OTG_USBH_handle_Disconnect_ISR(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_USBH_handle_Disconnect_ISR Handles disconnect event.
Definition: usb_hcd_int.c:244
uint8_t host_channels
Definition: usb_core.h:164
#define __IO
Definition: core_cm0.h:198
uint8_t(* DevConnected)(USB_OTG_CORE_HANDLE *pdev)
Definition: usb_hcd_int.h:61
#define USB_OTG_WRITE_REG32(reg, value)
Definition: usb_defines.h:226
uint32_t USBH_OTG_ISR_Handler(USB_OTG_CORE_HANDLE *pdev)
HOST_Handle_ISR This function handles all USB Host Interrupts.
Definition: usb_hcd_int.c:118
__IO uint32_t HNPTXSTS
Definition: usb_regs.h:96
__IO uint32_t HCFG
Definition: usb_regs.h:186
struct _USB_OTG_HCTSIZn_TypeDef::@94 b
__IO uint32_t HCINTMSK
Definition: usb_regs.h:208
__IO uint32_t GRXSTSP
Definition: usb_regs.h:93
#define MASK_HOST_INT_CHH(hc_num)
Definition: usb_hcd_int.h:86
#define USB_OTG_READ_REG32(reg)
Definition: usb_defines.h:225
USB_OTG_GREGS * GREGS
Definition: usb_regs.h:224
#define USB_OTG_EMBEDDED_PHY
Definition: usb_defines.h:65
__IO uint32_t HPTXSTS
Definition: usb_regs.h:190
#define EP_TYPE_INTR
Definition: usb_defines.h:143
uint8_t(* DevPortDisabled)(USB_OTG_CORE_HANDLE *pdev)
Definition: usb_hcd_int.h:64
__IO uint32_t HCCHAR
Definition: usb_regs.h:205
void * USB_OTG_ReadPacket(USB_OTG_CORE_HANDLE *pdev, uint8_t *dest, uint16_t len)
USB_OTG_ReadPacket : Reads a packet from the Rx FIFO.
Definition: usb_core.c:198
Header of the Core Layer.
struct _USB_OTG_HNPTXSTS_TypeDef::@69 b
#define HCFG_48_MHZ
Definition: usb_defines.h:169
__IO uint32_t GINTSTS
Definition: usb_regs.h:90
uint8_t dma_enable
Definition: usb_core.h:167
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR
Definition: usb_defines.h:88
#define CLEAR_HC_INT(HC_REGS, intr)
Definition: usb_hcd_int.h:78
__IO uint32_t HCTSIZ
Definition: usb_regs.h:209
uint32_t USB_OTG_ReadCoreItr(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_ReadCoreItr : returns the Core Interrupt register.
Definition: usb_core.c:609
struct _USB_OTG_HNPTXSTS_TypeDef::@69::@70 nptxqtop
struct _USB_OTG_HPTXSTS_TypeDef::@86::@87 ptxqtop
#define GRXSTS_PKTSTS_IN
Definition: usb_defines.h:86
Header of the Core Layer.
Peripheral Device Interface Layer.
static uint32_t USB_OTG_USBH_handle_hc_n_In_ISR(USB_OTG_CORE_HANDLE *pdev, uint32_t num)
USB_OTG_USBH_handle_hc_n_In_ISR Handles interrupt for a specific Host Channel.
Definition: usb_hcd_int.c:601
#define UNMASK_HOST_INT_CHH(hc_num)
Definition: usb_hcd_int.h:91
#define GRXSTS_PKTSTS_IN_XFER_COMP
Definition: usb_defines.h:87
static uint32_t USB_OTG_USBH_handle_rx_qlvl_ISR(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_USBH_handle_rx_qlvl_ISR Handles the Rx Status Queue Level Interrupt.
Definition: usb_hcd_int.c:755
#define HCFG_6_MHZ
Definition: usb_defines.h:170
struct _USB_OTG_GRXSTS_TypeDef::@67 b
uint8_t USB_OTG_IsHostMode(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_IsHostMode : Check if it is host mode.
Definition: usb_core.c:598
USB_OTG_CORE_REGS regs
Definition: usb_core.h:290
#define GRXSTS_PKTSTS_CH_HALTED
Definition: usb_defines.h:89
__IO uint32_t * HPRT0
Definition: usb_regs.h:230
USB_OTG_HC_REGS * HC_REGS[USB_OTG_MAX_TX_FIFOS]
Definition: usb_regs.h:229
USB_OTG_HREGS * HREGS
Definition: usb_regs.h:226
#define USB_OTG_MODIFY_REG32(reg, clear_mask, set_mask)
Definition: usb_defines.h:227
USB_OTG_STS USB_OTG_WritePacket(USB_OTG_CORE_HANDLE *pdev, uint8_t *src, uint8_t ch_ep_num, uint16_t len)
USB_OTG_WritePacket : Writes a packet into the Tx FIFO associated with the EP.
Definition: usb_core.c:168
static uint32_t USB_OTG_USBH_handle_nptxfempty_ISR(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_USBH_handle_nptxfempty_ISR Handles non periodic tx fifo empty.
Definition: usb_hcd_int.c:267
struct _USB_OTG_HCCHAR_TypeDef::@91 b
struct _USB_OTG_HCINTn_TypeDef::@93 b


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:20