usb_dcd.c
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1 
28 /* Includes ------------------------------------------------------------------*/
29 #include "usb_dcd.h"
30 #include "usb_bsp.h"
31 
32 
93 {
94  uint32_t i;
95  USB_OTG_EP *ep;
96 
97  USB_OTG_SelectCore (pdev , coreID);
98 
99  pdev->dev.device_status = USB_OTG_DEFAULT;
100  pdev->dev.device_address = 0;
101 
102  /* Init ep structure */
103  for (i = 0; i < pdev->cfg.dev_endpoints ; i++)
104  {
105  ep = &pdev->dev.in_ep[i];
106  /* Init ep structure */
107  ep->is_in = 1;
108  ep->num = i;
109  ep->tx_fifo_num = i;
110  /* Control until ep is activated */
111  ep->type = EP_TYPE_CTRL;
113  ep->xfer_buff = 0;
114  ep->xfer_len = 0;
115  }
116 
117  for (i = 0; i < pdev->cfg.dev_endpoints; i++)
118  {
119  ep = &pdev->dev.out_ep[i];
120  /* Init ep structure */
121  ep->is_in = 0;
122  ep->num = i;
123  ep->tx_fifo_num = i;
124  /* Control until ep is activated */
125  ep->type = EP_TYPE_CTRL;
127  ep->xfer_buff = 0;
128  ep->xfer_len = 0;
129  }
130 
132 
133 #if defined (STM32F446xx) || defined (STM32F469_479xx)
134 
135  /* Force Device Mode*/
137 
138  /*Init the Core (common init.) */
139  USB_OTG_CoreInit(pdev);
140 
141 #else
142 
143  /*Init the Core (common init.) */
144  USB_OTG_CoreInit(pdev);
145 
146  /* Force Device Mode*/
148 
149 #endif
150 
151  /* Init Device */
152  USB_OTG_CoreInitDev(pdev);
153 
154  /* Enable USB Global interrupt */
156 }
157 
158 
166  uint8_t ep_addr,
167  uint16_t ep_mps,
168  uint8_t ep_type)
169 {
170  USB_OTG_EP *ep;
171 
172  if ((ep_addr & 0x80) == 0x80)
173  {
174  ep = &pdev->dev.in_ep[ep_addr & 0x7F];
175  }
176  else
177  {
178  ep = &pdev->dev.out_ep[ep_addr & 0x7F];
179  }
180  ep->num = ep_addr & 0x7F;
181 
182  ep->is_in = (0x80 & ep_addr) != 0;
183  ep->maxpacket = ep_mps;
184  ep->type = ep_type;
185  if (ep->is_in)
186  {
187  /* Assign a Tx FIFO */
188  ep->tx_fifo_num = ep->num;
189  }
190  /* Set initial data PID. */
191  if (ep_type == USB_OTG_EP_BULK )
192  {
193  ep->data_pid_start = 0;
194  }
195  USB_OTG_EPActivate(pdev , ep );
196  return 0;
197 }
204 uint32_t DCD_EP_Close(USB_OTG_CORE_HANDLE *pdev , uint8_t ep_addr)
205 {
206  USB_OTG_EP *ep;
207 
208  if ((ep_addr&0x80) == 0x80)
209  {
210  ep = &pdev->dev.in_ep[ep_addr & 0x7F];
211  }
212  else
213  {
214  ep = &pdev->dev.out_ep[ep_addr & 0x7F];
215  }
216  ep->num = ep_addr & 0x7F;
217  ep->is_in = (0x80 & ep_addr) != 0;
218  USB_OTG_EPDeactivate(pdev , ep );
219  return 0;
220 }
221 
222 
232  uint8_t ep_addr,
233  uint8_t *pbuf,
234  uint16_t buf_len)
235 {
236  USB_OTG_EP *ep;
237 
238  ep = &pdev->dev.out_ep[ep_addr & 0x7F];
239 
240  /*setup and start the Xfer */
241  ep->xfer_buff = pbuf;
242  ep->xfer_len = buf_len;
243  ep->xfer_count = 0;
244  ep->is_in = 0;
245  ep->num = ep_addr & 0x7F;
246 
247  if (pdev->cfg.dma_enable == 1)
248  {
249  ep->dma_addr = (uint32_t)pbuf;
250  }
251 
252  if ( ep->num == 0 )
253  {
254  USB_OTG_EP0StartXfer(pdev , ep);
255  }
256  else
257  {
258  USB_OTG_EPStartXfer(pdev, ep );
259  }
260  return 0;
261 }
262 
272  uint8_t ep_addr,
273  uint8_t *pbuf,
274  uint32_t buf_len)
275 {
276  USB_OTG_EP *ep;
277 
278  ep = &pdev->dev.in_ep[ep_addr & 0x7F];
279 
280  /* Setup and start the Transfer */
281  ep->is_in = 1;
282  ep->num = ep_addr & 0x7F;
283  ep->xfer_buff = pbuf;
284  ep->dma_addr = (uint32_t)pbuf;
285  ep->xfer_count = 0;
286  ep->xfer_len = buf_len;
287 
288  if ( ep->num == 0 )
289  {
290  USB_OTG_EP0StartXfer(pdev , ep);
291  }
292  else
293  {
294  USB_OTG_EPStartXfer(pdev, ep );
295  }
296  return 0;
297 }
298 
299 
306 uint32_t DCD_EP_Stall (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum)
307 {
308  USB_OTG_EP *ep;
309  if ((0x80 & epnum) == 0x80)
310  {
311  ep = &pdev->dev.in_ep[epnum & 0x7F];
312  }
313  else
314  {
315  ep = &pdev->dev.out_ep[epnum];
316  }
317 
318  ep->is_stall = 1;
319  ep->num = epnum & 0x7F;
320  ep->is_in = ((epnum & 0x80) == 0x80);
321 
322  USB_OTG_EPSetStall(pdev , ep);
323  return (0);
324 }
325 
326 
333 uint32_t DCD_EP_ClrStall (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum)
334 {
335  USB_OTG_EP *ep;
336  if ((0x80 & epnum) == 0x80)
337  {
338  ep = &pdev->dev.in_ep[epnum & 0x7F];
339  }
340  else
341  {
342  ep = &pdev->dev.out_ep[epnum];
343  }
344 
345  ep->is_stall = 0;
346  ep->num = epnum & 0x7F;
347  ep->is_in = ((epnum & 0x80) == 0x80);
348 
349  USB_OTG_EPClearStall(pdev , ep);
350  return (0);
351 }
352 
353 
360 uint32_t DCD_EP_Flush (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum)
361 {
362 
363  if ((epnum & 0x80) == 0x80)
364  {
365  USB_OTG_FlushTxFifo(pdev, epnum & 0x7F);
366  }
367  else
368  {
369  USB_OTG_FlushRxFifo(pdev);
370  }
371 
372  return (0);
373 }
374 
375 
382 void DCD_EP_SetAddress (USB_OTG_CORE_HANDLE *pdev, uint8_t address)
383 {
385  dcfg.d32 = 0;
386  dcfg.b.devaddr = address;
387  USB_OTG_MODIFY_REG32( &pdev->regs.DREGS->DCFG, 0, dcfg.d32);
388 }
389 
396 {
397 #ifndef USE_OTG_MODE
399  dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL);
400  /* Connect device */
401  dctl.b.sftdiscon = 0;
402  USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32);
404 #endif
405 }
406 
407 
414 {
415 #ifndef USE_OTG_MODE
417  dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL);
418  /* Disconnect device for 3ms */
419  dctl.b.sftdiscon = 1;
420  USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32);
422 #endif
423 }
424 
425 
433 uint32_t DCD_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,uint8_t epnum)
434 {
435  USB_OTG_EP *ep;
436  uint32_t Status = 0;
437 
438  if ((0x80 & epnum) == 0x80)
439  {
440  ep = &pdev->dev.in_ep[epnum & 0x7F];
441  }
442  else
443  {
444  ep = &pdev->dev.out_ep[epnum];
445  }
446 
447  Status = USB_OTG_GetEPStatus(pdev ,ep);
448 
449  /* Return the current status */
450  return Status;
451 }
452 
460 void DCD_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum , uint32_t Status)
461 {
462  USB_OTG_EP *ep;
463 
464  if ((0x80 & epnum) == 0x80)
465  {
466  ep = &pdev->dev.in_ep[epnum & 0x7F];
467  }
468  else
469  {
470  ep = &pdev->dev.out_ep[epnum];
471  }
472 
473  USB_OTG_SetEPStatus(pdev ,ep , Status);
474 }
475 
488 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
uint32_t DCD_GetEPStatus(USB_OTG_CORE_HANDLE *pdev, uint8_t epnum)
returns the EP Status
Definition: usb_dcd.c:433
uint32_t DCD_EP_Flush(USB_OTG_CORE_HANDLE *pdev, uint8_t epnum)
This Function flushes the FIFOs.
Definition: usb_dcd.c:360
#define USB_OTG_DEFAULT
Definition: usb_dcd.h:56
Specific api&#39;s relative to the used hardware platform.
USB_OTG_STS USB_OTG_SetCurrentMode(USB_OTG_CORE_HANDLE *pdev, uint8_t mode)
USB_OTG_SetCurrentMode : Set ID line.
Definition: usb_core.c:541
__IO uint32_t DCFG
Definition: usb_regs.h:115
uint8_t num
Definition: usb_core.h:138
void DCD_DevConnect(USB_OTG_CORE_HANDLE *pdev)
Connect device (enable internal pull-up)
Definition: usb_dcd.c:395
USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_DisableGlobalInt Enables the controller&#39;s Global Int in the AHB Config reg.
Definition: usb_core.c:464
uint32_t dma_addr
Definition: usb_core.h:148
void DCD_Init(USB_OTG_CORE_HANDLE *pdev, USB_OTG_CORE_ID_TypeDef coreID)
Definition: usb_dcd.c:91
uint32_t DCD_EP_Tx(USB_OTG_CORE_HANDLE *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len)
Transmit data over USB.
Definition: usb_dcd.c:271
#define EP_TYPE_CTRL
Definition: usb_defines.h:140
void DCD_DevDisconnect(USB_OTG_CORE_HANDLE *pdev)
Disconnect device (disable internal pull-up)
Definition: usb_dcd.c:413
USB_OTG_CORE_ID_TypeDef
Definition: usb_defines.h:190
USB_OTG_STS USB_OTG_FlushRxFifo(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_FlushRxFifo : Flush a Rx FIFO.
Definition: usb_core.c:511
uint8_t dev_endpoints
Definition: usb_core.h:165
#define USB_OTG_MAX_EP0_SIZE
Definition: usb_regs.h:71
USB_OTG_CORE_CFGS cfg
Definition: usb_core.h:289
uint32_t DCD_EP_Open(USB_OTG_CORE_HANDLE *pdev, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Configure an EP.
Definition: usb_dcd.c:165
uint32_t DCD_EP_Close(USB_OTG_CORE_HANDLE *pdev, uint8_t ep_addr)
called when an EP is disabled
Definition: usb_dcd.c:204
uint8_t data_pid_start
Definition: usb_core.h:142
#define USB_OTG_WRITE_REG32(reg, value)
Definition: usb_defines.h:226
uint8_t * xfer_buff
Definition: usb_core.h:147
uint32_t xfer_len
Definition: usb_core.h:149
uint8_t type
Definition: usb_core.h:141
USB_OTG_STS USB_OTG_FlushTxFifo(USB_OTG_CORE_HANDLE *pdev, uint32_t num)
USB_OTG_FlushTxFifo : Flush a Tx FIFO.
Definition: usb_core.c:481
__IO uint32_t DCTL
Definition: usb_regs.h:116
#define USB_OTG_READ_REG32(reg)
Definition: usb_defines.h:225
void USB_OTG_BSP_mDelay(const uint32_t msec)
USB_OTG_BSP_mDelay This function provides delay time in milli sec.
void DCD_SetEPStatus(USB_OTG_CORE_HANDLE *pdev, uint8_t epnum, uint32_t Status)
Set the EP Status.
Definition: usb_dcd.c:460
USB_OTG_STS USB_OTG_SelectCore(USB_OTG_CORE_HANDLE *pdev, USB_OTG_CORE_ID_TypeDef coreID)
USB_OTG_SelectCore Initialize core registers address.
Definition: usb_core.c:222
#define USB_OTG_EP_BULK
Definition: usb_dcd.h:51
uint8_t dma_enable
Definition: usb_core.h:167
uint32_t DCD_EP_Stall(USB_OTG_CORE_HANDLE *pdev, uint8_t epnum)
Stall an endpoint.
Definition: usb_dcd.c:306
uint32_t maxpacket
Definition: usb_core.h:145
uint16_t tx_fifo_num
Definition: usb_core.h:144
USB_OTG_STS USB_OTG_EnableGlobalInt(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_EnableGlobalInt Enables the controller&#39;s Global Int in the AHB Config reg.
Definition: usb_core.c:446
#define DEVICE_MODE
Definition: usb_defines.h:110
Peripheral Driver Header file.
uint8_t is_stall
Definition: usb_core.h:140
void DCD_EP_SetAddress(USB_OTG_CORE_HANDLE *pdev, uint8_t address)
This Function set USB device address.
Definition: usb_dcd.c:382
uint8_t is_in
Definition: usb_core.h:139
USB_OTG_CORE_REGS regs
Definition: usb_core.h:290
uint32_t DCD_EP_PrepareRx(USB_OTG_CORE_HANDLE *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
DCD_EP_PrepareRx.
Definition: usb_dcd.c:231
uint32_t xfer_count
Definition: usb_core.h:150
USB_OTG_STS USB_OTG_CoreInit(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_CoreInit Initializes the USB_OTG controller registers and prepares the core device mode or ho...
Definition: usb_core.c:329
#define USB_OTG_MODIFY_REG32(reg, clear_mask, set_mask)
Definition: usb_defines.h:227
struct _USB_OTG_DCTL_TypeDef::@74 b
uint32_t DCD_EP_ClrStall(USB_OTG_CORE_HANDLE *pdev, uint8_t epnum)
Clear stall condition on endpoints.
Definition: usb_dcd.c:333
struct _USB_OTG_DCFG_TypeDef::@73 b
USB_OTG_DREGS * DREGS
Definition: usb_regs.h:225


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:20