usb_core.c
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1 
28 /* Includes ------------------------------------------------------------------*/
29 #include "usb_core.h"
30 #include "usb_bsp.h"
31 
32 
96 {
97  USB_OTG_GINTMSK_TypeDef int_mask;
98 
99  int_mask.d32 = 0;
100  /* Clear any pending USB_OTG Interrupts */
101 #ifndef USE_OTG_MODE
102  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GOTGINT, 0xFFFFFFFF);
103 #endif
104  /* Clear any pending interrupts */
105  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xBFFFFFFF);
106  /* Enable the interrupts in the INTMSK */
107  int_mask.b.wkupintr = 1;
108  int_mask.b.usbsuspend = 1;
109 
110 #ifdef USE_OTG_MODE
111  int_mask.b.otgintr = 1;
112  int_mask.b.sessreqintr = 1;
113  int_mask.b.conidstschng = 1;
114 #endif
115  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32);
116 }
117 
124 {
127  uint32_t count = 0;
128 
129  greset.d32 = 0;
130  /* Wait for AHB master IDLE state. */
131  do
132  {
134  greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL);
135  if (++count > 200000)
136  {
137  return USB_OTG_OK;
138  }
139  }
140  while (greset.b.ahbidle == 0);
141  /* Core Soft Reset */
142  count = 0;
143  greset.b.csftrst = 1;
144  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRSTCTL, greset.d32 );
145  do
146  {
147  greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL);
148  if (++count > 200000)
149  {
150  break;
151  }
152  }
153  while (greset.b.csftrst == 1);
154  /* Wait for 3 PHY Clocks*/
156  return status;
157 }
158 
169  uint8_t *src,
170  uint8_t ch_ep_num,
171  uint16_t len)
172 {
174  if (pdev->cfg.dma_enable == 0)
175  {
176  uint32_t count32b= 0 , i= 0;
177  __IO uint32_t *fifo;
178 
179  count32b = (len + 3) / 4;
180  fifo = pdev->regs.DFIFO[ch_ep_num];
181  for (i = 0; i < count32b; i++)
182  {
183  USB_OTG_WRITE_REG32( fifo, *((__packed uint32_t *)src) );
184  src+=4;
185  }
186  }
187  return status;
188 }
189 
190 
199  uint8_t *dest,
200  uint16_t len)
201 {
202  uint32_t i=0;
203  uint32_t count32b = (len + 3) / 4;
204 
205  __IO uint32_t *fifo = pdev->regs.DFIFO[0];
206 
207  for( i = 0; i < count32b; i++)
208  {
209  *(__packed uint32_t *)dest = USB_OTG_READ_REG32(fifo);
210  dest += 4 ;
211  }
212  return ((void *)dest);
213 }
214 
224 {
225  uint32_t i , baseAddress = 0;
227 
228  pdev->cfg.dma_enable = 0;
229 
230  /* at startup the core is in FS mode */
231  pdev->cfg.speed = USB_OTG_SPEED_FULL;
233 
234  /* initialize device cfg following its address */
235  if (coreID == USB_OTG_FS_CORE_ID)
236  {
237  baseAddress = USB_OTG_FS_BASE_ADDR;
238  pdev->cfg.coreID = USB_OTG_FS_CORE_ID;
239  pdev->cfg.host_channels = 8 ;
240  pdev->cfg.dev_endpoints = 4 ;
241  pdev->cfg.TotalFifoSize = 320; /* in 32-bits */
243 
244 #ifdef USB_OTG_FS_SOF_OUTPUT_ENABLED
245  pdev->cfg.Sof_output = 1;
246 #endif
247 
248 #ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT
249  pdev->cfg.low_power = 1;
250 #endif
251  }
252  else if (coreID == USB_OTG_HS_CORE_ID)
253  {
254  baseAddress = USB_OTG_HS_BASE_ADDR;
255  pdev->cfg.coreID = USB_OTG_HS_CORE_ID;
256  pdev->cfg.host_channels = 12 ;
257  pdev->cfg.dev_endpoints = 6 ;
258  pdev->cfg.TotalFifoSize = 1280;/* in 32-bits */
259 
260 #ifdef USB_OTG_ULPI_PHY_ENABLED
262 #else
263 #ifdef USB_OTG_EMBEDDED_PHY_ENABLED
265 #endif
266 #endif
267 
268 #ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
269  pdev->cfg.dma_enable = 1;
270 #endif
271 
272 #ifdef USB_OTG_HS_SOF_OUTPUT_ENABLED
273  pdev->cfg.Sof_output = 1;
274 #endif
275 
276 #ifdef USB_OTG_HS_LOW_PWR_MGMT_SUPPORT
277  pdev->cfg.low_power = 1;
278 #endif
279 
280  }
281 
282  else
283  {
284  /* Do Nothing */
285  }
286 
287  pdev->regs.GREGS = (USB_OTG_GREGS *)(baseAddress + \
289  pdev->regs.DREGS = (USB_OTG_DREGS *) (baseAddress + \
291 
292  for (i = 0; i < pdev->cfg.dev_endpoints; i++)
293  {
294  pdev->regs.INEP_REGS[i] = (USB_OTG_INEPREGS *) \
295  (baseAddress + USB_OTG_DEV_IN_EP_REG_OFFSET + \
296  (i * USB_OTG_EP_REG_OFFSET));
297  pdev->regs.OUTEP_REGS[i] = (USB_OTG_OUTEPREGS *) \
298  (baseAddress + USB_OTG_DEV_OUT_EP_REG_OFFSET + \
299  (i * USB_OTG_EP_REG_OFFSET));
300  }
301  pdev->regs.HREGS = (USB_OTG_HREGS *)(baseAddress + \
303  pdev->regs.HPRT0 = (uint32_t *)(baseAddress + USB_OTG_HOST_PORT_REGS_OFFSET);
304 
305  for (i = 0; i < pdev->cfg.host_channels; i++)
306  {
307  pdev->regs.HC_REGS[i] = (USB_OTG_HC_REGS *)(baseAddress + \
310  }
311  for (i = 0; i < pdev->cfg.host_channels; i++)
312  {
313  pdev->regs.DFIFO[i] = (uint32_t *)(baseAddress + USB_OTG_DATA_FIFO_OFFSET +\
314  (i * USB_OTG_DATA_FIFO_SIZE));
315  }
316  pdev->regs.PCGCCTL = (uint32_t *)(baseAddress + USB_OTG_PCGCCTL_OFFSET);
317 
318  return status;
319 }
320 
321 
330 {
333  USB_OTG_GCCFG_TypeDef gccfg;
335 #if defined (STM32F446xx) || defined (STM32F469_479xx)
337 #endif
338  usbcfg.d32 = 0;
339  gccfg.d32 = 0;
340  ahbcfg.d32 = 0;
341 
342  if (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY)
343  {
344  gccfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GCCFG);
345  gccfg.b.pwdn = 0;
346 
347  if (pdev->cfg.Sof_output)
348  {
349  gccfg.b.sofouten = 1;
350  }
351  USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32);
352 
353  /* Init The ULPI Interface */
354  usbcfg.d32 = 0;
355  usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
356 
357  usbcfg.b.physel = 0; /* HS Interface */
358 #ifdef USB_OTG_INTERNAL_VBUS_ENABLED
359  usbcfg.b.ulpi_ext_vbus_drv = 0; /* Use internal VBUS */
360 #else
361 #ifdef USB_OTG_EXTERNAL_VBUS_ENABLED
362  usbcfg.b.ulpi_ext_vbus_drv = 1; /* Use external VBUS */
363 #endif
364 #endif
365  usbcfg.b.term_sel_dl_pulse = 0; /* Data line pulsing using utmi_txvalid */
366 
367  usbcfg.b.ulpi_fsls = 0;
368  usbcfg.b.ulpi_clk_sus_m = 0;
369  USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
370 
371  /* Reset after a PHY select */
372  USB_OTG_CoreReset(pdev);
373 
374  if(pdev->cfg.dma_enable == 1)
375  {
376 
377  ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/
378  ahbcfg.b.dmaenable = 1;
379  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32);
380 
381  }
382  }
383  else /* FS interface (embedded Phy) */
384  {
385 
386  usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);;
387  usbcfg.b.physel = 1; /* FS Interface */
388  USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
389  /* Reset after a PHY select and set Host mode */
390  USB_OTG_CoreReset(pdev);
391  /* Deactivate the power down*/
392  gccfg.d32 = 0;
393  gccfg.b.pwdn = 1;
394 
395  // XXX Betaflight mod; disabled VBUS sensing features completely, including Sense A and B.
396  gccfg.b.disablevbussensing = 1;
397 
398  if(pdev->cfg.Sof_output)
399  {
400  gccfg.b.sofouten = 1;
401  }
402 
403  USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32);
404  USB_OTG_BSP_mDelay(20);
405  }
406  /* case the HS core is working in FS mode */
407  if(pdev->cfg.dma_enable == 1)
408  {
409 
410  ahbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GAHBCFG);
411  ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/
412  ahbcfg.b.dmaenable = 1;
413  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32);
414 
415  }
416  /* initialize OTG features */
417 #ifdef USE_OTG_MODE
418  usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
419  usbcfg.b.hnpcap = 1;
420  usbcfg.b.srpcap = 1;
421  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
423 #endif
424 
425 #if defined (STM32F446xx) || defined (STM32F469_479xx)
426  usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
427  usbcfg.b.srpcap = 1;
428  /*clear sdis bit in dctl */
429  dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL);
430  /* Connect device */
431  dctl.b.sftdiscon = 0;
432  USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32);
433  dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL);
434  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
436 #endif
437 
438  return status;
439 }
447 {
450 
451  ahbcfg.d32 = 0;
452  ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
453  USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, 0, ahbcfg.d32);
454  return status;
455 }
456 
457 
465 {
468  ahbcfg.d32 = 0;
469  ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
470  USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32, 0);
471  return status;
472 }
473 
474 
482 {
485 
486  uint32_t count = 0;
487  greset.d32 = 0;
488  greset.b.txfflsh = 1;
489  greset.b.txfnum = num;
490  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 );
491  do
492  {
493  greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL);
494  if (++count > 200000)
495  {
496  break;
497  }
498  }
499  while (greset.b.txfflsh == 1);
500  /* Wait for 3 PHY Clocks*/
502  return status;
503 }
504 
505 
512 {
515  uint32_t count = 0;
516 
517  greset.d32 = 0;
518  greset.b.rxfflsh = 1;
519  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 );
520  do
521  {
522  greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL);
523  if (++count > 200000)
524  {
525  break;
526  }
527  }
528  while (greset.b.rxfflsh == 1);
529  /* Wait for 3 PHY Clocks*/
531  return status;
532 }
533 
534 
542 {
545 
546  usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
547 
548  usbcfg.b.force_host = 0;
549  usbcfg.b.force_dev = 0;
550 
551  if ( mode == HOST_MODE)
552  {
553  usbcfg.b.force_host = 1;
554  }
555  else if ( mode == DEVICE_MODE)
556  {
557  usbcfg.b.force_dev = 1;
558  }
559 
560  else
561  {
562  /* Do Nothing */
563  }
564 
565  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
566  USB_OTG_BSP_mDelay(50);
567  return status;
568 }
569 
570 
577 {
578  return (USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS ) & 0x1);
579 }
580 
581 
588 {
589  return (USB_OTG_GetMode(pdev) != HOST_MODE);
590 }
591 
592 
599 {
600  return (USB_OTG_GetMode(pdev) == HOST_MODE);
601 }
602 
603 
610 {
611  uint32_t v = 0;
612  v = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS);
613  v &= USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTMSK);
614  return v;
615 }
616 
617 
624 {
625  return (USB_OTG_READ_REG32 (&pdev->regs.GREGS->GOTGINT));
626 }
627 
628 #ifdef USE_HOST_MODE
629 
634 USB_OTG_STS USB_OTG_CoreInitHost(USB_OTG_CORE_HANDLE *pdev)
635 {
637  USB_OTG_FSIZ_TypeDef nptxfifosize;
638  USB_OTG_FSIZ_TypeDef ptxfifosize;
640 
641 #ifdef USE_OTG_MODE
642  USB_OTG_OTGCTL_TypeDef gotgctl;
643 #endif
644 
645  uint32_t i = 0;
646 
647  nptxfifosize.d32 = 0;
648  ptxfifosize.d32 = 0;
649 #ifdef USE_OTG_MODE
650  gotgctl.d32 = 0;
651 #endif
652  hcfg.d32 = 0;
653 
654 
655  /* configure charge pump IO */
657 
658  /* Restart the Phy Clock */
659  USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0);
660 
661  /* Initialize Host Configuration Register */
662  if (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY)
663  {
664  USB_OTG_InitFSLSPClkSel(pdev , HCFG_30_60_MHZ);
665  }
666  else
667  {
668  USB_OTG_InitFSLSPClkSel(pdev , HCFG_48_MHZ);
669  }
670  USB_OTG_ResetPort(pdev);
671 
672  hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG);
673  hcfg.b.fslssupp = 0;
674  USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32);
675 
676  /* Configure data FIFO sizes */
677  /* Rx FIFO */
678 #ifdef USB_OTG_FS_CORE
679  if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID)
680  {
681  /* set Rx FIFO size */
683  nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE;
684  nptxfifosize.b.depth = TXH_NP_FS_FIFOSIZ;
685  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32);
686 
687  ptxfifosize.b.startaddr = RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ;
688  ptxfifosize.b.depth = TXH_P_FS_FIFOSIZ;
689  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32);
690  }
691 #endif
692 #ifdef USB_OTG_HS_CORE
693  if (pdev->cfg.coreID == USB_OTG_HS_CORE_ID)
694  {
695  /* set Rx FIFO size */
696  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE);
697  nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE;
698  nptxfifosize.b.depth = TXH_NP_HS_FIFOSIZ;
699  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32);
700 
701  ptxfifosize.b.startaddr = RX_FIFO_HS_SIZE + TXH_NP_HS_FIFOSIZ;
702  ptxfifosize.b.depth = TXH_P_HS_FIFOSIZ;
703  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32);
704  }
705 #endif
706 
707 #ifdef USE_OTG_MODE
708  /* Clear Host Set HNP Enable in the USB_OTG Control Register */
709  gotgctl.b.hstsethnpen = 1;
710  USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GOTGCTL, gotgctl.d32, 0);
711 #endif
712 
713  /* Make sure the FIFOs are flushed. */
714  USB_OTG_FlushTxFifo(pdev, 0x10 ); /* all Tx FIFOs */
715  USB_OTG_FlushRxFifo(pdev);
716 
717 
718  /* Clear all pending HC Interrupts */
719  for (i = 0; i < pdev->cfg.host_channels; i++)
720  {
721  USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINT, 0xFFFFFFFF );
722  USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINTMSK, 0 );
723  }
724 #ifndef USE_OTG_MODE
725  USB_OTG_DriveVbus(pdev, 1);
726 #endif
727 
728  USB_OTG_EnableHostInt(pdev);
729  return status;
730 }
731 
738 uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev)
739 {
740  return !(USB_OTG_READ_REG32(&pdev->regs.HREGS->HFNUM) & 0x1);
741 }
742 
749 void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state)
750 {
751  USB_OTG_HPRT0_TypeDef hprt0;
752 
753  hprt0.d32 = 0;
754 
755  /* enable disable the external charge pump */
756  USB_OTG_BSP_DriveVBUS(pdev, state);
757 
758  /* Turn on the Host port power. */
759  hprt0.d32 = USB_OTG_ReadHPRT0(pdev);
760  if ((hprt0.b.prtpwr == 0 ) && (state == 1 ))
761  {
762  hprt0.b.prtpwr = 1;
763  USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32);
764  }
765  if ((hprt0.b.prtpwr == 1 ) && (state == 0 ))
766  {
767  hprt0.b.prtpwr = 0;
768  USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32);
769  }
770 
771  USB_OTG_BSP_mDelay(200);
772 }
778 USB_OTG_STS USB_OTG_EnableHostInt(USB_OTG_CORE_HANDLE *pdev)
779 {
782  intmsk.d32 = 0;
783  /* Disable all interrupts. */
785 
786  /* Clear any pending interrupts. */
787  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF);
788 
789  /* Enable the common interrupts */
791 
792  if (pdev->cfg.dma_enable == 0)
793  {
794  intmsk.b.rxstsqlvl = 1;
795  }
796 
797 
798  intmsk.b.incomplisoout = 1;
799  intmsk.b.hcintr = 1;
800 intmsk.b.portintr = 1;
801  USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32);
802 
803  intmsk.d32 = 0;
804 
805  intmsk.b.disconnect = 1;
806 
807  intmsk.b.sofintr = 1;
808  USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, intmsk.d32, 0);
809  return status;
810 }
811 
819 void USB_OTG_InitFSLSPClkSel(USB_OTG_CORE_HANDLE *pdev , uint8_t freq)
820 {
822 
823  hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG);
824  hcfg.b.fslspclksel = freq;
825  USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32);
826 }
827 
828 
834 uint32_t USB_OTG_ReadHPRT0(USB_OTG_CORE_HANDLE *pdev)
835 {
836  USB_OTG_HPRT0_TypeDef hprt0;
837 
838  hprt0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0);
839  hprt0.b.prtena = 0;
840  hprt0.b.prtconndet = 0;
841  hprt0.b.prtenchng = 0;
842  hprt0.b.prtovrcurrchng = 0;
843  return hprt0.d32;
844 }
845 
846 
852 uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev)
853 {
854  return (USB_OTG_READ_REG32 (&pdev->regs.HREGS->HAINT));
855 }
856 
857 
865 uint32_t USB_OTG_ResetPort(USB_OTG_CORE_HANDLE *pdev)
866 {
867  USB_OTG_HPRT0_TypeDef hprt0;
868 
869  hprt0.d32 = USB_OTG_ReadHPRT0(pdev);
870  hprt0.b.prtrst = 1;
871  USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32);
872  USB_OTG_BSP_mDelay (100); /* See Note #1 */
873  hprt0.b.prtrst = 0;
874  USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32);
875  USB_OTG_BSP_mDelay (20);
876  return 1;
877 }
878 
879 
886 USB_OTG_STS USB_OTG_HC_Init(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
887 {
889  uint32_t intr_enable = 0;
890  USB_OTG_HCINTMSK_TypeDef hcintmsk;
891  USB_OTG_GINTMSK_TypeDef gintmsk;
892  USB_OTG_HCCHAR_TypeDef hcchar;
894 
895 
896  gintmsk.d32 = 0;
897  hcintmsk.d32 = 0;
898  hcchar.d32 = 0;
899 
900  /* Clear old interrupt conditions for this host channel. */
901  hcint.d32 = 0xFFFFFFFF;
902  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINT, hcint.d32);
903 
904  /* Enable channel interrupts required for this transfer. */
905  hcintmsk.d32 = 0;
906 
907  if (pdev->cfg.dma_enable == 1)
908  {
909  hcintmsk.b.ahberr = 1;
910  }
911 
912  switch (pdev->host.hc[hc_num].ep_type)
913  {
914  case EP_TYPE_CTRL:
915  case EP_TYPE_BULK:
916  hcintmsk.b.xfercompl = 1;
917  hcintmsk.b.stall = 1;
918  hcintmsk.b.xacterr = 1;
919  hcintmsk.b.datatglerr = 1;
920  hcintmsk.b.nak = 1;
921  if (pdev->host.hc[hc_num].ep_is_in)
922  {
923  hcintmsk.b.bblerr = 1;
924  }
925  else
926  {
927  hcintmsk.b.nyet = 1;
928  if (pdev->host.hc[hc_num].do_ping)
929  {
930  hcintmsk.b.ack = 1;
931  }
932  }
933  break;
934  case EP_TYPE_INTR:
935  hcintmsk.b.xfercompl = 1;
936  hcintmsk.b.nak = 1;
937  hcintmsk.b.stall = 1;
938  hcintmsk.b.xacterr = 1;
939  hcintmsk.b.datatglerr = 1;
940  hcintmsk.b.frmovrun = 1;
941 
942  if (pdev->host.hc[hc_num].ep_is_in)
943  {
944  hcintmsk.b.bblerr = 1;
945  }
946 
947  break;
948  case EP_TYPE_ISOC:
949  hcintmsk.b.xfercompl = 1;
950  hcintmsk.b.frmovrun = 1;
951  hcintmsk.b.ack = 1;
952 
953  if (pdev->host.hc[hc_num].ep_is_in)
954  {
955  hcintmsk.b.xacterr = 1;
956  hcintmsk.b.bblerr = 1;
957  }
958  break;
959  }
960 
961 
962  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, hcintmsk.d32);
963 
964 
965  /* Enable the top level host channel interrupt. */
966  intr_enable = (1 << hc_num);
967  USB_OTG_MODIFY_REG32(&pdev->regs.HREGS->HAINTMSK, 0, intr_enable);
968 
969  /* Make sure host channel interrupts are enabled. */
970  gintmsk.b.hcintr = 1;
971  USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, 0, gintmsk.d32);
972 
973  /* Program the HCCHAR register */
974  hcchar.d32 = 0;
975  hcchar.b.devaddr = pdev->host.hc[hc_num].dev_addr;
976  hcchar.b.epnum = pdev->host.hc[hc_num].ep_num;
977  hcchar.b.epdir = pdev->host.hc[hc_num].ep_is_in;
978  hcchar.b.lspddev = (pdev->host.hc[hc_num].speed == HPRT0_PRTSPD_LOW_SPEED);
979  hcchar.b.eptype = pdev->host.hc[hc_num].ep_type;
980  hcchar.b.mps = pdev->host.hc[hc_num].max_packet;
981  if (pdev->host.hc[hc_num].ep_type == HCCHAR_INTR)
982  {
983  hcchar.b.oddfrm = 1;
984  }
985  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32);
986  return status;
987 }
988 
989 
996 USB_OTG_STS USB_OTG_HC_StartXfer(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
997 {
999  USB_OTG_HCCHAR_TypeDef hcchar;
1000  USB_OTG_HCTSIZn_TypeDef hctsiz;
1001  USB_OTG_HNPTXSTS_TypeDef hnptxsts;
1002  USB_OTG_HPTXSTS_TypeDef hptxsts;
1003  USB_OTG_GINTMSK_TypeDef intmsk;
1004  uint16_t len_words = 0;
1005 
1006  uint16_t num_packets;
1007  uint16_t max_hc_pkt_count;
1008 
1009  max_hc_pkt_count = 256;
1010  hctsiz.d32 = 0;
1011  hcchar.d32 = 0;
1012  intmsk.d32 = 0;
1013 
1014  /* Compute the expected number of packets associated to the transfer */
1015  if (pdev->host.hc[hc_num].xfer_len > 0)
1016  {
1017  num_packets = (pdev->host.hc[hc_num].xfer_len + \
1018  pdev->host.hc[hc_num].max_packet - 1) / pdev->host.hc[hc_num].max_packet;
1019 
1020  if (num_packets > max_hc_pkt_count)
1021  {
1022  num_packets = max_hc_pkt_count;
1023  pdev->host.hc[hc_num].xfer_len = num_packets * \
1024  pdev->host.hc[hc_num].max_packet;
1025  }
1026  }
1027  else
1028  {
1029  num_packets = 1;
1030  }
1031  if (pdev->host.hc[hc_num].ep_is_in)
1032  {
1033  pdev->host.hc[hc_num].xfer_len = num_packets * \
1034  pdev->host.hc[hc_num].max_packet;
1035  }
1036  /* Initialize the HCTSIZn register */
1037  hctsiz.b.xfersize = pdev->host.hc[hc_num].xfer_len;
1038  hctsiz.b.pktcnt = num_packets;
1039  hctsiz.b.pid = pdev->host.hc[hc_num].data_pid;
1040  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32);
1041 
1042  if (pdev->cfg.dma_enable == 1)
1043  {
1044  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCDMA, (unsigned int)pdev->host.hc[hc_num].xfer_buff);
1045  }
1046 
1047 
1048  hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR);
1049  hcchar.b.oddfrm = USB_OTG_IsEvenFrame(pdev);
1050 
1051  /* Set host channel enable */
1052  hcchar.b.chen = 1;
1053  hcchar.b.chdis = 0;
1054  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32);
1055 
1056  if (pdev->cfg.dma_enable == 0) /* Slave mode */
1057  {
1058  if((pdev->host.hc[hc_num].ep_is_in == 0) &&
1059  (pdev->host.hc[hc_num].xfer_len > 0))
1060  {
1061  switch(pdev->host.hc[hc_num].ep_type)
1062  {
1063  /* Non periodic transfer */
1064  case EP_TYPE_CTRL:
1065  case EP_TYPE_BULK:
1066 
1067  hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS);
1068  len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4;
1069 
1070  /* check if there is enough space in FIFO space */
1071  if(len_words > hnptxsts.b.nptxfspcavail)
1072  {
1073  /* need to process data in nptxfempty interrupt */
1074  intmsk.b.nptxfempty = 1;
1075  USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32);
1076  }
1077 
1078  break;
1079  /* Periodic transfer */
1080  case EP_TYPE_INTR:
1081  case EP_TYPE_ISOC:
1082  hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS);
1083  len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4;
1084  /* check if there is enough space in FIFO space */
1085  if(len_words > hptxsts.b.ptxfspcavail) /* split the transfer */
1086  {
1087  /* need to process data in ptxfempty interrupt */
1088  intmsk.b.ptxfempty = 1;
1089  USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32);
1090  }
1091  break;
1092 
1093  default:
1094  break;
1095  }
1096 
1097  /* Write packet into the Tx FIFO. */
1098  USB_OTG_WritePacket(pdev,
1099  pdev->host.hc[hc_num].xfer_buff ,
1100  hc_num, pdev->host.hc[hc_num].xfer_len);
1101  }
1102  }
1103  return status;
1104 }
1105 
1106 
1113 USB_OTG_STS USB_OTG_HC_Halt(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
1114 {
1116  USB_OTG_HNPTXSTS_TypeDef nptxsts;
1117  USB_OTG_HPTXSTS_TypeDef hptxsts;
1118  USB_OTG_HCCHAR_TypeDef hcchar;
1119 
1120  nptxsts.d32 = 0;
1121  hptxsts.d32 = 0;
1122  hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR);
1123 
1124  hcchar.b.chdis = 1;
1125 
1126  /* Check for space in the request queue to issue the halt. */
1127  if (hcchar.b.eptype == HCCHAR_CTRL || hcchar.b.eptype == HCCHAR_BULK)
1128  {
1129  nptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS);
1130  if (nptxsts.b.nptxqspcavail == 0)
1131  {
1132  hcchar.b.chen = 0;
1133  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32);
1134  }
1135  }
1136  else
1137  {
1138  hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS);
1139  if (hptxsts.b.ptxqspcavail == 0)
1140  {
1141  hcchar.b.chen = 0;
1142  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32);
1143  }
1144  }
1145  hcchar.b.chen = 1;
1146  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32);
1147  return status;
1148 }
1149 
1155 USB_OTG_STS USB_OTG_HC_DoPing(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
1156 {
1158  USB_OTG_HCCHAR_TypeDef hcchar;
1159  USB_OTG_HCTSIZn_TypeDef hctsiz;
1160 
1161  hctsiz.d32 = 0;
1162  hctsiz.b.dopng = 1;
1163  hctsiz.b.pktcnt = 1;
1164  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32);
1165 
1166  hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR);
1167  hcchar.b.chen = 1;
1168  hcchar.b.chdis = 0;
1169  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32);
1170  return status;
1171 }
1172 
1178 void USB_OTG_StopHost(USB_OTG_CORE_HANDLE *pdev)
1179 {
1180  USB_OTG_HCCHAR_TypeDef hcchar;
1181  uint32_t i;
1182 
1183  USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINTMSK , 0);
1184  USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINT, 0xFFFFFFFF);
1185  /* Flush out any leftover queued requests. */
1186 
1187  for (i = 0; i < pdev->cfg.host_channels; i++)
1188  {
1189  hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[i]->HCCHAR);
1190  hcchar.b.chen = 0;
1191  hcchar.b.chdis = 1;
1192  hcchar.b.epdir = 0;
1193  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[i]->HCCHAR, hcchar.d32);
1194  }
1195 
1196  /* Flush the FIFO */
1197  USB_OTG_FlushRxFifo(pdev);
1198  USB_OTG_FlushTxFifo(pdev , 0x10 );
1199 }
1200 #endif
1201 #ifdef USE_DEVICE_MODE
1202 /* PCD Core Layer */
1203 
1210 void USB_OTG_InitDevSpeed(USB_OTG_CORE_HANDLE *pdev , uint8_t speed)
1211 {
1212  USB_OTG_DCFG_TypeDef dcfg;
1213 
1214  dcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCFG);
1215  dcfg.b.devspd = speed;
1216  USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCFG, dcfg.d32);
1217 }
1218 
1219 
1226 USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev)
1227 {
1229  USB_OTG_DEPCTL_TypeDef depctl;
1230  uint32_t i;
1231  USB_OTG_DCFG_TypeDef dcfg;
1232  USB_OTG_FSIZ_TypeDef nptxfifosize;
1233  USB_OTG_FSIZ_TypeDef txfifosize;
1235  USB_OTG_DTHRCTL_TypeDef dthrctl;
1236 
1237  depctl.d32 = 0;
1238  dcfg.d32 = 0;
1239  nptxfifosize.d32 = 0;
1240  txfifosize.d32 = 0;
1241  msk.d32 = 0;
1242 
1243  /* Restart the Phy Clock */
1244  USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0);
1245  /* Device configuration register */
1246  dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG);
1248  USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32 );
1249 
1250 #ifdef USB_OTG_FS_CORE
1251  if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID )
1252  {
1253 
1254  /* Set Full speed phy */
1255  USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_FULL);
1256 
1257  /* set Rx FIFO size */
1259 
1260  /* EP0 TX*/
1261  nptxfifosize.b.depth = TX0_FIFO_FS_SIZE;
1262  nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE;
1263  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 );
1264 
1265 
1266  /* EP1 TX*/
1267  txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
1268  txfifosize.b.depth = TX1_FIFO_FS_SIZE;
1269  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 );
1270 
1271 
1272  /* EP2 TX*/
1273  txfifosize.b.startaddr += txfifosize.b.depth;
1274  txfifosize.b.depth = TX2_FIFO_FS_SIZE;
1275  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 );
1276 
1277 
1278  /* EP3 TX*/
1279  txfifosize.b.startaddr += txfifosize.b.depth;
1280  txfifosize.b.depth = TX3_FIFO_FS_SIZE;
1281  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 );
1282  }
1283 #endif
1284 #ifdef USB_OTG_HS_CORE
1285  if(pdev->cfg.coreID == USB_OTG_HS_CORE_ID )
1286  {
1287 
1288  /* Set High speed phy */
1289 
1290  if(pdev->cfg.phy_itface == USB_OTG_ULPI_PHY)
1291  {
1292  USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH);
1293  }
1294  else /* set High speed phy in Full speed mode */
1295  {
1296  USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH_IN_FULL);
1297  }
1298 
1299  /* set Rx FIFO size */
1300  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE);
1301 
1302  /* EP0 TX*/
1303  nptxfifosize.b.depth = TX0_FIFO_HS_SIZE;
1304  nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE;
1305  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 );
1306 
1307 
1308  /* EP1 TX*/
1309  txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
1310  txfifosize.b.depth = TX1_FIFO_HS_SIZE;
1311  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 );
1312 
1313 
1314  /* EP2 TX*/
1315  txfifosize.b.startaddr += txfifosize.b.depth;
1316  txfifosize.b.depth = TX2_FIFO_HS_SIZE;
1317  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 );
1318 
1319 
1320  /* EP3 TX*/
1321  txfifosize.b.startaddr += txfifosize.b.depth;
1322  txfifosize.b.depth = TX3_FIFO_HS_SIZE;
1323  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 );
1324 
1325  /* EP4 TX*/
1326  txfifosize.b.startaddr += txfifosize.b.depth;
1327  txfifosize.b.depth = TX4_FIFO_HS_SIZE;
1328  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[3], txfifosize.d32 );
1329 
1330 
1331  /* EP5 TX*/
1332  txfifosize.b.startaddr += txfifosize.b.depth;
1333  txfifosize.b.depth = TX5_FIFO_HS_SIZE;
1334  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[4], txfifosize.d32 );
1335  }
1336 #endif
1337  /* Flush the FIFOs */
1338  USB_OTG_FlushTxFifo(pdev , 0x10); /* all Tx FIFOs */
1339  USB_OTG_FlushRxFifo(pdev);
1340  /* Clear all pending Device Interrupts */
1341  USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 );
1342  USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 );
1343  USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF );
1344  USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 );
1345 
1346  for (i = 0; i < pdev->cfg.dev_endpoints; i++)
1347  {
1348  depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[i]->DIEPCTL);
1349  if (depctl.b.epena)
1350  {
1351  depctl.d32 = 0;
1352  depctl.b.epdis = 1;
1353  depctl.b.snak = 1;
1354  }
1355  else
1356  {
1357  depctl.d32 = 0;
1358  }
1359  USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPCTL, depctl.d32);
1360  USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPTSIZ, 0);
1361  USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF);
1362  }
1363  for (i = 0; i < pdev->cfg.dev_endpoints; i++)
1364  {
1365  USB_OTG_DEPCTL_TypeDef depctl;
1366  depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[i]->DOEPCTL);
1367  if (depctl.b.epena)
1368  {
1369  depctl.d32 = 0;
1370  depctl.b.epdis = 1;
1371  depctl.b.snak = 1;
1372  }
1373  else
1374  {
1375  depctl.d32 = 0;
1376  }
1377  USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPCTL, depctl.d32);
1378  USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPTSIZ, 0);
1379  USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF);
1380  }
1381  msk.d32 = 0;
1382  msk.b.txfifoundrn = 1;
1383  USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPMSK, msk.d32, msk.d32);
1384 
1385  if (pdev->cfg.dma_enable == 1)
1386  {
1387  dthrctl.d32 = 0;
1388  dthrctl.b.non_iso_thr_en = 1;
1389  dthrctl.b.iso_thr_en = 1;
1390  dthrctl.b.tx_thr_len = 64;
1391  dthrctl.b.rx_thr_en = 1;
1392  dthrctl.b.rx_thr_len = 64;
1393  USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DTHRCTL, dthrctl.d32);
1394  }
1395  USB_OTG_EnableDevInt(pdev);
1396  return status;
1397 }
1398 
1399 
1405 USB_OTG_STS USB_OTG_EnableDevInt(USB_OTG_CORE_HANDLE *pdev)
1406 {
1408  USB_OTG_GINTMSK_TypeDef intmsk;
1409 
1410  intmsk.d32 = 0;
1411 
1412  /* Disable all interrupts. */
1413  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, 0);
1414  /* Clear any pending interrupts */
1415  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xBFFFFFFF);
1416  /* Enable the common interrupts */
1418 
1419  if (pdev->cfg.dma_enable == 0)
1420  {
1421  intmsk.b.rxstsqlvl = 1;
1422  }
1423 
1424  /* Enable interrupts matching to the Device mode ONLY */
1425  intmsk.b.usbsuspend = 1;
1426  intmsk.b.usbreset = 1;
1427  intmsk.b.enumdone = 1;
1428  intmsk.b.inepintr = 1;
1429  intmsk.b.outepintr = 1;
1430  intmsk.b.sofintr = 1;
1431 
1432  intmsk.b.incomplisoin = 1;
1433  intmsk.b.incomplisoout = 1;
1434 #ifdef VBUS_SENSING_ENABLED
1435  intmsk.b.sessreqintr = 1;
1436  intmsk.b.otgintr = 1;
1437 #endif
1438  USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32);
1439  return status;
1440 }
1441 
1442 
1449 enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev)
1450 {
1451  USB_OTG_DSTS_TypeDef dsts;
1452  enum USB_OTG_SPEED speed = USB_SPEED_UNKNOWN;
1453 
1454 
1455  dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
1456 
1457  switch (dsts.b.enumspd)
1458  {
1460  speed = USB_SPEED_HIGH;
1461  break;
1464  speed = USB_SPEED_FULL;
1465  break;
1466 
1468  speed = USB_SPEED_LOW;
1469  break;
1470  default:
1471  speed = USB_SPEED_FULL;
1472  break;
1473  }
1474 
1475  return speed;
1476 }
1477 
1484 USB_OTG_STS USB_OTG_EP0Activate(USB_OTG_CORE_HANDLE *pdev)
1485 {
1487  USB_OTG_DSTS_TypeDef dsts;
1488  USB_OTG_DEPCTL_TypeDef diepctl;
1489  USB_OTG_DCTL_TypeDef dctl;
1490 
1491  dctl.d32 = 0;
1492  /* Read the Device Status and Endpoint 0 Control registers */
1493  dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
1494  diepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL);
1495  /* Set the MPS of the IN EP based on the enumeration speed */
1496  switch (dsts.b.enumspd)
1497  {
1501  diepctl.b.mps = DEP0CTL_MPS_64;
1502  break;
1504  diepctl.b.mps = DEP0CTL_MPS_8;
1505  break;
1506  default:
1507  diepctl.b.mps = DEP0CTL_MPS_64;
1508  break;
1509  }
1510  USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL, diepctl.d32);
1511  dctl.b.cgnpinnak = 1;
1512  USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, dctl.d32);
1513  return status;
1514 }
1515 
1516 
1522 USB_OTG_STS USB_OTG_EPActivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
1523 {
1525  USB_OTG_DEPCTL_TypeDef depctl;
1526  USB_OTG_DAINT_TypeDef daintmsk;
1527  __IO uint32_t *addr;
1528 
1529 
1530  depctl.d32 = 0;
1531  daintmsk.d32 = 0;
1532  /* Read DEPCTLn register */
1533  if (ep->is_in == 1)
1534  {
1535  addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL;
1536  daintmsk.ep.in = 1 << ep->num;
1537  }
1538  else
1539  {
1540  addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL;
1541  daintmsk.ep.out = 1 << ep->num;
1542  }
1543  /* If the EP is already active don't change the EP Control
1544  * register. */
1545  depctl.d32 = USB_OTG_READ_REG32(addr);
1546  if (!depctl.b.usbactep)
1547  {
1548  depctl.b.mps = ep->maxpacket;
1549  depctl.b.eptype = ep->type;
1550  depctl.b.txfnum = ep->tx_fifo_num;
1551  depctl.b.setd0pid = 1;
1552  depctl.b.usbactep = 1;
1553  USB_OTG_WRITE_REG32(addr, depctl.d32);
1554  }
1555  /* Enable the Interrupt for this EP */
1556 #ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
1557  if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID))
1558  {
1559  USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, 0, daintmsk.d32);
1560  }
1561  else
1562 #endif
1563  USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, 0, daintmsk.d32);
1564  return status;
1565 }
1566 
1567 
1573 USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
1574 {
1576  USB_OTG_DEPCTL_TypeDef depctl;
1577  USB_OTG_DAINT_TypeDef daintmsk;
1578  __IO uint32_t *addr;
1579 
1580  depctl.d32 = 0;
1581  daintmsk.d32 = 0;
1582  /* Read DEPCTLn register */
1583  if (ep->is_in == 1)
1584  {
1585  addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL;
1586  daintmsk.ep.in = 1 << ep->num;
1587  }
1588  else
1589  {
1590  addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL;
1591  daintmsk.ep.out = 1 << ep->num;
1592  }
1593  depctl.b.usbactep = 0;
1594  USB_OTG_WRITE_REG32(addr, depctl.d32);
1595  /* Disable the Interrupt for this EP */
1596 
1597 #ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
1598  if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID))
1599  {
1600  USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, daintmsk.d32, 0);
1601  }
1602  else
1603 #endif
1604  USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, daintmsk.d32, 0);
1605  return status;
1606 }
1607 
1608 
1615 USB_OTG_STS USB_OTG_EPStartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
1616 {
1618  USB_OTG_DEPCTL_TypeDef depctl;
1619  USB_OTG_DEPXFRSIZ_TypeDef deptsiz;
1620  USB_OTG_DSTS_TypeDef dsts;
1621  uint32_t fifoemptymsk = 0;
1622 
1623  depctl.d32 = 0;
1624  deptsiz.d32 = 0;
1625  /* IN endpoint */
1626  if (ep->is_in == 1)
1627  {
1628  depctl.d32 = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPCTL));
1629  deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ));
1630  /* Zero Length Packet? */
1631  if (ep->xfer_len == 0)
1632  {
1633  deptsiz.b.xfersize = 0;
1634  deptsiz.b.pktcnt = 1;
1635  }
1636  else
1637  {
1638  /* Program the transfer size and packet count
1639  * as follows: xfersize = N * maxpacket +
1640  * short_packet pktcnt = N + (short_packet
1641  * exist ? 1 : 0)
1642  */
1643  deptsiz.b.xfersize = ep->xfer_len;
1644  deptsiz.b.pktcnt = (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
1645 
1646  if (ep->type == EP_TYPE_ISOC)
1647  {
1648  deptsiz.b.mc = 1;
1649  }
1650  }
1651  USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ, deptsiz.d32);
1652 
1653  if (pdev->cfg.dma_enable == 1)
1654  {
1656  }
1657  else
1658  {
1659  if (ep->type != EP_TYPE_ISOC)
1660  {
1661  /* Enable the Tx FIFO Empty Interrupt for this EP */
1662  if (ep->xfer_len > 0)
1663  {
1664  fifoemptymsk = 1 << ep->num;
1665  USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk);
1666  }
1667  }
1668  }
1669 
1670 
1671  if (ep->type == EP_TYPE_ISOC)
1672  {
1673  dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
1674 
1675  if (((dsts.b.soffn)&0x1) == 0)
1676  {
1677  depctl.b.setd1pid = 1;
1678  }
1679  else
1680  {
1681  depctl.b.setd0pid = 1;
1682  }
1683  }
1684 
1685  /* EP enable, IN data in FIFO */
1686  depctl.b.cnak = 1;
1687  depctl.b.epena = 1;
1688  USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPCTL, depctl.d32);
1689 
1690  if (ep->type == EP_TYPE_ISOC)
1691  {
1692  USB_OTG_WritePacket(pdev, ep->xfer_buff, ep->num, ep->xfer_len);
1693  }
1694  }
1695  else
1696  {
1697  /* OUT endpoint */
1698  depctl.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL));
1699  deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ));
1700  /* Program the transfer size and packet count as follows:
1701  * pktcnt = N
1702  * xfersize = N * maxpacket
1703  */
1704  if (ep->xfer_len == 0)
1705  {
1706  deptsiz.b.xfersize = ep->maxpacket;
1707  deptsiz.b.pktcnt = 1;
1708  }
1709  else
1710  {
1711  deptsiz.b.pktcnt = (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
1712  deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
1713  ep->xfer_len = deptsiz.b.xfersize ;
1714  }
1715  USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32);
1716 
1717  if (pdev->cfg.dma_enable == 1)
1718  {
1720  }
1721 
1722  if (ep->type == EP_TYPE_ISOC)
1723  {
1724  if (ep->even_odd_frame)
1725  {
1726  depctl.b.setd1pid = 1;
1727  }
1728  else
1729  {
1730  depctl.b.setd0pid = 1;
1731  }
1732  }
1733  /* EP enable */
1734  depctl.b.cnak = 1;
1735  depctl.b.epena = 1;
1736  USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL, depctl.d32);
1737  }
1738  return status;
1739 }
1740 
1741 
1748 USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
1749 {
1751  USB_OTG_DEPCTL_TypeDef depctl;
1753  USB_OTG_INEPREGS *in_regs;
1754  uint32_t fifoemptymsk = 0;
1755 
1756  depctl.d32 = 0;
1757  deptsiz.d32 = 0;
1758  /* IN endpoint */
1759  if (ep->is_in == 1)
1760  {
1761  in_regs = pdev->regs.INEP_REGS[0];
1762  depctl.d32 = USB_OTG_READ_REG32(&in_regs->DIEPCTL);
1763  deptsiz.d32 = USB_OTG_READ_REG32(&in_regs->DIEPTSIZ);
1764  /* Zero Length Packet? */
1765  if (ep->xfer_len == 0)
1766  {
1767  deptsiz.b.xfersize = 0;
1768  deptsiz.b.pktcnt = 1;
1769 
1770  }
1771  else
1772  {
1773  if (ep->xfer_len > ep->maxpacket)
1774  {
1775  ep->xfer_len = ep->maxpacket;
1776  deptsiz.b.xfersize = ep->maxpacket;
1777  }
1778  else
1779  {
1780  deptsiz.b.xfersize = ep->xfer_len;
1781  }
1782  deptsiz.b.pktcnt = 1;
1783  }
1784  USB_OTG_WRITE_REG32(&in_regs->DIEPTSIZ, deptsiz.d32);
1785 
1786  if (pdev->cfg.dma_enable == 1)
1787  {
1788  USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr);
1789  }
1790 
1791  /* EP enable, IN data in FIFO */
1792  depctl.b.cnak = 1;
1793  depctl.b.epena = 1;
1794  USB_OTG_WRITE_REG32(&in_regs->DIEPCTL, depctl.d32);
1795 
1796 
1797 
1798  if (pdev->cfg.dma_enable == 0)
1799  {
1800  /* Enable the Tx FIFO Empty Interrupt for this EP */
1801  if (ep->xfer_len > 0)
1802  {
1803  {
1804  fifoemptymsk |= 1 << ep->num;
1805  USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk);
1806  }
1807  }
1808  }
1809  }
1810  else
1811  {
1812  /* OUT endpoint */
1813  depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
1814  deptsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ);
1815  /* Program the transfer size and packet count as follows:
1816  * xfersize = N * (maxpacket + 4 - (maxpacket % 4))
1817  * pktcnt = N */
1818  if (ep->xfer_len == 0)
1819  {
1820  deptsiz.b.xfersize = ep->maxpacket;
1821  deptsiz.b.pktcnt = 1;
1822  }
1823  else
1824  {
1825  ep->xfer_len = ep->maxpacket;
1826  deptsiz.b.xfersize = ep->maxpacket;
1827  deptsiz.b.pktcnt = 1;
1828  }
1829  USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32);
1830  if (pdev->cfg.dma_enable == 1)
1831  {
1833  }
1834  /* EP enable */
1835  depctl.b.cnak = 1;
1836  depctl.b.epena = 1;
1837  USB_OTG_WRITE_REG32 (&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL), depctl.d32);
1838 
1839  }
1840  return status;
1841 }
1842 
1843 
1849 USB_OTG_STS USB_OTG_EPSetStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
1850 {
1852  USB_OTG_DEPCTL_TypeDef depctl;
1853  __IO uint32_t *depctl_addr;
1854 
1855  depctl.d32 = 0;
1856  if (ep->is_in == 1)
1857  {
1858  depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL);
1859  depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
1860  /* set the disable and stall bits */
1861  if (depctl.b.epena)
1862  {
1863  depctl.b.epdis = 1;
1864  }
1865  depctl.b.stall = 1;
1866  USB_OTG_WRITE_REG32(depctl_addr, depctl.d32);
1867  }
1868  else
1869  {
1870  depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
1871  depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
1872  /* set the stall bit */
1873  depctl.b.stall = 1;
1874  USB_OTG_WRITE_REG32(depctl_addr, depctl.d32);
1875  }
1876  return status;
1877 }
1878 
1879 
1885 USB_OTG_STS USB_OTG_EPClearStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
1886 {
1888  USB_OTG_DEPCTL_TypeDef depctl;
1889  __IO uint32_t *depctl_addr;
1890 
1891  depctl.d32 = 0;
1892 
1893  if (ep->is_in == 1)
1894  {
1895  depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL);
1896  }
1897  else
1898  {
1899  depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
1900  }
1901  depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
1902  /* clear the stall bits */
1903  depctl.b.stall = 0;
1904  if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
1905  {
1906  depctl.b.setd0pid = 1; /* DATA0 */
1907  }
1908  USB_OTG_WRITE_REG32(depctl_addr, depctl.d32);
1909  return status;
1910 }
1911 
1912 
1918 uint32_t USB_OTG_ReadDevAllOutEp_itr(USB_OTG_CORE_HANDLE *pdev)
1919 {
1920  uint32_t v;
1921  v = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT);
1922  v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK);
1923  return ((v & 0xffff0000) >> 16);
1924 }
1925 
1926 
1933 uint32_t USB_OTG_ReadDevOutEP_itr(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum)
1934 {
1935  uint32_t v;
1936  v = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[epnum]->DOEPINT);
1937  v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOEPMSK);
1938  return v;
1939 }
1940 
1941 
1947 uint32_t USB_OTG_ReadDevAllInEPItr(USB_OTG_CORE_HANDLE *pdev)
1948 {
1949  uint32_t v;
1950  v = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT);
1951  v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK);
1952  return (v & 0xffff);
1953 }
1954 
1960 void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev)
1961 {
1962  USB_OTG_DEP0XFRSIZ_TypeDef doeptsize0;
1963  doeptsize0.d32 = 0;
1964  doeptsize0.b.supcnt = 3;
1965  doeptsize0.b.pktcnt = 1;
1966  doeptsize0.b.xfersize = 8 * 3;
1967  USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPTSIZ, doeptsize0.d32 );
1968 
1969  if (pdev->cfg.dma_enable == 1)
1970  {
1971  USB_OTG_DEPCTL_TypeDef doepctl;
1972  doepctl.d32 = 0;
1974  (uint32_t)&pdev->dev.setup_packet);
1975 
1976  /* EP enable */
1977  doepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[0]->DOEPCTL);
1978  doepctl.b.epena = 1;
1979  doepctl.d32 = 0x80008000;
1980  USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPCTL, doepctl.d32);
1981  }
1982 }
1983 
1989 void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev)
1990 {
1991 
1992  USB_OTG_DCTL_TypeDef dctl;
1993  USB_OTG_DSTS_TypeDef dsts;
1994  USB_OTG_PCGCCTL_TypeDef power;
1995 
1996  if (pdev->dev.DevRemoteWakeup)
1997  {
1998  dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
1999  if(dsts.b.suspsts == 1)
2000  {
2001  if(pdev->cfg.low_power)
2002  {
2003  /* un-gate USB Core clock */
2004  power.d32 = USB_OTG_READ_REG32(pdev->regs.PCGCCTL);
2005  power.b.gatehclk = 0;
2006  power.b.stoppclk = 0;
2007  USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32);
2008  }
2009  /* active Remote wakeup signaling */
2010  dctl.d32 = 0;
2011  dctl.b.rmtwkupsig = 1;
2012  USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, 0, dctl.d32);
2013  USB_OTG_BSP_mDelay(5);
2014  USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 );
2015  }
2016  }
2017 }
2018 
2019 
2025 void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev)
2026 {
2027  if(pdev->cfg.low_power)
2028  {
2029 
2030  USB_OTG_DSTS_TypeDef dsts;
2031  USB_OTG_PCGCCTL_TypeDef power;
2032 
2033  dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
2034 
2035  if(dsts.b.suspsts == 1)
2036  {
2037  /* un-gate USB Core clock */
2038  power.d32 = USB_OTG_READ_REG32(pdev->regs.PCGCCTL);
2039  power.b.gatehclk = 0;
2040  power.b.stoppclk = 0;
2041  USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32);
2042 
2043  }
2044  }
2045 }
2046 
2052 void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev)
2053 {
2054  uint32_t i;
2055 
2056  pdev->dev.device_status = 1;
2057 
2058  for (i = 0; i < pdev->cfg.dev_endpoints ; i++)
2059  {
2060  USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF);
2061  USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF);
2062  }
2063 
2064  USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 );
2065  USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 );
2066  USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 );
2067  USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF );
2068 
2069  /* Flush the FIFO */
2070  USB_OTG_FlushRxFifo(pdev);
2071  USB_OTG_FlushTxFifo(pdev , 0x10 );
2072 }
2073 
2081 uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep)
2082 {
2083  USB_OTG_DEPCTL_TypeDef depctl;
2084  __IO uint32_t *depctl_addr;
2085  uint32_t Status = 0;
2086 
2087  depctl.d32 = 0;
2088  if (ep->is_in == 1)
2089  {
2090  depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL);
2091  depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
2092 
2093  if (depctl.b.stall == 1)
2094  {
2095  Status = USB_OTG_EP_TX_STALL;
2096  }
2097  else if (depctl.b.naksts == 1)
2098  {
2099  Status = USB_OTG_EP_TX_NAK;
2100  }
2101  else
2102  {
2103  Status = USB_OTG_EP_TX_VALID;
2104  }
2105  }
2106  else
2107  {
2108  depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
2109  depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
2110  if (depctl.b.stall == 1)
2111  {
2112  Status = USB_OTG_EP_RX_STALL;
2113  }
2114  else if (depctl.b.naksts == 1)
2115  {
2116  Status = USB_OTG_EP_RX_NAK;
2117  }
2118  else
2119  {
2120  Status = USB_OTG_EP_RX_VALID;
2121  }
2122  }
2123 
2124  /* Return the current status */
2125  return Status;
2126 }
2127 
2135 void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status)
2136 {
2137  USB_OTG_DEPCTL_TypeDef depctl;
2138  __IO uint32_t *depctl_addr;
2139 
2140  depctl.d32 = 0;
2141 
2142  /* Process for IN endpoint */
2143  if (ep->is_in == 1)
2144  {
2145  depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL);
2146  depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
2147 
2148  if (Status == USB_OTG_EP_TX_STALL)
2149  {
2150  USB_OTG_EPSetStall(pdev, ep); return;
2151  }
2152  else if (Status == USB_OTG_EP_TX_NAK)
2153  {
2154  depctl.b.snak = 1;
2155  }
2156  else if (Status == USB_OTG_EP_TX_VALID)
2157  {
2158  if (depctl.b.stall == 1)
2159  {
2160  ep->even_odd_frame = 0;
2161  USB_OTG_EPClearStall(pdev, ep);
2162  return;
2163  }
2164  depctl.b.cnak = 1;
2165  depctl.b.usbactep = 1;
2166  depctl.b.epena = 1;
2167  }
2168  else if (Status == USB_OTG_EP_TX_DIS)
2169  {
2170  depctl.b.usbactep = 0;
2171  }
2172 
2173  else
2174  {
2175  /* Do Nothing */
2176  }
2177  }
2178  else /* Process for OUT endpoint */
2179  {
2180  depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
2181  depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
2182 
2183  if (Status == USB_OTG_EP_RX_STALL) {
2184  depctl.b.stall = 1;
2185  }
2186  else if (Status == USB_OTG_EP_RX_NAK)
2187  {
2188  depctl.b.snak = 1;
2189  }
2190  else if (Status == USB_OTG_EP_RX_VALID)
2191  {
2192  if (depctl.b.stall == 1)
2193  {
2194  ep->even_odd_frame = 0;
2195  USB_OTG_EPClearStall(pdev, ep);
2196  return;
2197  }
2198  depctl.b.cnak = 1;
2199  depctl.b.usbactep = 1;
2200  depctl.b.epena = 1;
2201  }
2202  else if (Status == USB_OTG_EP_RX_DIS)
2203  {
2204  depctl.b.usbactep = 0;
2205  }
2206 
2207  else
2208  {
2209  /* Do Nothing */
2210  }
2211  }
2212 
2213  USB_OTG_WRITE_REG32(depctl_addr, depctl.d32);
2214 }
2215 
2216 #endif
2217 
2229 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
static void USB_OTG_EnableCommonInt(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_EnableCommonInt Initializes the commmon interrupts, used in both device and modes...
Definition: usb_core.c:95
USB_OTG_STS USB_OTG_FlushTxFifo(USB_OTG_CORE_HANDLE *pdev, uint32_t num)
USB_OTG_FlushTxFifo : Flush a Tx FIFO.
Definition: usb_core.c:481
#define HCCHAR_BULK
Definition: usb_defines.h:174
struct _USB_OTG_DTHRCTL_TypeDef::@79 b
Specific api&#39;s relative to the used hardware platform.
__IO uint32_t DOEPCTL
Definition: usb_regs.h:167
uint32_t disablevbussensing
Definition: usb_regs.h:640
struct _USB_OTG_HPTXSTS_TypeDef::@86 b
USB_OTG_STS USB_OTG_EnableGlobalInt(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_EnableGlobalInt Enables the controller&#39;s Global Int in the AHB Config reg.
Definition: usb_core.c:446
uint8_t phy_itface
Definition: usb_core.h:170
#define USB_OTG_DATA_FIFO_OFFSET
Definition: usb_regs.h:63
struct _USB_OTG_HCFG_TypeDef::@83 b
__IO uint32_t DIEPINT
Definition: usb_regs.h:149
USB_OTG_STS USB_OTG_SelectCore(USB_OTG_CORE_HANDLE *pdev, USB_OTG_CORE_ID_TypeDef coreID)
USB_OTG_SelectCore Initialize core registers address.
Definition: usb_core.c:222
__IO uint32_t DCFG
Definition: usb_regs.h:115
__IO uint32_t DIEPCTL
Definition: usb_regs.h:147
__IO uint32_t HCINT
Definition: usb_regs.h:207
uint8_t num
Definition: usb_core.h:138
uint32_t fslspclksel
Definition: usb_regs.h:885
USB_OTG_SPEED
Definition: usb_defines.h:233
struct _USB_OTG_HCINTMSK_TypeDef::@95 b
#define USB_OTG_PCGCCTL_OFFSET
Definition: usb_regs.h:62
#define EP_TYPE_ISOC
Definition: usb_defines.h:141
#define USB_OTG_FS_BASE_ADDR
Definition: usb_regs.h:51
#define TX3_FIFO_FS_SIZE
Definition: usb_conf.h:167
#define DCFG_FRAME_INTERVAL_80
Definition: usb_defines.h:126
struct _USB_OTG_GINTMSK_TypeDef::@64 b
__IO uint32_t DOEPINT
Definition: usb_regs.h:169
__IO uint32_t HCDMA
Definition: usb_regs.h:210
uint16_t TotalFifoSize
Definition: usb_core.h:169
#define USB_OTG_EP_RX_VALID
Definition: usb_core.h:68
#define USB_OTG_SPEED_PARAM_HIGH_IN_FULL
Definition: usb_defines.h:58
#define USB_OTG_EP_RX_NAK
Definition: usb_core.h:67
__IO uint32_t DIEPTXF[USB_OTG_MAX_TX_FIFOS]
Definition: usb_regs.h:102
#define DEP0CTL_MPS_64
Definition: usb_defines.h:131
__IO uint32_t DOEPTSIZ
Definition: usb_regs.h:171
__IO uint32_t DOEPMSK
Definition: usb_regs.h:120
#define USB_OTG_EP_RX_STALL
Definition: usb_core.h:66
struct _USB_OTG_FSIZ_TypeDef::@68 b
#define USB_OTG_EP_REG_OFFSET
Definition: usb_regs.h:56
uint32_t dma_addr
Definition: usb_core.h:148
USB_OTG_STS USB_OTG_WritePacket(USB_OTG_CORE_HANDLE *pdev, uint8_t *src, uint8_t ch_ep_num, uint16_t len)
USB_OTG_WritePacket : Writes a packet into the Tx FIFO associated with the EP.
Definition: usb_core.c:168
#define EP_TYPE_CTRL
Definition: usb_defines.h:140
uint8_t USB_OTG_IsHostMode(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_IsHostMode : Check if it is host mode.
Definition: usb_core.c:598
#define USB_OTG_HOST_PORT_REGS_OFFSET
Definition: usb_regs.h:59
uint8_t USB_OTG_IsDeviceMode(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_IsDeviceMode : Check if it is device mode.
Definition: usb_core.c:587
void USB_OTG_BSP_uDelay(const uint32_t usec)
USB_OTG_BSP_uDelay This function provides delay time in micro sec.
USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_DisableGlobalInt Enables the controller&#39;s Global Int in the AHB Config reg.
Definition: usb_core.c:464
#define DSTS_ENUMSPD_LS_PHY_6MHZ
Definition: usb_defines.h:123
USB_OTG_CORE_ID_TypeDef
Definition: usb_defines.h:190
__IO uint32_t GINTMSK
Definition: usb_regs.h:91
USB_OTG_STS
Definition: usb_core.h:79
struct _USB_OTG_DEP0XFRSIZ_TypeDef::@82 b
#define USB_OTG_SPEED_FULL
Definition: usb_defines.h:62
uint8_t dev_endpoints
Definition: usb_core.h:165
#define EP_TYPE_BULK
Definition: usb_defines.h:142
#define DSTS_ENUMSPD_FS_PHY_48MHZ
Definition: usb_defines.h:124
static volatile uint8_t * status
Definition: drv_i2c.c:102
#define USB_OTG_DEV_OUT_EP_REG_OFFSET
Definition: usb_regs.h:57
USB_OTG_INEPREGS * INEP_REGS[USB_OTG_MAX_TX_FIFOS]
Definition: usb_regs.h:227
__IO uint32_t DIEPMSK
Definition: usb_regs.h:119
USB_OTG_OUTEPREGS * OUTEP_REGS[USB_OTG_MAX_TX_FIFOS]
Definition: usb_regs.h:228
USB_OTG_CORE_CFGS cfg
Definition: usb_core.h:289
#define USB_OTG_CHAN_REGS_OFFSET
Definition: usb_regs.h:61
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ
Definition: usb_defines.h:122
__IO uint32_t DEACHMSK
Definition: usb_regs.h:130
#define USB_OTG_EP_TX_STALL
Definition: usb_core.h:61
uint32_t prtovrcurrchng
Definition: usb_regs.h:955
uint16_t mps
Definition: usb_core.h:168
#define TX0_FIFO_FS_SIZE
Definition: usb_conf.h:164
uint8_t speed
Definition: usb_core.h:166
__IO uint32_t DOEPDMA
Definition: usb_regs.h:172
#define TX2_FIFO_FS_SIZE
Definition: usb_conf.h:166
#define USB_OTG_CORE_GLOBAL_REGS_OFFSET
Definition: usb_regs.h:53
__IO uint32_t GOTGINT
Definition: usb_regs.h:86
#define USB_OTG_DATA_FIFO_SIZE
Definition: usb_regs.h:64
__IO uint32_t DIEPEMPMSK
Definition: usb_regs.h:128
__IO uint32_t DIEPTXF0_HNPTXFSIZ
Definition: usb_regs.h:95
__IO uint32_t GOTGCTL
Definition: usb_regs.h:85
#define USB_OTG_HOST_GLOBAL_REG_OFFSET
Definition: usb_regs.h:58
uint8_t even_odd_frame
Definition: usb_core.h:143
struct _USB_OTG_HPRT0_TypeDef::@88 b
#define HPRT0_PRTSPD_LOW_SPEED
Definition: usb_defines.h:166
#define USB_OTG_DEV_GLOBAL_REG_OFFSET
Definition: usb_regs.h:54
uint8_t host_channels
Definition: usb_core.h:164
#define __IO
Definition: core_cm0.h:198
#define USB_OTG_FS_MAX_PACKET_SIZE
Definition: usb_regs.h:70
#define USB_OTG_WRITE_REG32(reg, value)
Definition: usb_defines.h:226
uint8_t * xfer_buff
Definition: usb_core.h:147
uint32_t xfer_len
Definition: usb_core.h:149
#define USB_OTG_EP_RX_DIS
Definition: usb_core.h:65
__IO uint32_t HNPTXSTS
Definition: usb_regs.h:96
__IO uint32_t HCFG
Definition: usb_regs.h:186
uint8_t type
Definition: usb_core.h:141
static volatile uint8_t addr
Definition: drv_i2c.c:95
struct _USB_OTG_HCTSIZn_TypeDef::@94 b
struct _USB_OTG_GAHBCFG_TypeDef::@61 b
uint32_t USB_OTG_ReadCoreItr(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_ReadCoreItr : returns the Core Interrupt register.
Definition: usb_core.c:609
__IO uint32_t HCINTMSK
Definition: usb_regs.h:208
__IO uint32_t DCTL
Definition: usb_regs.h:116
#define USB_OTG_READ_REG32(reg)
Definition: usb_defines.h:225
__IO uint32_t DIEPDMA
Definition: usb_regs.h:152
__IO uint32_t * PCGCCTL
Definition: usb_regs.h:232
USB_OTG_GREGS * GREGS
Definition: usb_regs.h:224
void USB_OTG_BSP_mDelay(const uint32_t msec)
USB_OTG_BSP_mDelay This function provides delay time in milli sec.
__IO uint32_t DAINTMSK
Definition: usb_regs.h:122
struct _USB_OTG_GUSBCFG_TypeDef::@62 b
#define USB_OTG_EMBEDDED_PHY
Definition: usb_defines.h:65
#define USB_OTG_SPEED_PARAM_HIGH
Definition: usb_defines.h:57
__IO uint32_t HPTXSTS
Definition: usb_regs.h:190
USB_OTG_STS USB_OTG_FlushRxFifo(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_FlushRxFifo : Flush a Rx FIFO.
Definition: usb_core.c:511
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ
Definition: usb_defines.h:121
#define EP_TYPE_INTR
Definition: usb_defines.h:143
__IO uint32_t DAINT
Definition: usb_regs.h:121
#define USB_OTG_EP_TX_DIS
Definition: usb_core.h:60
#define USB_OTG_HS_BASE_ADDR
Definition: usb_regs.h:50
__IO uint32_t HCCHAR
Definition: usb_regs.h:205
__IO uint32_t GCCFG
Definition: usb_regs.h:98
#define HCFG_30_60_MHZ
Definition: usb_defines.h:168
USB_OTG_STS USB_OTG_SetCurrentMode(USB_OTG_CORE_HANDLE *pdev, uint8_t mode)
USB_OTG_SetCurrentMode : Set ID line.
Definition: usb_core.c:541
struct _USB_OTG_DAINT_TypeDef::@78 ep
#define USB_OTG_EP_TX_NAK
Definition: usb_core.h:62
static USB_OTG_STS USB_OTG_CoreReset(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_CoreReset : Soft reset of the core.
Definition: usb_core.c:123
uint8_t Sof_output
Definition: usb_core.h:171
__IO uint32_t * DFIFO[USB_OTG_MAX_TX_FIFOS]
Definition: usb_regs.h:231
Header of the Core Layer.
__IO uint32_t HAINTMSK
Definition: usb_regs.h:192
__IO uint32_t GUSBCFG
Definition: usb_regs.h:88
struct _USB_OTG_GCCFG_TypeDef::@72 b
struct _USB_OTG_HNPTXSTS_TypeDef::@69 b
#define HCFG_48_MHZ
Definition: usb_defines.h:169
__IO uint32_t GINTSTS
Definition: usb_regs.h:90
__IO uint32_t HFNUM
Definition: usb_regs.h:188
uint8_t dma_enable
Definition: usb_core.h:167
#define USB_OTG_EP_TX_VALID
Definition: usb_core.h:63
__IO uint32_t GRSTCTL
Definition: usb_regs.h:89
__IO uint32_t GAHBCFG
Definition: usb_regs.h:87
#define TX1_FIFO_FS_SIZE
Definition: usb_conf.h:165
uint32_t maxpacket
Definition: usb_core.h:145
uint32_t term_sel_dl_pulse
Definition: usb_regs.h:356
struct _USB_OTG_DEPCTL_TypeDef::@80 b
__IO uint32_t HCTSIZ
Definition: usb_regs.h:209
uint16_t tx_fifo_num
Definition: usb_core.h:144
#define RX_FIFO_FS_SIZE
Definition: usb_conf.h:163
struct _USB_OTG_PCGCCTL_TypeDef::@96 b
#define USB_OTG_HOST_CHAN_REGS_OFFSET
Definition: usb_regs.h:60
#define USB_OTG_SPEED_PARAM_FULL
Definition: usb_defines.h:59
#define USB_OTG_DEV_IN_EP_REG_OFFSET
Definition: usb_regs.h:55
void * USB_OTG_ReadPacket(USB_OTG_CORE_HANDLE *pdev, uint8_t *dest, uint16_t len)
USB_OTG_ReadPacket : Reads a packet from the Rx FIFO.
Definition: usb_core.c:198
#define HCCHAR_INTR
Definition: usb_defines.h:175
void USB_OTG_BSP_ConfigVBUS(uint32_t speed)
USB_OTG_BSP_ConfigVBUS Configures the IO for the Vbus and OverCurrent.
uint8_t coreID
Definition: usb_core.h:173
struct _USB_OTG_DIEPINTn_TypeDef::@76 b
__IO uint32_t DTHRCTL
Definition: usb_regs.h:127
uint32_t USB_OTG_GetMode(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_GetMode : Get current mode.
Definition: usb_core.c:576
struct _USB_OTG_DEPXFRSIZ_TypeDef::@81 b
__IO uint32_t DSTS
Definition: usb_regs.h:117
#define DEVICE_MODE
Definition: usb_defines.h:110
struct _USB_OTG_DSTS_TypeDef::@75 b
__IO uint32_t DIEPTSIZ
Definition: usb_regs.h:151
#define DEP0CTL_MPS_8
Definition: usb_defines.h:134
__IO uint32_t HAINT
Definition: usb_regs.h:191
uint8_t low_power
Definition: usb_core.h:172
uint32_t ulpi_ext_vbus_drv
Definition: usb_regs.h:352
uint8_t is_in
Definition: usb_core.h:139
USB_OTG_CORE_REGS regs
Definition: usb_core.h:290
__IO uint32_t * HPRT0
Definition: usb_regs.h:230
USB_OTG_HC_REGS * HC_REGS[USB_OTG_MAX_TX_FIFOS]
Definition: usb_regs.h:229
#define HCCHAR_CTRL
Definition: usb_defines.h:172
__IO uint32_t GRXFSIZ
Definition: usb_regs.h:94
USB_OTG_HREGS * HREGS
Definition: usb_regs.h:226
#define USB_OTG_ULPI_PHY
Definition: usb_defines.h:64
USB_OTG_STS USB_OTG_CoreInit(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_CoreInit Initializes the USB_OTG controller registers and prepares the core device mode or ho...
Definition: usb_core.c:329
__IO uint32_t HPTXFSIZ
Definition: usb_regs.h:101
#define HOST_MODE
Definition: usb_defines.h:111
#define USB_OTG_MODIFY_REG32(reg, clear_mask, set_mask)
Definition: usb_defines.h:227
struct _USB_OTG_DCTL_TypeDef::@74 b
struct _USB_OTG_DCFG_TypeDef::@73 b
USB_OTG_DREGS * DREGS
Definition: usb_regs.h:225
struct _USB_OTG_HCCHAR_TypeDef::@91 b
void USB_OTG_BSP_DriveVBUS(uint32_t speed, uint8_t state)
BSP_Drive_VBUS Drives the Vbus signal through IO.
uint32_t USB_OTG_ReadOtgItr(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_ReadOtgItr : returns the USB_OTG Interrupt register.
Definition: usb_core.c:623


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:20