Public Attributes | List of all members

Structure type to access the System Control Block (SCB). More...

#include <core_cm0.h>

Public Attributes

__IO uint32_t ABFSR
 
__I uint32_t ADR
 
__IO uint32_t AFSR
 
__IO uint32_t AHBPCR
 
__IO uint32_t AHBSCR
 
__IO uint32_t AIRCR
 
__IO uint32_t BFAR
 
__IO uint32_t CACR
 
__IO uint32_t CCR
 
__I uint32_t CCSIDR
 
__IO uint32_t CFSR
 
__I uint32_t CLIDR
 
__IO uint32_t CPACR
 
__I uint32_t CPUID
 
__IO uint32_t CSSELR
 
__I uint32_t CTR
 
__O uint32_t DCCIMVAC
 
__O uint32_t DCCISW
 
__O uint32_t DCCMVAC
 
__O uint32_t DCCMVAU
 
__O uint32_t DCCSW
 
__O uint32_t DCIMVAU
 
__O uint32_t DCISW
 
__I uint32_t DFR
 
__IO uint32_t DFSR
 
__IO uint32_t DTCMCR
 
__IO uint32_t HFSR
 
__O uint32_t ICIALLU
 
__O uint32_t ICIMVAU
 
__IO uint32_t ICSR
 
__I uint32_t ID_AFR
 
__I uint32_t ID_DFR
 
__I uint32_t ID_ISAR [5]
 
__I uint32_t ID_MFR [4]
 
__I uint32_t ID_PFR [2]
 
__I uint32_t ISAR [5]
 
__IO uint32_t ITCMCR
 
__IO uint32_t MMFAR
 
__I uint32_t MMFR [4]
 
__I uint32_t MVFR0
 
__I uint32_t MVFR1
 
__I uint32_t MVFR2
 
__I uint32_t PFR [2]
 
uint32_t RESERVED0
 
uint32_t RESERVED1
 
uint32_t RESERVED3 [93]
 
uint32_t RESERVED4 [15]
 
uint32_t RESERVED5 [1]
 
uint32_t RESERVED6 [1]
 
uint32_t RESERVED7 [6]
 
uint32_t RESERVED8 [1]
 
__IO uint32_t SCR
 
__IO uint32_t SFCR
 
__IO uint32_t SHCSR
 
__IO uint32_t SHP [2]
 
__IO uint8_t SHP [12]
 
__IO uint8_t SHPR [12]
 
__O uint32_t STIR
 
__IO uint32_t VTOR
 

Detailed Description

Structure type to access the System Control Block (SCB).

Definition at line 334 of file core_cm0.h.

Member Data Documentation

__IO uint32_t SCB_Type::ABFSR

Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register

Definition at line 461 of file core_cm7.h.

__I uint32_t SCB_Type::ADR

Offset: 0x04C (R/ ) Auxiliary Feature Register

Offset: 0x4C Auxiliary Feature Register

Definition at line 366 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__IO uint32_t SCB_Type::AFSR

Offset: 0x03C (R/W) Auxiliary Fault Status Register

Offset: 0x3C Auxiliary Fault Status Register

Definition at line 363 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__IO uint32_t SCB_Type::AHBPCR

Offset: 0x298 (R/W) AHBP Control Register

Definition at line 457 of file core_cm7.h.

__IO uint32_t SCB_Type::AHBSCR

Offset: 0x2A0 (R/W) AHB Slave Control Register

Definition at line 459 of file core_cm7.h.

__IO uint32_t SCB_Type::AIRCR

Offset: 0x00C (R/W) Application Interrupt and Reset Control Register

Offset: 0x0C Application Interrupt / Reset Control Register

Definition at line 339 of file core_cm0.h.

__IO uint32_t SCB_Type::BFAR

Offset: 0x038 (R/W) BusFault Address Register

Offset: 0x38 Bus Fault Address Register

Definition at line 362 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__IO uint32_t SCB_Type::CACR

Offset: 0x29C (R/W) L1 Cache Control Register

Definition at line 458 of file core_cm7.h.

__IO uint32_t SCB_Type::CCR

Offset: 0x014 (R/W) Configuration Control Register

Offset: 0x14 Configuration Control Register

Definition at line 341 of file core_cm0.h.

__I uint32_t SCB_Type::CCSIDR

Offset: 0x080 (R/ ) Cache Size ID Register

Definition at line 434 of file core_cm7.h.

__IO uint32_t SCB_Type::CFSR

Offset: 0x028 (R/W) Configurable Fault Status Register

Offset: 0x28 Configurable Fault Status Register

Definition at line 358 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__I uint32_t SCB_Type::CLIDR

Offset: 0x078 (R/ ) Cache Level ID register

Definition at line 432 of file core_cm7.h.

__IO uint32_t SCB_Type::CPACR

Offset: 0x088 (R/W) Coprocessor Access Control Register

Definition at line 370 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__I uint32_t SCB_Type::CPUID

Offset: 0x000 (R/ ) CPUID Base Register

Offset: 0x00 CPU ID Base Register

Definition at line 336 of file core_cm0.h.

__IO uint32_t SCB_Type::CSSELR

Offset: 0x084 (R/W) Cache Size Selection Register

Definition at line 435 of file core_cm7.h.

__I uint32_t SCB_Type::CTR

Offset: 0x07C (R/ ) Cache Type register

Definition at line 433 of file core_cm7.h.

__O uint32_t SCB_Type::DCCIMVAC

Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC

Definition at line 452 of file core_cm7.h.

__O uint32_t SCB_Type::DCCISW

Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way

Definition at line 453 of file core_cm7.h.

__O uint32_t SCB_Type::DCCMVAC

Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC

Definition at line 450 of file core_cm7.h.

__O uint32_t SCB_Type::DCCMVAU

Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU

Definition at line 449 of file core_cm7.h.

__O uint32_t SCB_Type::DCCSW

Offset: 0x26C ( /W) D-Cache Clean by Set-way

Definition at line 451 of file core_cm7.h.

__O uint32_t SCB_Type::DCIMVAU

Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC

Definition at line 447 of file core_cm7.h.

__O uint32_t SCB_Type::DCISW

Offset: 0x260 ( /W) D-Cache Invalidate by Set-way

Definition at line 448 of file core_cm7.h.

__I uint32_t SCB_Type::DFR

Offset: 0x048 (R/ ) Debug Feature Register

Offset: 0x48 Debug Feature Register

Definition at line 365 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__IO uint32_t SCB_Type::DFSR

Offset: 0x030 (R/W) Debug Fault Status Register

Offset: 0x30 Debug Fault Status Register

Definition at line 360 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__IO uint32_t SCB_Type::DTCMCR

Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers

Definition at line 456 of file core_cm7.h.

__IO uint32_t SCB_Type::HFSR

Offset: 0x02C (R/W) HardFault Status Register

Offset: 0x2C Hard Fault Status Register

Definition at line 359 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__O uint32_t SCB_Type::ICIALLU

Offset: 0x250 ( /W) I-Cache Invalidate All to PoU

Definition at line 444 of file core_cm7.h.

__O uint32_t SCB_Type::ICIMVAU

Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU

Definition at line 446 of file core_cm7.h.

__IO uint32_t SCB_Type::ICSR

Offset: 0x004 (R/W) Interrupt Control and State Register

Offset: 0x04 Interrupt Control State Register

Definition at line 337 of file core_cm0.h.

__I uint32_t SCB_Type::ID_AFR

Offset: 0x04C (R/ ) Auxiliary Feature Register

Definition at line 428 of file core_cm7.h.

__I uint32_t SCB_Type::ID_DFR

Offset: 0x048 (R/ ) Debug Feature Register

Definition at line 427 of file core_cm7.h.

__I uint32_t SCB_Type::ID_ISAR[5]

Offset: 0x060 (R/ ) Instruction Set Attributes Register

Definition at line 430 of file core_cm7.h.

__I uint32_t SCB_Type::ID_MFR[4]

Offset: 0x050 (R/ ) Memory Model Feature Register

Definition at line 429 of file core_cm7.h.

__I uint32_t SCB_Type::ID_PFR[2]

Offset: 0x040 (R/ ) Processor Feature Register

Definition at line 426 of file core_cm7.h.

__I uint32_t SCB_Type::ISAR

Offset: 0x060 (R/ ) Instruction Set Attributes Register

Offset: 0x60 ISA Feature Register

Definition at line 368 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__IO uint32_t SCB_Type::ITCMCR

Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register

Definition at line 455 of file core_cm7.h.

__IO uint32_t SCB_Type::MMFAR

Offset: 0x034 (R/W) MemManage Fault Address Register

Offset: 0x34 Mem Manage Address Register

Definition at line 361 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__I uint32_t SCB_Type::MMFR

Offset: 0x050 (R/ ) Memory Model Feature Register

Offset: 0x50 Memory Model Feature Register

Definition at line 367 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__I uint32_t SCB_Type::MVFR0

Offset: 0x240 (R/ ) Media and VFP Feature Register 0

Definition at line 440 of file core_cm7.h.

__I uint32_t SCB_Type::MVFR1

Offset: 0x244 (R/ ) Media and VFP Feature Register 1

Definition at line 441 of file core_cm7.h.

__I uint32_t SCB_Type::MVFR2

Offset: 0x248 (R/ ) Media and VFP Feature Register 1

Definition at line 442 of file core_cm7.h.

__I uint32_t SCB_Type::PFR

Offset: 0x040 (R/ ) Processor Feature Register

Offset: 0x40 Processor Feature Register

Definition at line 364 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

uint32_t SCB_Type::RESERVED0

Definition at line 338 of file core_cm0.h.

uint32_t SCB_Type::RESERVED1

Definition at line 342 of file core_cm0.h.

uint32_t SCB_Type::RESERVED3[93]

Definition at line 437 of file core_cm7.h.

uint32_t SCB_Type::RESERVED4[15]

Definition at line 439 of file core_cm7.h.

uint32_t SCB_Type::RESERVED5[1]

Definition at line 443 of file core_cm7.h.

uint32_t SCB_Type::RESERVED6[1]

Definition at line 445 of file core_cm7.h.

uint32_t SCB_Type::RESERVED7[6]

Definition at line 454 of file core_cm7.h.

uint32_t SCB_Type::RESERVED8[1]

Definition at line 460 of file core_cm7.h.

__IO uint32_t SCB_Type::SCR

Offset: 0x010 (R/W) System Control Register

Offset: 0x10 System Control Register

Definition at line 340 of file core_cm0.h.

__IO uint32_t SCB_Type::SFCR

Offset: 0x290 (R/W) Security Features Register

Definition at line 352 of file core_sc000.h.

__IO uint32_t SCB_Type::SHCSR

Offset: 0x024 (R/W) System Handler Control and State Register

Offset: 0x24 System Handler Control and State Register

Definition at line 344 of file core_cm0.h.

__IO uint8_t SCB_Type::SHP

Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED

Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)

Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15)

Definition at line 343 of file core_cm0.h.

__IO uint8_t SCB_Type::SHP[12]

Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)

Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15)

Definition at line 356 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__IO uint8_t SCB_Type::SHPR[12]

Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)

Definition at line 418 of file core_cm7.h.

__O uint32_t SCB_Type::STIR

Offset: 0x200 ( /W) Software Triggered Interrupt Register

Definition at line 438 of file core_cm7.h.

__IO uint32_t SCB_Type::VTOR

Offset: 0x008 (R/W) Vector Table Offset Register

Offset: 0x08 Vector Table Offset Register

Definition at line 352 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.


The documentation for this struct was generated from the following files:


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Sep 3 2020 03:22:25