Public Attributes | List of all members

Structure type to access the Nested Vectored Interrupt Controller (NVIC). More...

#include <core_cm0.h>

Public Attributes

__IO uint32_t IABR [8]
 
__IO uint32_t ICER [1]
 
__IO uint32_t ICPR [1]
 
__IO uint32_t IP [8]
 
__IO uint8_t IP [240]
 
__IO uint32_t ISER [1]
 
__IO uint32_t ISPR [1]
 
uint32_t RESERVED0 [31]
 
uint32_t RESERVED2 [31]
 
uint32_t RESERVED3 [31]
 
uint32_t RESERVED4 [64]
 
uint32_t RESERVED5 [644]
 
uint32_t RSERVED1 [31]
 
__O uint32_t STIR
 

Detailed Description

Structure type to access the Nested Vectored Interrupt Controller (NVIC).

Definition at line 309 of file core_cm0.h.

Member Data Documentation

__IO uint32_t NVIC_Type::IABR

Offset: 0x200 (R/W) Interrupt Active bit Register

Offset: 0x200 Interrupt Active bit Register

Definition at line 326 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__IO uint32_t NVIC_Type::ICER

Offset: 0x080 (R/W) Interrupt Clear Enable Register

Offset: 0x080 Interrupt Clear Enable Register

Definition at line 313 of file core_cm0.h.

__IO uint32_t NVIC_Type::ICPR

Offset: 0x180 (R/W) Interrupt Clear Pending Register

Offset: 0x180 Interrupt Clear Pending Register

Definition at line 317 of file core_cm0.h.

__IO uint8_t NVIC_Type::IP

Offset: 0x300 (R/W) Interrupt Priority Register

Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)

Offset: 0x300 Interrupt Priority Register (8Bit wide)

Definition at line 320 of file core_cm0.h.

__IO uint8_t NVIC_Type::IP[240]

Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)

Offset: 0x300 Interrupt Priority Register (8Bit wide)

Definition at line 328 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.

__IO uint32_t NVIC_Type::ISER

Offset: 0x000 (R/W) Interrupt Set Enable Register

Offset: 0x000 Interrupt Set Enable Register

Definition at line 311 of file core_cm0.h.

__IO uint32_t NVIC_Type::ISPR

Offset: 0x100 (R/W) Interrupt Set Pending Register

Offset: 0x100 Interrupt Set Pending Register

Definition at line 315 of file core_cm0.h.

uint32_t NVIC_Type::RESERVED0

Definition at line 312 of file core_cm0.h.

uint32_t NVIC_Type::RESERVED2

Definition at line 316 of file core_cm0.h.

uint32_t NVIC_Type::RESERVED3

Definition at line 318 of file core_cm0.h.

uint32_t NVIC_Type::RESERVED4

Definition at line 319 of file core_cm0.h.

uint32_t NVIC_Type::RESERVED5
uint32_t NVIC_Type::RSERVED1

Definition at line 314 of file core_cm0.h.

__O uint32_t NVIC_Type::STIR

Offset: 0xE00 ( /W) Software Trigger Interrupt Register

Offset: 0xE00 Software Trigger Interrupt Register

Definition at line 330 of file airbourne/airbourne/lib/CMSIS/CM4/CoreSupport/core_cm3.h.


The documentation for this struct was generated from the following files:


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Fri Jul 24 2020 03:20:15