stm32f4xx_sdio.c
Go to the documentation of this file.
1 
155 /* Includes ------------------------------------------------------------------*/
156 #include "stm32f4xx_sdio.h"
157 #include "stm32f4xx_rcc.h"
158 
168 /* Private typedef -----------------------------------------------------------*/
169 /* Private define ------------------------------------------------------------*/
170 
171 /* ------------ SDIO registers bit address in the alias region ----------- */
172 #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
173 
174 /* --- CLKCR Register ---*/
175 /* Alias word address of CLKEN bit */
176 #define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
177 #define CLKEN_BitNumber 0x08
178 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
179 
180 /* --- CMD Register ---*/
181 /* Alias word address of SDIOSUSPEND bit */
182 #define CMD_OFFSET (SDIO_OFFSET + 0x0C)
183 #define SDIOSUSPEND_BitNumber 0x0B
184 #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
185 
186 /* Alias word address of ENCMDCOMPL bit */
187 #define ENCMDCOMPL_BitNumber 0x0C
188 #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
189 
190 /* Alias word address of NIEN bit */
191 #define NIEN_BitNumber 0x0D
192 #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
193 
194 /* Alias word address of ATACMD bit */
195 #define ATACMD_BitNumber 0x0E
196 #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
197 
198 /* --- DCTRL Register ---*/
199 /* Alias word address of DMAEN bit */
200 #define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
201 #define DMAEN_BitNumber 0x03
202 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
203 
204 /* Alias word address of RWSTART bit */
205 #define RWSTART_BitNumber 0x08
206 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
207 
208 /* Alias word address of RWSTOP bit */
209 #define RWSTOP_BitNumber 0x09
210 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
211 
212 /* Alias word address of RWMOD bit */
213 #define RWMOD_BitNumber 0x0A
214 #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
215 
216 /* Alias word address of SDIOEN bit */
217 #define SDIOEN_BitNumber 0x0B
218 #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
219 
220 /* ---------------------- SDIO registers bit mask ------------------------ */
221 /* --- CLKCR Register ---*/
222 /* CLKCR register clear mask */
223 #define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
224 
225 /* --- PWRCTRL Register ---*/
226 /* SDIO PWRCTRL Mask */
227 #define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
228 
229 /* --- DCTRL Register ---*/
230 /* SDIO DCTRL Clear Mask */
231 #define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
232 
233 /* --- CMD Register ---*/
234 /* CMD Register clear mask */
235 #define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
236 
237 /* SDIO RESP Registers Address */
238 #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
239 
240 /* Private macro -------------------------------------------------------------*/
241 /* Private variables ---------------------------------------------------------*/
242 /* Private function prototypes -----------------------------------------------*/
243 /* Private functions ---------------------------------------------------------*/
244 
266 void SDIO_DeInit(void)
267 {
270 }
271 
279 void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
280 {
281  uint32_t tmpreg = 0;
282 
283  /* Check the parameters */
287  assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
289 
290 /*---------------------------- SDIO CLKCR Configuration ------------------------*/
291  /* Get the SDIO CLKCR value */
292  tmpreg = SDIO->CLKCR;
293 
294  /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
295  tmpreg &= CLKCR_CLEAR_MASK;
296 
297  /* Set CLKDIV bits according to SDIO_ClockDiv value */
298  /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
299  /* Set BYPASS bit according to SDIO_ClockBypass value */
300  /* Set WIDBUS bits according to SDIO_BusWide value */
301  /* Set NEGEDGE bits according to SDIO_ClockEdge value */
302  /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
303  tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
304  SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
305  SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
306 
307  /* Write to SDIO CLKCR */
308  SDIO->CLKCR = tmpreg;
309 }
310 
317 void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
318 {
319  /* SDIO_InitStruct members default value */
320  SDIO_InitStruct->SDIO_ClockDiv = 0x00;
321  SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
322  SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
324  SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
326 }
327 
335 {
336  /* Check the parameters */
338 
339  *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
340 }
341 
350 void SDIO_SetPowerState(uint32_t SDIO_PowerState)
351 {
352  /* Check the parameters */
353  assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
354 
355  SDIO->POWER = SDIO_PowerState;
356 }
357 
367 uint32_t SDIO_GetPowerState(void)
368 {
369  return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
370 }
371 
399 void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
400 {
401  uint32_t tmpreg = 0;
402 
403  /* Check the parameters */
404  assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
405  assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
406  assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
407  assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
408 
409 /*---------------------------- SDIO ARG Configuration ------------------------*/
410  /* Set the SDIO Argument value */
411  SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
412 
413 /*---------------------------- SDIO CMD Configuration ------------------------*/
414  /* Get the SDIO CMD value */
415  tmpreg = SDIO->CMD;
416  /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
417  tmpreg &= CMD_CLEAR_MASK;
418  /* Set CMDINDEX bits according to SDIO_CmdIndex value */
419  /* Set WAITRESP bits according to SDIO_Response value */
420  /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
421  /* Set CPSMEN bits according to SDIO_CPSM value */
422  tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
423  | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
424 
425  /* Write to SDIO CMD */
426  SDIO->CMD = tmpreg;
427 }
428 
435 void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
436 {
437  /* SDIO_CmdInitStruct members default value */
438  SDIO_CmdInitStruct->SDIO_Argument = 0x00;
439  SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
440  SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
441  SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
442  SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
443 }
444 
451 {
452  return (uint8_t)(SDIO->RESPCMD);
453 }
454 
465 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
466 {
467  __IO uint32_t tmp = 0;
468 
469  /* Check the parameters */
470  assert_param(IS_SDIO_RESP(SDIO_RESP));
471 
472  tmp = SDIO_RESP_ADDR + SDIO_RESP;
473 
474  return (*(__IO uint32_t *) tmp);
475 }
476 
503 void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
504 {
505  uint32_t tmpreg = 0;
506 
507  /* Check the parameters */
508  assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
509  assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
510  assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
512  assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
513 
514 /*---------------------------- SDIO DTIMER Configuration ---------------------*/
515  /* Set the SDIO Data TimeOut value */
516  SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
517 
518 /*---------------------------- SDIO DLEN Configuration -----------------------*/
519  /* Set the SDIO DataLength value */
520  SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
521 
522 /*---------------------------- SDIO DCTRL Configuration ----------------------*/
523  /* Get the SDIO DCTRL value */
524  tmpreg = SDIO->DCTRL;
525  /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
526  tmpreg &= DCTRL_CLEAR_MASK;
527  /* Set DEN bit according to SDIO_DPSM value */
528  /* Set DTMODE bit according to SDIO_TransferMode value */
529  /* Set DTDIR bit according to SDIO_TransferDir value */
530  /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
531  tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
532  | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
533 
534  /* Write to SDIO DCTRL */
535  SDIO->DCTRL = tmpreg;
536 }
537 
544 void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
545 {
546  /* SDIO_DataInitStruct members default value */
547  SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
548  SDIO_DataInitStruct->SDIO_DataLength = 0x00;
549  SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
550  SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
551  SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
552  SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
553 }
554 
560 uint32_t SDIO_GetDataCounter(void)
561 {
562  return SDIO->DCOUNT;
563 }
564 
570 uint32_t SDIO_ReadData(void)
571 {
572  return SDIO->FIFO;
573 }
574 
580 void SDIO_WriteData(uint32_t Data)
581 {
582  SDIO->FIFO = Data;
583 }
584 
590 uint32_t SDIO_GetFIFOCount(void)
591 {
592  return SDIO->FIFOCNT;
593 }
594 
620 {
621  /* Check the parameters */
623 
624  *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
625 }
626 
634 {
635  /* Check the parameters */
637 
638  *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
639 }
640 
649 void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
650 {
651  /* Check the parameters */
652  assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
653 
654  *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
655 }
656 
664 {
665  /* Check the parameters */
667 
668  *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
669 }
670 
678 {
679  /* Check the parameters */
681 
682  *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
683 }
684 
710 {
711  /* Check the parameters */
713 
714  *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
715 }
716 
724 {
725  /* Check the parameters */
727 
728  *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
729 }
730 
738 {
739  /* Check the parameters */
741 
742  *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
743 }
744 
770 {
771  /* Check the parameters */
773 
774  *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
775 }
776 
827 void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
828 {
829  /* Check the parameters */
830  assert_param(IS_SDIO_IT(SDIO_IT));
832 
833  if (NewState != DISABLE)
834  {
835  /* Enable the SDIO interrupts */
836  SDIO->MASK |= SDIO_IT;
837  }
838  else
839  {
840  /* Disable the SDIO interrupts */
841  SDIO->MASK &= ~SDIO_IT;
842  }
843 }
844 
875 FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
876 {
877  FlagStatus bitstatus = RESET;
878 
879  /* Check the parameters */
880  assert_param(IS_SDIO_FLAG(SDIO_FLAG));
881 
882  if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
883  {
884  bitstatus = SET;
885  }
886  else
887  {
888  bitstatus = RESET;
889  }
890  return bitstatus;
891 }
892 
912 void SDIO_ClearFlag(uint32_t SDIO_FLAG)
913 {
914  /* Check the parameters */
915  assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
916 
917  SDIO->ICR = SDIO_FLAG;
918 }
919 
951 ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
952 {
953  ITStatus bitstatus = RESET;
954 
955  /* Check the parameters */
956  assert_param(IS_SDIO_GET_IT(SDIO_IT));
957  if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
958  {
959  bitstatus = SET;
960  }
961  else
962  {
963  bitstatus = RESET;
964  }
965  return bitstatus;
966 }
967 
987 void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
988 {
989  /* Check the parameters */
990  assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
991 
992  SDIO->ICR = SDIO_IT;
993 }
994 
1011 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
#define IS_SDIO_TRANSFER_MODE(MODE)
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
Checks whether the specified SDIO flag is set or not.
FlagStatus
Definition: stm32f4xx.h:706
void SDIO_WriteData(uint32_t Data)
Write one data word to Tx FIFO.
void SDIO_StopSDIOReadWait(FunctionalState NewState)
Stops the SD I/O Read Wait operation.
void SDIO_CommandCompletionCmd(FunctionalState NewState)
Enables or disables the command completion signal.
#define CLKCR_CLEAR_MASK
FunctionalState
Definition: stm32f4xx.h:708
#define IS_SDIO_CLEAR_FLAG(FLAG)
#define IS_SDIO_GET_IT(IT)
#define CMD_CLEAR_MASK
#define IS_SDIO_CLOCK_EDGE(EDGE)
uint32_t SDIO_GetPowerState(void)
Gets the power status of the controller.
#define DCTRL_CLEAR_MASK
uint32_t SDIO_ClockPowerSave
#define SDIO_DPSM_Disable
#define IS_SDIO_DATA_LENGTH(LENGTH)
#define IS_SDIO_IT(IT)
#define IS_SDIO_RESP(RESP)
#define DCTRL_RWSTART_BB
void assert_param(int val)
#define CLKCR_CLKEN_BB
#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL)
void SDIO_StructInit(SDIO_InitTypeDef *SDIO_InitStruct)
Fills each SDIO_InitStruct member with its default value.
#define SDIO_DataBlockSize_1b
void SDIO_ClearFlag(uint32_t SDIO_FLAG)
Clears the SDIO's pending flags.
#define IS_SDIO_READWAIT_MODE(MODE)
#define SDIO_TransferDir_ToCard
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
#define IS_SDIO_TRANSFER_DIR(DIR)
#define IS_SDIO_CLEAR_IT(IT)
void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
Clears the SDIO's interrupt pending bits.
#define SDIO_BusWide_1b
#define DCTRL_SDIOEN_BB
Definition: stm32f4xx.h:706
uint8_t SDIO_GetCommandResponse(void)
Returns command index of last command for which response received.
#define DCTRL_RWMOD_BB
#define IS_SDIO_CMD_INDEX(INDEX)
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
Enables or disables the SDIO interrupts.
#define SDIO
Definition: stm32f4xx.h:2086
enum FlagStatus ITStatus
void SDIO_StartSDIOReadWait(FunctionalState NewState)
Starts the SD I/O Read Wait operation.
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
Sets one of the two options of inserting read wait interval.
void SDIO_CEATAITCmd(FunctionalState NewState)
Enables or disables the CE-ATA interrupt.
#define IS_SDIO_CPSM(CPSM)
#define CMD_SDIOSUSPEND_BB
#define IS_SDIO_BLOCK_SIZE(SIZE)
void SDIO_SetSDIOOperation(FunctionalState NewState)
Enables or disables the SD I/O Mode Operation.
#define __IO
Definition: core_cm0.h:198
uint32_t SDIO_GetFIFOCount(void)
Returns the number of words left to be written to or read from FIFO.
#define IS_SDIO_CLOCK_POWER_SAVE(SAVE)
void SDIO_DataStructInit(SDIO_DataInitTypeDef *SDIO_DataInitStruct)
Fills each SDIO_DataInitStruct member with its default value.
#define SDIO_ClockEdge_Rising
#define SDIO_Wait_No
void SDIO_SetPowerState(uint32_t SDIO_PowerState)
Sets the power status of the controller.
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
Returns response received from the card for the last command.
uint32_t SDIO_ReadData(void)
Read one data word from Rx FIFO.
void SDIO_DataConfig(SDIO_DataInitTypeDef *SDIO_DataInitStruct)
Initializes the SDIO data path according to the specified parameters in the SDIO_DataInitStruct.
void SDIO_ClockCmd(FunctionalState NewState)
Enables or disables the SDIO Clock.
#define DCTRL_RWSTOP_BB
uint32_t SDIO_BusWide
#define IS_SDIO_FLAG(FLAG)
#define IS_SDIO_BUS_WIDE(WIDE)
This file contains all the functions prototypes for the SDIO firmware library.
#define SDIO_ClockPowerSave_Disable
uint32_t SDIO_ClockBypass
void SDIO_Init(SDIO_InitTypeDef *SDIO_InitStruct)
Initializes the SDIO peripheral according to the specified parameters in the SDIO_InitStruct.
#define SDIO_RESP_ADDR
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
#define IS_SDIO_POWER_STATE(STATE)
void SDIO_DeInit(void)
Deinitializes the SDIO peripheral registers to their default reset values.
#define SDIO_CPSM_Disable
uint32_t SDIO_HardwareFlowControl
#define CMD_NIEN_BB
void SDIO_SendCEATACmd(FunctionalState NewState)
Sends CE-ATA command (CMD61).
uint32_t SDIO_ClockEdge
#define SDIO_ClockBypass_Disable
#define IS_SDIO_RESPONSE(RESPONSE)
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
Checks whether the specified SDIO interrupt has occurred or not.
#define SDIO_TransferMode_Block
#define IS_SDIO_CLOCK_BYPASS(BYPASS)
#define IS_SDIO_DPSM(DPSM)
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
Enables or disables the SD I/O Mode suspend command sending.
uint32_t SDIO_GetDataCounter(void)
Returns number of remaining data bytes to be transferred.
#define SDIO_HardwareFlowControl_Disable
#define SDIO_Response_No
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
Initializes the SDIO Command according to the specified parameters in the SDIO_CmdInitStruct and send...
#define CMD_ENCMDCOMPL_BB
#define IS_SDIO_WAIT(WAIT)
void SDIO_DMACmd(FunctionalState NewState)
Enables or disables the SDIO DMA request.
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
Fills each SDIO_CmdInitStruct member with its default value.
#define CMD_ATACMD_BB
#define DCTRL_DMAEN_BB
#define PWR_PWRCTRL_MASK


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19