stm32f4xx_pwr.c
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1 
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f4xx_pwr.h"
39 #include "stm32f4xx_rcc.h"
40 
50 /* Private typedef -----------------------------------------------------------*/
51 /* Private define ------------------------------------------------------------*/
52 /* --------- PWR registers bit address in the alias region ---------- */
53 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
54 
55 /* --- CR Register ---*/
56 
57 /* Alias word address of DBP bit */
58 #define CR_OFFSET (PWR_OFFSET + 0x00)
59 #define DBP_BitNumber 0x08
60 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
61 
62 /* Alias word address of PVDE bit */
63 #define PVDE_BitNumber 0x04
64 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
65 
66 /* Alias word address of FPDS bit */
67 #define FPDS_BitNumber 0x09
68 #define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
69 
70 /* Alias word address of PMODE bit */
71 #define PMODE_BitNumber 0x0E
72 #define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
73 
74 
75 /* --- CSR Register ---*/
76 
77 /* Alias word address of EWUP bit */
78 #define CSR_OFFSET (PWR_OFFSET + 0x04)
79 #define EWUP_BitNumber 0x08
80 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
81 
82 /* Alias word address of BRE bit */
83 #define BRE_BitNumber 0x09
84 #define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
85 
86 /* ------------------ PWR registers bit mask ------------------------ */
87 
88 /* CR register bit mask */
89 #define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
90 #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
91 #define CR_VOS_MASK ((uint32_t)0xFFFF3FFF)
92 
93 /* Private macro -------------------------------------------------------------*/
94 /* Private variables ---------------------------------------------------------*/
95 /* Private function prototypes -----------------------------------------------*/
96 /* Private functions ---------------------------------------------------------*/
97 
127 void PWR_DeInit(void)
128 {
131 }
132 
143 {
144  /* Check the parameters */
146 
147  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
148 }
149 
190 void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
191 {
192  uint32_t tmpreg = 0;
193 
194  /* Check the parameters */
195  assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
196 
197  tmpreg = PWR->CR;
198 
199  /* Clear PLS[7:5] bits */
200  tmpreg &= CR_PLS_MASK;
201 
202  /* Set PLS[7:5] bits according to PWR_PVDLevel value */
203  tmpreg |= PWR_PVDLevel;
204 
205  /* Store the new value */
206  PWR->CR = tmpreg;
207 }
208 
216 {
217  /* Check the parameters */
219 
220  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
221 }
222 
250 {
251  /* Check the parameters */
253 
254  *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
255 }
256 
311 {
312  /* Check the parameters */
314 
315  *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState;
316 }
317 
332 void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
333 {
334  uint32_t tmpreg = 0;
335 
336  /* Check the parameters */
337  assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage));
338 
339  tmpreg = PWR->CR;
340 
341  /* Clear VOS[15:14] bits */
342  tmpreg &= CR_VOS_MASK;
343 
344  /* Set VOS[15:14] bits according to PWR_Regulator_Voltage value */
345  tmpreg |= PWR_Regulator_Voltage;
346 
347  /* Store the new value */
348  PWR->CR = tmpreg;
349 }
350 
379 {
380  /* Check the parameters */
382 
383  *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState;
384 }
385 
522 void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
523 {
524  uint32_t tmpreg = 0;
525 
526  /* Check the parameters */
527  assert_param(IS_PWR_REGULATOR(PWR_Regulator));
528  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
529 
530  /* Select the regulator state in STOP mode ---------------------------------*/
531  tmpreg = PWR->CR;
532  /* Clear PDDS and LPDSR bits */
533  tmpreg &= CR_DS_MASK;
534 
535  /* Set LPDSR bit according to PWR_Regulator value */
536  tmpreg |= PWR_Regulator;
537 
538  /* Store the new value */
539  PWR->CR = tmpreg;
540 
541  /* Set SLEEPDEEP bit of Cortex System Control Register */
542  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
543 
544  /* Select STOP mode entry --------------------------------------------------*/
545  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
546  {
547  /* Request Wait For Interrupt */
548  __WFI();
549  }
550  else
551  {
552  /* Request Wait For Event */
553  __WFE();
554  }
555  /* Reset SLEEPDEEP bit of Cortex System Control Register */
556  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
557 }
558 
571 {
572  /* Clear Wakeup flag */
573  PWR->CR |= PWR_CR_CWUF;
574 
575  /* Select STANDBY mode */
576  PWR->CR |= PWR_CR_PDDS;
577 
578  /* Set SLEEPDEEP bit of Cortex System Control Register */
579  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
580 
581 /* This option is used to ensure that store operations are completed */
582 #if defined ( __CC_ARM )
583  __force_stores();
584 #endif
585  /* Request Wait For Interrupt */
586  __WFI();
587 }
588 
627 FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
628 {
629  FlagStatus bitstatus = RESET;
630 
631  /* Check the parameters */
632  assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
633 
634  if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
635  {
636  bitstatus = SET;
637  }
638  else
639  {
640  bitstatus = RESET;
641  }
642  /* Return the flag status */
643  return bitstatus;
644 }
645 
654 void PWR_ClearFlag(uint32_t PWR_FLAG)
655 {
656  /* Check the parameters */
657  assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
658 
659  PWR->CR |= PWR_FLAG << 2;
660 }
661 
678 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
FlagStatus
Definition: stm32f4xx.h:706
FunctionalState
Definition: stm32f4xx.h:708
#define SCB_SCR_SLEEPDEEP_Msk
Definition: core_cm0.h:412
#define IS_PWR_CLEAR_FLAG(FLAG)
void PWR_EnterSTANDBYMode(void)
Enters STANDBY mode.
#define CR_PLS_MASK
Definition: stm32f4xx_pwr.c:90
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).
void PWR_BackupRegulatorCmd(FunctionalState NewState)
Enables or disables the Backup Regulator.
This file contains all the functions prototypes for the PWR firmware library.
void assert_param(int val)
#define PWR_CR_CWUF
Definition: stm32f4xx.h:8354
void PWR_ClearFlag(uint32_t PWR_FLAG)
Clears the PWR&#39;s pending flags.
#define IS_PWR_PVD_LEVEL(LEVEL)
Definition: stm32f4xx_pwr.h:68
#define CR_DS_MASK
Definition: stm32f4xx_pwr.c:89
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
#define CSR_BRE_BB
Definition: stm32f4xx_pwr.c:84
#define IS_PWR_STOP_ENTRY(ENTRY)
Definition: stm32f4xx_pwr.h:95
Definition: stm32f4xx.h:706
#define SCB
Definition: core_cm0.h:503
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
void PWR_BackupAccessCmd(FunctionalState NewState)
Enables or disables access to the backup domain (RTC registers, RTC backup data registers and backup ...
#define CR_FPDS_BB
Definition: stm32f4xx_pwr.c:68
#define __IO
Definition: core_cm0.h:198
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
Checks whether the specified PWR flag is set or not.
#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE)
#define CR_DBP_BB
Definition: stm32f4xx_pwr.c:60
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
Enters STOP mode.
void PWR_PVDCmd(FunctionalState NewState)
Enables or disables the Power Voltage Detector(PVD).
#define CR_VOS_MASK
Definition: stm32f4xx_pwr.c:91
void PWR_FlashPowerDownCmd(FunctionalState NewState)
Enables or disables the Flash Power Down in STOP mode.
#define PWR
Definition: stm32f4xx.h:2074
void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
Configures the main internal regulator output voltage.
#define CSR_EWUP_BB
Definition: stm32f4xx_pwr.c:80
void PWR_DeInit(void)
Deinitializes the PWR peripheral registers to their default reset values.
void PWR_WakeUpPinCmd(FunctionalState NewState)
Enables or disables the WakeUp Pin functionality.
#define PWR_CR_PDDS
Definition: stm32f4xx.h:8353
#define CR_PVDE_BB
Definition: stm32f4xx_pwr.c:64
#define IS_PWR_REGULATOR(REGULATOR)
Definition: stm32f4xx_pwr.h:83
#define PWR_STOPEntry_WFI
Definition: stm32f4xx_pwr.h:93
#define IS_PWR_GET_FLAG(FLAG)


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19