stm32f4xx_can.c
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1 
84 /* Includes ------------------------------------------------------------------*/
85 #include "stm32f4xx_can.h"
86 #include "stm32f4xx_rcc.h"
87 
96 /* Private typedef -----------------------------------------------------------*/
97 /* Private define ------------------------------------------------------------*/
98 
99 /* CAN Master Control Register bits */
100 #define MCR_DBF ((uint32_t)0x00010000) /* software master reset */
101 
102 /* CAN Mailbox Transmit Request */
103 #define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */
104 
105 /* CAN Filter Master Register bits */
106 #define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */
107 
108 /* Time out for INAK bit */
109 #define INAK_TIMEOUT ((uint32_t)0x0000FFFF)
110 /* Time out for SLAK bit */
111 #define SLAK_TIMEOUT ((uint32_t)0x0000FFFF)
112 
113 /* Flags in TSR register */
114 #define CAN_FLAGS_TSR ((uint32_t)0x08000000)
115 /* Flags in RF1R register */
116 #define CAN_FLAGS_RF1R ((uint32_t)0x04000000)
117 /* Flags in RF0R register */
118 #define CAN_FLAGS_RF0R ((uint32_t)0x02000000)
119 /* Flags in MSR register */
120 #define CAN_FLAGS_MSR ((uint32_t)0x01000000)
121 /* Flags in ESR register */
122 #define CAN_FLAGS_ESR ((uint32_t)0x00F00000)
123 
124 /* Mailboxes definition */
125 #define CAN_TXMAILBOX_0 ((uint8_t)0x00)
126 #define CAN_TXMAILBOX_1 ((uint8_t)0x01)
127 #define CAN_TXMAILBOX_2 ((uint8_t)0x02)
128 
129 #define CAN_MODE_MASK ((uint32_t) 0x00000003)
130 
131 /* Private macro -------------------------------------------------------------*/
132 /* Private variables ---------------------------------------------------------*/
133 /* Private function prototypes -----------------------------------------------*/
134 /* Private functions ---------------------------------------------------------*/
135 static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
136 
168 {
169  /* Check the parameters */
171 
172  if (CANx == CAN1)
173  {
174  /* Enable CAN1 reset state */
176  /* Release CAN1 from reset state */
178  }
179  else
180  {
181  /* Enable CAN2 reset state */
183  /* Release CAN2 from reset state */
185  }
186 }
187 
197 uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
198 {
199  uint8_t InitStatus = CAN_InitStatus_Failed;
200  uint32_t wait_ack = 0x00000000;
201  /* Check the parameters */
203  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
204  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
205  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
206  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
207  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
208  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
209  assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
210  assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
211  assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
212  assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
213  assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
214 
215  /* Exit from sleep mode */
216  CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
217 
218  /* Request initialisation */
219  CANx->MCR |= CAN_MCR_INRQ ;
220 
221  /* Wait the acknowledge */
222  while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
223  {
224  wait_ack++;
225  }
226 
227  /* Check acknowledge */
228  if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
229  {
230  InitStatus = CAN_InitStatus_Failed;
231  }
232  else
233  {
234  /* Set the time triggered communication mode */
235  if (CAN_InitStruct->CAN_TTCM == ENABLE)
236  {
237  CANx->MCR |= CAN_MCR_TTCM;
238  }
239  else
240  {
241  CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;
242  }
243 
244  /* Set the automatic bus-off management */
245  if (CAN_InitStruct->CAN_ABOM == ENABLE)
246  {
247  CANx->MCR |= CAN_MCR_ABOM;
248  }
249  else
250  {
251  CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;
252  }
253 
254  /* Set the automatic wake-up mode */
255  if (CAN_InitStruct->CAN_AWUM == ENABLE)
256  {
257  CANx->MCR |= CAN_MCR_AWUM;
258  }
259  else
260  {
261  CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;
262  }
263 
264  /* Set the no automatic retransmission */
265  if (CAN_InitStruct->CAN_NART == ENABLE)
266  {
267  CANx->MCR |= CAN_MCR_NART;
268  }
269  else
270  {
271  CANx->MCR &= ~(uint32_t)CAN_MCR_NART;
272  }
273 
274  /* Set the receive FIFO locked mode */
275  if (CAN_InitStruct->CAN_RFLM == ENABLE)
276  {
277  CANx->MCR |= CAN_MCR_RFLM;
278  }
279  else
280  {
281  CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;
282  }
283 
284  /* Set the transmit FIFO priority */
285  if (CAN_InitStruct->CAN_TXFP == ENABLE)
286  {
287  CANx->MCR |= CAN_MCR_TXFP;
288  }
289  else
290  {
291  CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;
292  }
293 
294  /* Set the bit timing register */
295  CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
296  ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
297  ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
298  ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
299  ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
300 
301  /* Request leave initialisation */
302  CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
303 
304  /* Wait the acknowledge */
305  wait_ack = 0;
306 
307  while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
308  {
309  wait_ack++;
310  }
311 
312  /* ...and check acknowledged */
313  if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
314  {
315  InitStatus = CAN_InitStatus_Failed;
316  }
317  else
318  {
319  InitStatus = CAN_InitStatus_Success ;
320  }
321  }
322 
323  /* At this step, return the status of initialization */
324  return InitStatus;
325 }
326 
334 void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
335 {
336  uint32_t filter_number_bit_pos = 0;
337  /* Check the parameters */
338  assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
339  assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
340  assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
342  assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
343 
344  filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
345 
346  /* Initialisation mode for the filter */
347  CAN1->FMR |= FMR_FINIT;
348 
349  /* Filter Deactivation */
350  CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;
351 
352  /* Filter Scale */
353  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
354  {
355  /* 16-bit scale for the filter */
356  CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;
357 
358  /* First 16-bit identifier and First 16-bit mask */
359  /* Or First 16-bit identifier and Second 16-bit identifier */
360  CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
361  ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
362  (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
363 
364  /* Second 16-bit identifier and Second 16-bit mask */
365  /* Or Third 16-bit identifier and Fourth 16-bit identifier */
366  CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
367  ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
368  (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
369  }
370 
371  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
372  {
373  /* 32-bit scale for the filter */
374  CAN1->FS1R |= filter_number_bit_pos;
375  /* 32-bit identifier or First 32-bit identifier */
376  CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
377  ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
378  (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
379  /* 32-bit mask or Second 32-bit identifier */
380  CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
381  ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
382  (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
383  }
384 
385  /* Filter Mode */
386  if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
387  {
388  /*Id/Mask mode for the filter*/
389  CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;
390  }
391  else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
392  {
393  /*Identifier list mode for the filter*/
394  CAN1->FM1R |= (uint32_t)filter_number_bit_pos;
395  }
396 
397  /* Filter FIFO assignment */
398  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
399  {
400  /* FIFO 0 assignation for the filter */
401  CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;
402  }
403 
404  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
405  {
406  /* FIFO 1 assignation for the filter */
407  CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;
408  }
409 
410  /* Filter activation */
411  if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
412  {
413  CAN1->FA1R |= filter_number_bit_pos;
414  }
415 
416  /* Leave the initialisation mode for the filter */
417  CAN1->FMR &= ~FMR_FINIT;
418 }
419 
425 void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
426 {
427  /* Reset CAN init structure parameters values */
428 
429  /* Initialize the time triggered communication mode */
430  CAN_InitStruct->CAN_TTCM = DISABLE;
431 
432  /* Initialize the automatic bus-off management */
433  CAN_InitStruct->CAN_ABOM = DISABLE;
434 
435  /* Initialize the automatic wake-up mode */
436  CAN_InitStruct->CAN_AWUM = DISABLE;
437 
438  /* Initialize the no automatic retransmission */
439  CAN_InitStruct->CAN_NART = DISABLE;
440 
441  /* Initialize the receive FIFO locked mode */
442  CAN_InitStruct->CAN_RFLM = DISABLE;
443 
444  /* Initialize the transmit FIFO priority */
445  CAN_InitStruct->CAN_TXFP = DISABLE;
446 
447  /* Initialize the CAN_Mode member */
448  CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
449 
450  /* Initialize the CAN_SJW member */
451  CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
452 
453  /* Initialize the CAN_BS1 member */
454  CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
455 
456  /* Initialize the CAN_BS2 member */
457  CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
458 
459  /* Initialize the CAN_Prescaler member */
460  CAN_InitStruct->CAN_Prescaler = 1;
461 }
462 
468 void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
469 {
470  /* Check the parameters */
471  assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
472 
473  /* Enter Initialisation mode for the filter */
474  CAN1->FMR |= FMR_FINIT;
475 
476  /* Select the start slave bank */
477  CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;
478  CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;
479 
480  /* Leave Initialisation mode for the filter */
481  CAN1->FMR &= ~FMR_FINIT;
482 }
483 
494 {
495  /* Check the parameters */
498 
499  if (NewState != DISABLE)
500  {
501  /* Enable Debug Freeze */
502  CANx->MCR |= MCR_DBF;
503  }
504  else
505  {
506  /* Disable Debug Freeze */
507  CANx->MCR &= ~MCR_DBF;
508  }
509 }
510 
511 
524 {
525  /* Check the parameters */
528  if (NewState != DISABLE)
529  {
530  /* Enable the TTCM mode */
531  CANx->MCR |= CAN_MCR_TTCM;
532 
533  /* Set TGT bits */
534  CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT);
535  CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT);
536  CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT);
537  }
538  else
539  {
540  /* Disable the TTCM mode */
541  CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM);
542 
543  /* Reset TGT bits */
544  CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT);
545  CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT);
546  CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT);
547  }
548 }
577 uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
578 {
579  uint8_t transmit_mailbox = 0;
580  /* Check the parameters */
582  assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
583  assert_param(IS_CAN_RTR(TxMessage->RTR));
584  assert_param(IS_CAN_DLC(TxMessage->DLC));
585 
586  /* Select one empty transmit mailbox */
587  if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
588  {
589  transmit_mailbox = 0;
590  }
591  else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
592  {
593  transmit_mailbox = 1;
594  }
595  else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
596  {
597  transmit_mailbox = 2;
598  }
599  else
600  {
601  transmit_mailbox = CAN_TxStatus_NoMailBox;
602  }
603 
604  if (transmit_mailbox != CAN_TxStatus_NoMailBox)
605  {
606  /* Set up the Id */
607  CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
608  if (TxMessage->IDE == CAN_Id_Standard)
609  {
610  assert_param(IS_CAN_STDID(TxMessage->StdId));
611  CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \
612  TxMessage->RTR);
613  }
614  else
615  {
616  assert_param(IS_CAN_EXTID(TxMessage->ExtId));
617  CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \
618  TxMessage->IDE | \
619  TxMessage->RTR);
620  }
621 
622  /* Set up the DLC */
623  TxMessage->DLC &= (uint8_t)0x0000000F;
624  CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
625  CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;
626 
627  /* Set up the data field */
628  CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) |
629  ((uint32_t)TxMessage->Data[2] << 16) |
630  ((uint32_t)TxMessage->Data[1] << 8) |
631  ((uint32_t)TxMessage->Data[0]));
632  CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) |
633  ((uint32_t)TxMessage->Data[6] << 16) |
634  ((uint32_t)TxMessage->Data[5] << 8) |
635  ((uint32_t)TxMessage->Data[4]));
636  /* Request transmission */
637  CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;
638  }
639  return transmit_mailbox;
640 }
641 
649 uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
650 {
651  uint32_t state = 0;
652 
653  /* Check the parameters */
655  assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
656 
657  switch (TransmitMailbox)
658  {
659  case (CAN_TXMAILBOX_0):
660  state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0);
661  break;
662  case (CAN_TXMAILBOX_1):
663  state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1);
664  break;
665  case (CAN_TXMAILBOX_2):
666  state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2);
667  break;
668  default:
669  state = CAN_TxStatus_Failed;
670  break;
671  }
672  switch (state)
673  {
674  /* transmit pending */
675  case (0x0): state = CAN_TxStatus_Pending;
676  break;
677  /* transmit failed */
679  break;
681  break;
683  break;
684  /* transmit succeeded */
686  break;
688  break;
690  break;
691  default: state = CAN_TxStatus_Failed;
692  break;
693  }
694  return (uint8_t) state;
695 }
696 
703 void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
704 {
705  /* Check the parameters */
708  /* abort transmission */
709  switch (Mailbox)
710  {
711  case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0;
712  break;
713  case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1;
714  break;
715  case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2;
716  break;
717  default:
718  break;
719  }
720 }
750 void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
751 {
752  /* Check the parameters */
754  assert_param(IS_CAN_FIFO(FIFONumber));
755  /* Get the Id */
756  RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
757  if (RxMessage->IDE == CAN_Id_Standard)
758  {
759  RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
760  }
761  else
762  {
763  RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
764  }
765 
766  RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
767  /* Get the DLC */
768  RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
769  /* Get the FMI */
770  RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
771  /* Get the data field */
772  RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
773  RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
774  RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
775  RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
776  RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
777  RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
778  RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
779  RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
780  /* Release the FIFO */
781  /* Release FIFO0 */
782  if (FIFONumber == CAN_FIFO0)
783  {
784  CANx->RF0R |= CAN_RF0R_RFOM0;
785  }
786  /* Release FIFO1 */
787  else /* FIFONumber == CAN_FIFO1 */
788  {
789  CANx->RF1R |= CAN_RF1R_RFOM1;
790  }
791 }
792 
799 void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
800 {
801  /* Check the parameters */
803  assert_param(IS_CAN_FIFO(FIFONumber));
804  /* Release FIFO0 */
805  if (FIFONumber == CAN_FIFO0)
806  {
807  CANx->RF0R |= CAN_RF0R_RFOM0;
808  }
809  /* Release FIFO1 */
810  else /* FIFONumber == CAN_FIFO1 */
811  {
812  CANx->RF1R |= CAN_RF1R_RFOM1;
813  }
814 }
815 
822 uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
823 {
824  uint8_t message_pending=0;
825  /* Check the parameters */
827  assert_param(IS_CAN_FIFO(FIFONumber));
828  if (FIFONumber == CAN_FIFO0)
829  {
830  message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
831  }
832  else if (FIFONumber == CAN_FIFO1)
833  {
834  message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
835  }
836  else
837  {
838  message_pending = 0;
839  }
840  return message_pending;
841 }
872 uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)
873 {
874  uint8_t status = CAN_ModeStatus_Failed;
875 
876  /* Timeout for INAK or also for SLAK bits*/
877  uint32_t timeout = INAK_TIMEOUT;
878 
879  /* Check the parameters */
881  assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
882 
883  if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
884  {
885  /* Request initialisation */
886  CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ);
887 
888  /* Wait the acknowledge */
889  while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))
890  {
891  timeout--;
892  }
893  if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
894  {
895  status = CAN_ModeStatus_Failed;
896  }
897  else
898  {
899  status = CAN_ModeStatus_Success;
900  }
901  }
902  else if (CAN_OperatingMode == CAN_OperatingMode_Normal)
903  {
904  /* Request leave initialisation and sleep mode and enter Normal mode */
905  CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));
906 
907  /* Wait the acknowledge */
908  while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))
909  {
910  timeout--;
911  }
912  if ((CANx->MSR & CAN_MODE_MASK) != 0)
913  {
914  status = CAN_ModeStatus_Failed;
915  }
916  else
917  {
918  status = CAN_ModeStatus_Success;
919  }
920  }
921  else if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
922  {
923  /* Request Sleep mode */
924  CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
925 
926  /* Wait the acknowledge */
927  while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))
928  {
929  timeout--;
930  }
931  if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
932  {
933  status = CAN_ModeStatus_Failed;
934  }
935  else
936  {
937  status = CAN_ModeStatus_Success;
938  }
939  }
940  else
941  {
942  status = CAN_ModeStatus_Failed;
943  }
944 
945  return (uint8_t) status;
946 }
947 
953 uint8_t CAN_Sleep(CAN_TypeDef* CANx)
954 {
955  uint8_t sleepstatus = CAN_Sleep_Failed;
956 
957  /* Check the parameters */
959 
960  /* Request Sleep mode */
961  CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
962 
963  /* Sleep mode status */
964  if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
965  {
966  /* Sleep mode not entered */
967  sleepstatus = CAN_Sleep_Ok;
968  }
969  /* return sleep mode status */
970  return (uint8_t)sleepstatus;
971 }
972 
978 uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
979 {
980  uint32_t wait_slak = SLAK_TIMEOUT;
981  uint8_t wakeupstatus = CAN_WakeUp_Failed;
982 
983  /* Check the parameters */
985 
986  /* Wake up request */
987  CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
988 
989  /* Sleep mode status */
990  while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
991  {
992  wait_slak--;
993  }
994  if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
995  {
996  /* wake up done : Sleep mode exited */
997  wakeupstatus = CAN_WakeUp_Ok;
998  }
999  /* return wakeup status */
1000  return (uint8_t)wakeupstatus;
1001 }
1041 {
1042  uint8_t errorcode=0;
1043 
1044  /* Check the parameters */
1046 
1047  /* Get the error code*/
1048  errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC);
1049 
1050  /* Return the error code*/
1051  return errorcode;
1052 }
1053 
1066 {
1067  uint8_t counter=0;
1068 
1069  /* Check the parameters */
1071 
1072  /* Get the Receive Error Counter*/
1073  counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24);
1074 
1075  /* Return the Receive Error Counter*/
1076  return counter;
1077 }
1078 
1079 
1086 {
1087  uint8_t counter=0;
1088 
1089  /* Check the parameters */
1091 
1092  /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
1093  counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16);
1094 
1095  /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
1096  return counter;
1097 }
1290 void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
1291 {
1292  /* Check the parameters */
1294  assert_param(IS_CAN_IT(CAN_IT));
1295  assert_param(IS_FUNCTIONAL_STATE(NewState));
1296 
1297  if (NewState != DISABLE)
1298  {
1299  /* Enable the selected CANx interrupt */
1300  CANx->IER |= CAN_IT;
1301  }
1302  else
1303  {
1304  /* Disable the selected CANx interrupt */
1305  CANx->IER &= ~CAN_IT;
1306  }
1307 }
1330 FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
1331 {
1332  FlagStatus bitstatus = RESET;
1333 
1334  /* Check the parameters */
1336  assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
1337 
1338 
1339  if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)
1340  {
1341  /* Check the status of the specified CAN flag */
1342  if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
1343  {
1344  /* CAN_FLAG is set */
1345  bitstatus = SET;
1346  }
1347  else
1348  {
1349  /* CAN_FLAG is reset */
1350  bitstatus = RESET;
1351  }
1352  }
1353  else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)
1354  {
1355  /* Check the status of the specified CAN flag */
1356  if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
1357  {
1358  /* CAN_FLAG is set */
1359  bitstatus = SET;
1360  }
1361  else
1362  {
1363  /* CAN_FLAG is reset */
1364  bitstatus = RESET;
1365  }
1366  }
1367  else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)
1368  {
1369  /* Check the status of the specified CAN flag */
1370  if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
1371  {
1372  /* CAN_FLAG is set */
1373  bitstatus = SET;
1374  }
1375  else
1376  {
1377  /* CAN_FLAG is reset */
1378  bitstatus = RESET;
1379  }
1380  }
1381  else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)
1382  {
1383  /* Check the status of the specified CAN flag */
1384  if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
1385  {
1386  /* CAN_FLAG is set */
1387  bitstatus = SET;
1388  }
1389  else
1390  {
1391  /* CAN_FLAG is reset */
1392  bitstatus = RESET;
1393  }
1394  }
1395  else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */
1396  {
1397  /* Check the status of the specified CAN flag */
1398  if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
1399  {
1400  /* CAN_FLAG is set */
1401  bitstatus = SET;
1402  }
1403  else
1404  {
1405  /* CAN_FLAG is reset */
1406  bitstatus = RESET;
1407  }
1408  }
1409  /* Return the CAN_FLAG status */
1410  return bitstatus;
1411 }
1412 
1430 void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
1431 {
1432  uint32_t flagtmp=0;
1433  /* Check the parameters */
1435  assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
1436 
1437  if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */
1438  {
1439  /* Clear the selected CAN flags */
1440  CANx->ESR = (uint32_t)RESET;
1441  }
1442  else /* MSR or TSR or RF0R or RF1R */
1443  {
1444  flagtmp = CAN_FLAG & 0x000FFFFF;
1445 
1446  if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)
1447  {
1448  /* Receive Flags */
1449  CANx->RF0R = (uint32_t)(flagtmp);
1450  }
1451  else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)
1452  {
1453  /* Receive Flags */
1454  CANx->RF1R = (uint32_t)(flagtmp);
1455  }
1456  else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)
1457  {
1458  /* Transmit Flags */
1459  CANx->TSR = (uint32_t)(flagtmp);
1460  }
1461  else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */
1462  {
1463  /* Operating mode Flags */
1464  CANx->MSR = (uint32_t)(flagtmp);
1465  }
1466  }
1467 }
1468 
1490 ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
1491 {
1492  ITStatus itstatus = RESET;
1493  /* Check the parameters */
1495  assert_param(IS_CAN_IT(CAN_IT));
1496 
1497  /* check the interrupt enable bit */
1498  if((CANx->IER & CAN_IT) != RESET)
1499  {
1500  /* in case the Interrupt is enabled, .... */
1501  switch (CAN_IT)
1502  {
1503  case CAN_IT_TME:
1504  /* Check CAN_TSR_RQCPx bits */
1506  break;
1507  case CAN_IT_FMP0:
1508  /* Check CAN_RF0R_FMP0 bit */
1509  itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);
1510  break;
1511  case CAN_IT_FF0:
1512  /* Check CAN_RF0R_FULL0 bit */
1513  itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);
1514  break;
1515  case CAN_IT_FOV0:
1516  /* Check CAN_RF0R_FOVR0 bit */
1517  itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);
1518  break;
1519  case CAN_IT_FMP1:
1520  /* Check CAN_RF1R_FMP1 bit */
1521  itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);
1522  break;
1523  case CAN_IT_FF1:
1524  /* Check CAN_RF1R_FULL1 bit */
1525  itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);
1526  break;
1527  case CAN_IT_FOV1:
1528  /* Check CAN_RF1R_FOVR1 bit */
1529  itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);
1530  break;
1531  case CAN_IT_WKU:
1532  /* Check CAN_MSR_WKUI bit */
1533  itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);
1534  break;
1535  case CAN_IT_SLK:
1536  /* Check CAN_MSR_SLAKI bit */
1537  itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);
1538  break;
1539  case CAN_IT_EWG:
1540  /* Check CAN_ESR_EWGF bit */
1541  itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);
1542  break;
1543  case CAN_IT_EPV:
1544  /* Check CAN_ESR_EPVF bit */
1545  itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);
1546  break;
1547  case CAN_IT_BOF:
1548  /* Check CAN_ESR_BOFF bit */
1549  itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);
1550  break;
1551  case CAN_IT_LEC:
1552  /* Check CAN_ESR_LEC bit */
1553  itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);
1554  break;
1555  case CAN_IT_ERR:
1556  /* Check CAN_MSR_ERRI bit */
1557  itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI);
1558  break;
1559  default:
1560  /* in case of error, return RESET */
1561  itstatus = RESET;
1562  break;
1563  }
1564  }
1565  else
1566  {
1567  /* in case the Interrupt is not enabled, return RESET */
1568  itstatus = RESET;
1569  }
1570 
1571  /* Return the CAN_IT status */
1572  return itstatus;
1573 }
1574 
1594 void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
1595 {
1596  /* Check the parameters */
1598  assert_param(IS_CAN_CLEAR_IT(CAN_IT));
1599 
1600  switch (CAN_IT)
1601  {
1602  case CAN_IT_TME:
1603  /* Clear CAN_TSR_RQCPx (rc_w1)*/
1605  break;
1606  case CAN_IT_FF0:
1607  /* Clear CAN_RF0R_FULL0 (rc_w1)*/
1608  CANx->RF0R = CAN_RF0R_FULL0;
1609  break;
1610  case CAN_IT_FOV0:
1611  /* Clear CAN_RF0R_FOVR0 (rc_w1)*/
1612  CANx->RF0R = CAN_RF0R_FOVR0;
1613  break;
1614  case CAN_IT_FF1:
1615  /* Clear CAN_RF1R_FULL1 (rc_w1)*/
1616  CANx->RF1R = CAN_RF1R_FULL1;
1617  break;
1618  case CAN_IT_FOV1:
1619  /* Clear CAN_RF1R_FOVR1 (rc_w1)*/
1620  CANx->RF1R = CAN_RF1R_FOVR1;
1621  break;
1622  case CAN_IT_WKU:
1623  /* Clear CAN_MSR_WKUI (rc_w1)*/
1624  CANx->MSR = CAN_MSR_WKUI;
1625  break;
1626  case CAN_IT_SLK:
1627  /* Clear CAN_MSR_SLAKI (rc_w1)*/
1628  CANx->MSR = CAN_MSR_SLAKI;
1629  break;
1630  case CAN_IT_EWG:
1631  /* Clear CAN_MSR_ERRI (rc_w1) */
1632  CANx->MSR = CAN_MSR_ERRI;
1633  /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
1634  break;
1635  case CAN_IT_EPV:
1636  /* Clear CAN_MSR_ERRI (rc_w1) */
1637  CANx->MSR = CAN_MSR_ERRI;
1638  /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
1639  break;
1640  case CAN_IT_BOF:
1641  /* Clear CAN_MSR_ERRI (rc_w1) */
1642  CANx->MSR = CAN_MSR_ERRI;
1643  /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
1644  break;
1645  case CAN_IT_LEC:
1646  /* Clear LEC bits */
1647  CANx->ESR = RESET;
1648  /* Clear CAN_MSR_ERRI (rc_w1) */
1649  CANx->MSR = CAN_MSR_ERRI;
1650  break;
1651  case CAN_IT_ERR:
1652  /*Clear LEC bits */
1653  CANx->ESR = RESET;
1654  /* Clear CAN_MSR_ERRI (rc_w1) */
1655  CANx->MSR = CAN_MSR_ERRI;
1656  /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/
1657  break;
1658  default:
1659  break;
1660  }
1661 }
1672 static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
1673 {
1674  ITStatus pendingbitstatus = RESET;
1675 
1676  if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
1677  {
1678  /* CAN_IT is set */
1679  pendingbitstatus = SET;
1680  }
1681  else
1682  {
1683  /* CAN_IT is reset */
1684  pendingbitstatus = RESET;
1685  }
1686  return pendingbitstatus;
1687 }
1688 
1701 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
#define CAN_RF1R_FULL1
Definition: stm32f4xx.h:2610
#define CAN_TSR_RQCP2
Definition: stm32f4xx.h:2585
#define IS_CAN_BANKNUMBER(BANKNUMBER)
#define CAN_TXMAILBOX_0
FlagStatus
Definition: stm32f4xx.h:706
#define IS_CAN_FILTER_FIFO(FIFO)
#define CAN_TSR_RQCP0
Definition: stm32f4xx.h:2575
#define MCR_DBF
#define CAN_MSR_WKUI
Definition: stm32f4xx.h:2567
uint8_t IDE
#define CAN_TSR_TXOK1
Definition: stm32f4xx.h:2581
#define CAN_RF1R_FOVR1
Definition: stm32f4xx.h:2611
#define CAN_BS2_3tq
#define CAN_InitStatus_Failed
#define CAN_IT_FOV1
#define CAN_MCR_SLEEP
Definition: stm32f4xx.h:2554
CAN init structure definition.
Definition: stm32f4xx_can.h:56
uint8_t RTR
FunctionalState
Definition: stm32f4xx.h:708
#define CAN_RF0R_FOVR0
Definition: stm32f4xx.h:2605
uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef *CANx)
Returns the CANx Receive Error Counter (REC).
#define CAN_IT_FMP1
uint8_t CAN_Init(CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct)
Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.
#define IS_CAN_OPERATING_MODE(MODE)
#define CAN_IT_EPV
#define CAN_IT_BOF
FunctionalState CAN_FilterActivation
uint8_t CAN_OperatingModeRequest(CAN_TypeDef *CANx, uint8_t CAN_OperatingMode)
Selects the CAN Operation mode.
uint8_t CAN_Transmit(CAN_TypeDef *CANx, CanTxMsg *TxMessage)
Initiates and transmits a CAN frame message.
__IO uint32_t RDTR
Definition: stm32f4xx.h:777
#define CAN_FLAGS_MSR
#define CAN_Sleep_Failed
#define CAN_FIFO0
#define CAN_RF0R_FULL0
Definition: stm32f4xx.h:2604
FunctionalState CAN_TTCM
Definition: stm32f4xx_can.h:76
__IO uint32_t RDLR
Definition: stm32f4xx.h:778
FunctionalState CAN_AWUM
Definition: stm32f4xx_can.h:82
uint8_t FMI
void CAN_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage)
Receives a correct CAN frame.
#define CAN_IT_FMP0
#define CAN_Filter_FIFO0
uint8_t Data[8]
void CAN_ClearITPendingBit(CAN_TypeDef *CANx, uint32_t CAN_IT)
Clears the CANx&#39;s interrupt pending bits.
#define CAN_RF0R_FMP0
Definition: stm32f4xx.h:2603
void CAN_DeInit(CAN_TypeDef *CANx)
Deinitializes the CAN peripheral registers to their default reset values.
#define CAN_WakeUp_Ok
#define CAN_FLAGS_RF1R
FunctionalState CAN_TXFP
Definition: stm32f4xx_can.h:91
#define CAN_RF1R_RFOM1
Definition: stm32f4xx.h:2612
#define CAN_ESR_BOFF
Definition: stm32f4xx.h:2633
void assert_param(int val)
uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef *CANx)
Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
FunctionalState CAN_NART
Definition: stm32f4xx_can.h:85
#define IS_CAN_BS2(BS2)
#define CAN_OperatingMode_Normal
uint8_t CAN_GetLastErrorCode(CAN_TypeDef *CANx)
Returns the CANx&#39;s last error code (LEC).
#define CAN_MCR_ABOM
Definition: stm32f4xx.h:2559
__IO uint32_t TDLR
Definition: stm32f4xx.h:766
void CAN_ITConfig(CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState)
Enables or disables the specified CANx interrupts.
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
#define IS_CAN_IT(IT)
#define INAK_TIMEOUT
#define CAN_TXMAILBOX_2
static volatile uint8_t * status
Definition: drv_i2c.c:102
#define IS_CAN_DLC(DLC)
ITStatus CAN_GetITStatus(CAN_TypeDef *CANx, uint32_t CAN_IT)
Checks whether the specified CANx interrupt has occurred or not.
static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
Checks whether the CAN interrupt has occurred or not.
#define IS_CAN_ALL_PERIPH(PERIPH)
Definition: stm32f4xx_can.h:50
#define CAN_IT_FF1
#define IS_CAN_GET_FLAG(FLAG)
uint8_t CAN_WakeUp(CAN_TypeDef *CANx)
Wakes up the CAN peripheral from sleep mode .
#define CAN_ESR_EWGF
Definition: stm32f4xx.h:2631
Definition: stm32f4xx.h:706
This file contains all the functions prototypes for the CAN firmware library.
#define SLAK_TIMEOUT
__IO uint32_t IER
Definition: stm32f4xx.h:803
void CAN_FilterInit(CAN_FilterInitTypeDef *CAN_FilterInitStruct)
Configures the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct...
uint8_t DLC
#define CAN_FIFO1
__IO uint32_t TDHR
Definition: stm32f4xx.h:767
enum FlagStatus ITStatus
void CAN_FIFORelease(CAN_TypeDef *CANx, uint8_t FIFONumber)
Releases the specified receive FIFO.
uint8_t CAN_TransmitStatus(CAN_TypeDef *CANx, uint8_t TransmitMailbox)
Checks the transmission status of a CAN Frame.
#define CAN_TSR_TME1
Definition: stm32f4xx.h:2594
#define CAN_MSR_INAK
Definition: stm32f4xx.h:2564
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
#define CAN_TDT0R_TGT
Definition: stm32f4xx.h:2661
#define CAN_BS1_4tq
__IO uint32_t RF0R
Definition: stm32f4xx.h:801
#define IS_CAN_MODE(MODE)
#define IS_CAN_CLEAR_FLAG(FLAG)
#define CAN_Sleep_Ok
#define CAN_IT_FOV0
#define IS_CAN_IDTYPE(IDTYPE)
#define CAN_IT_SLK
#define CAN_Filter_FIFO1
#define CAN_MSR_SLAK
Definition: stm32f4xx.h:2565
#define CAN_MCR_NART
Definition: stm32f4xx.h:2557
#define CAN_OperatingMode_Sleep
#define CAN_ESR_EPVF
Definition: stm32f4xx.h:2632
#define CAN_TSR_ABRQ0
Definition: stm32f4xx.h:2579
void CAN_ClearFlag(CAN_TypeDef *CANx, uint32_t CAN_FLAG)
Clears the CAN&#39;s pending flags.
uint8_t CAN_Sleep(CAN_TypeDef *CANx)
Enters the Sleep (low power) mode.
#define CAN1
Definition: stm32f4xx.h:2069
#define IS_CAN_STDID(STDID)
FlagStatus CAN_GetFlagStatus(CAN_TypeDef *CANx, uint32_t CAN_FLAG)
Checks whether the specified CAN flag is set or not.
#define CAN_TSR_RQCP1
Definition: stm32f4xx.h:2580
#define CAN_IT_FF0
#define CAN_TxStatus_NoMailBox
#define IS_CAN_CLEAR_IT(IT)
#define CAN_ESR_TEC
Definition: stm32f4xx.h:2640
#define IS_CAN_FILTER_NUMBER(NUMBER)
uint8_t DLC
#define CAN_IT_EWG
#define CAN_TSR_ABRQ1
Definition: stm32f4xx.h:2584
void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct)
Fills each CAN_InitStruct member with its default value.
#define TMIDxR_TXRQ
FunctionalState CAN_RFLM
Definition: stm32f4xx_can.h:88
#define IS_CAN_EXTID(EXTID)
#define CAN_TxStatus_Pending
__IO uint32_t RDHR
Definition: stm32f4xx.h:779
__IO uint32_t TIR
Definition: stm32f4xx.h:764
#define FMR_FINIT
#define CAN_IT_ERR
#define CAN_MCR_AWUM
Definition: stm32f4xx.h:2558
#define IS_CAN_PRESCALER(PRESCALER)
#define CAN_SJW_1tq
#define CAN_MSR_SLAKI
Definition: stm32f4xx.h:2568
#define CAN_MCR_TXFP
Definition: stm32f4xx.h:2555
#define CAN_MCR_TTCM
Definition: stm32f4xx.h:2560
__IO uint32_t RIR
Definition: stm32f4xx.h:776
#define CAN_TDT2R_TGT
Definition: stm32f4xx.h:2709
__IO uint32_t TSR
Definition: stm32f4xx.h:800
#define IS_CAN_FILTER_SCALE(SCALE)
void CAN_TTComModeCmd(CAN_TypeDef *CANx, FunctionalState NewState)
Enables or disables the CAN Time TriggerOperation communication mode.
__IO uint32_t BTR
Definition: stm32f4xx.h:805
#define CAN_MCR_RFLM
Definition: stm32f4xx.h:2556
__IO uint32_t MCR
Definition: stm32f4xx.h:798
uint8_t RTR
#define CAN_IT_WKU
#define CAN_TxStatus_Failed
uint16_t CAN_FilterFIFOAssignment
#define CAN_FilterScale_32bit
uint32_t ExtId
#define CAN_ESR_LEC
Definition: stm32f4xx.h:2635
#define CAN_TSR_TME2
Definition: stm32f4xx.h:2595
#define IS_CAN_FILTER_MODE(MODE)
#define CAN_RF0R_RFOM0
Definition: stm32f4xx.h:2606
#define CAN_TSR_TME0
Definition: stm32f4xx.h:2593
#define CAN_TDT1R_TGT
Definition: stm32f4xx.h:2685
#define IS_CAN_SJW(SJW)
CAN filter init structure definition.
Definition: stm32f4xx_can.h:98
#define CAN_MODE_MASK
Controller Area Network.
Definition: stm32f4xx.h:796
void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
Select the start bank filter for slave CAN.
uint16_t CAN_Prescaler
Definition: stm32f4xx_can.h:58
#define CAN_FLAGS_ESR
CAN Tx message structure definition.
#define CAN_MCR_INRQ
Definition: stm32f4xx.h:2553
uint32_t StdId
#define CAN_FLAGS_RF0R
uint8_t IDE
#define CAN_ModeStatus_Failed
__IO uint32_t MSR
Definition: stm32f4xx.h:799
#define CAN_TXMAILBOX_1
#define CAN_WakeUp_Failed
uint32_t StdId
__IO uint32_t TDTR
Definition: stm32f4xx.h:765
#define CAN_Mode_Normal
CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]
Definition: stm32f4xx.h:808
#define CAN_FilterMode_IdMask
#define IS_CAN_FIFO(FIFO)
#define CAN_TSR_TXOK0
Definition: stm32f4xx.h:2576
#define CAN_TSR_ABRQ2
Definition: stm32f4xx.h:2589
#define CAN_Id_Standard
#define CAN_TSR_TXOK2
Definition: stm32f4xx.h:2586
#define IS_CAN_BS1(BS1)
uint8_t CAN_MessagePending(CAN_TypeDef *CANx, uint8_t FIFONumber)
Returns the number of pending received messages.
#define CAN_OperatingMode_Initialization
__IO uint32_t RF1R
Definition: stm32f4xx.h:802
FunctionalState CAN_ABOM
Definition: stm32f4xx_can.h:79
#define CAN_ModeStatus_Success
#define CAN_FLAG_LEC
#define CAN_ESR_REC
Definition: stm32f4xx.h:2641
#define CAN_InitStatus_Success
#define CAN_MSR_ERRI
Definition: stm32f4xx.h:2566
#define IS_CAN_RTR(RTR)
CAN_TxMailBox_TypeDef sTxMailBox[3]
Definition: stm32f4xx.h:807
#define CAN_TxStatus_Ok
__IO uint32_t ESR
Definition: stm32f4xx.h:804
#define CAN_FLAGS_TSR
uint32_t ExtId
void CAN_CancelTransmit(CAN_TypeDef *CANx, uint8_t Mailbox)
Cancels a transmit request.
void CAN_DBGFreeze(CAN_TypeDef *CANx, FunctionalState NewState)
Enables or disables the DBG Freeze for CAN.
#define CAN_IT_TME
#define CAN_RF1R_FMP1
Definition: stm32f4xx.h:2609
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX)
uint8_t Data[8]
CAN Rx message structure definition.
#define CAN_IT_LEC
#define CAN_FilterScale_16bit


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19