stm32f30x_tim.c
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1 
119 /* Includes ------------------------------------------------------------------*/
120 #include "stm32f30x_tim.h"
121 #include "stm32f30x_rcc.h"
122 
132 /* Private typedef -----------------------------------------------------------*/
133 /* Private define ------------------------------------------------------------*/
134 
135 /* ---------------------- TIM registers bit mask ------------------------ */
136 #define SMCR_ETR_MASK ((uint16_t)0x00FF)
137 #define CCMR_OFFSET ((uint16_t)0x0018)
138 #define CCER_CCE_SET ((uint16_t)0x0001)
139 #define CCER_CCNE_SET ((uint16_t)0x0004)
140 #define CCMR_OC13M_MASK ((uint32_t)0xFFFEFF8F)
141 #define CCMR_OC24M_MASK ((uint32_t)0xFEFF8FFF)
142 
143 /* Private macro -------------------------------------------------------------*/
144 /* Private variables ---------------------------------------------------------*/
145 /* Private function prototypes -----------------------------------------------*/
146 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
147  uint16_t TIM_ICFilter);
148 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
149  uint16_t TIM_ICFilter);
150 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
151  uint16_t TIM_ICFilter);
152 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
153  uint16_t TIM_ICFilter);
154 
155 /* Private functions ---------------------------------------------------------*/
156 
200 {
201  /* Check the parameters */
203 
204  if (TIMx == TIM1)
205  {
208  }
209  else if (TIMx == TIM2)
210  {
213  }
214  else if (TIMx == TIM3)
215  {
218  }
219  else if (TIMx == TIM4)
220  {
223  }
224  else if (TIMx == TIM6)
225  {
228  }
229  else if (TIMx == TIM7)
230  {
233  }
234  else if (TIMx == TIM8)
235  {
238  }
239  else if (TIMx == TIM15)
240  {
243  }
244  else if (TIMx == TIM16)
245  {
248  }
249  else
250  {
251  if (TIMx == TIM17)
252  {
255  }
256  }
257 }
258 
267 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
268 {
269  uint16_t tmpcr1 = 0;
270 
271  /* Check the parameters */
273  assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
274  assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
275 
276  tmpcr1 = TIMx->CR1;
277 
278  if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) ||
279  (TIMx == TIM3)|| (TIMx == TIM4))
280  {
281  /* Select the Counter Mode */
282  tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS));
283  tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
284  }
285 
286  if((TIMx != TIM6) && (TIMx != TIM7))
287  {
288  /* Set the clock division */
289  tmpcr1 &= (uint16_t)(~TIM_CR1_CKD);
290  tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
291  }
292 
293  TIMx->CR1 = tmpcr1;
294 
295  /* Set the Autoreload value */
296  TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
297 
298  /* Set the Prescaler value */
299  TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
300 
301  if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15) ||
302  (TIMx == TIM16) || (TIMx == TIM17))
303  {
304  /* Set the Repetition Counter value */
305  TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
306  }
307 
308  /* Generate an update event to reload the Prescaler
309  and the repetition counter(only for TIM1 and TIM8) value immediatly */
311 }
312 
319 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
320 {
321  /* Set the default configuration */
322  TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
323  TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
324  TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
325  TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
326  TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
327 }
328 
339 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
340 {
341  /* Check the parameters */
343  assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
344  /* Set the Prescaler value */
345  TIMx->PSC = Prescaler;
346  /* Set or reset the UG Bit */
347  TIMx->EGR = TIM_PSCReloadMode;
348 }
349 
362 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
363 {
364  uint16_t tmpcr1 = 0;
365 
366  /* Check the parameters */
368  assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
369 
370  tmpcr1 = TIMx->CR1;
371 
372  /* Reset the CMS and DIR Bits */
373  tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS);
374 
375  /* Set the Counter Mode */
376  tmpcr1 |= TIM_CounterMode;
377 
378  /* Write to TIMx CR1 register */
379  TIMx->CR1 = tmpcr1;
380 }
381 
388 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
389 {
390  /* Check the parameters */
392 
393  /* Set the Counter Register value */
394  TIMx->CNT = Counter;
395 }
396 
403 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
404 {
405  /* Check the parameters */
407 
408  /* Set the Autoreload Register value */
409  TIMx->ARR = Autoreload;
410 }
411 
418 {
419  /* Check the parameters */
421 
422  /* Get the Counter Register value */
423  return TIMx->CNT;
424 }
425 
432 {
433  /* Check the parameters */
435 
436  /* Get the Prescaler Register value */
437  return TIMx->PSC;
438 }
439 
448 {
449  /* Check the parameters */
452 
453  if (NewState != DISABLE)
454  {
455  /* Set the Update Disable Bit */
456  TIMx->CR1 |= TIM_CR1_UDIS;
457  }
458  else
459  {
460  /* Reset the Update Disable Bit */
461  TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS;
462  }
463 }
464 
476 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
477 {
478  /* Check the parameters */
480  assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
481 
482  if (TIM_UpdateSource != TIM_UpdateSource_Global)
483  {
484  /* Set the URS Bit */
485  TIMx->CR1 |= TIM_CR1_URS;
486  }
487  else
488  {
489  /* Reset the URS Bit */
490  TIMx->CR1 &= (uint16_t)~TIM_CR1_URS;
491  }
492 }
493 
503 {
504  /* Check the parameters */
507 
508  if (NewState != DISABLE)
509  {
510  /* Enable the TIM Counter */
511  TIMx->CR1 |= TIM_CR1_UIFREMAP;
512  }
513  else
514  {
515  /* Disable the TIM Counter */
516  TIMx->CR1 &= (uint16_t)~TIM_CR1_UIFREMAP;
517  }
518 }
519 
528 {
529  /* Check the parameters */
532 
533  if (NewState != DISABLE)
534  {
535  /* Set the ARR Preload Bit */
536  TIMx->CR1 |= TIM_CR1_ARPE;
537  }
538  else
539  {
540  /* Reset the ARR Preload Bit */
541  TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE;
542  }
543 }
544 
554 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
555 {
556  /* Check the parameters */
558  assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
559 
560  /* Reset the OPM Bit */
561  TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM;
562 
563  /* Configure the OPM Mode */
564  TIMx->CR1 |= TIM_OPMode;
565 }
566 
577 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
578 {
579  /* Check the parameters */
581  assert_param(IS_TIM_CKD_DIV(TIM_CKD));
582 
583  /* Reset the CKD Bits */
584  TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD);
585 
586  /* Set the CKD value */
587  TIMx->CR1 |= TIM_CKD;
588 }
589 
598 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
599 {
600  /* Check the parameters */
603 
604  if (NewState != DISABLE)
605  {
606  /* Enable the TIM Counter */
607  TIMx->CR1 |= TIM_CR1_CEN;
608  }
609  else
610  {
611  /* Disable the TIM Counter */
612  TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN;
613  }
614 }
676 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
677 {
678  uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
679 
680  /* Check the parameters */
682  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
684  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
685 
686  /* Disable the Channel 1: Reset the CC1E Bit */
687  TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
688 
689  /* Get the TIMx CCER register value */
690  tmpccer = TIMx->CCER;
691  /* Get the TIMx CR2 register value */
692  tmpcr2 = TIMx->CR2;
693 
694  /* Get the TIMx CCMR1 register value */
695  tmpccmrx = TIMx->CCMR1;
696 
697  /* Reset the Output Compare Mode Bits */
698  tmpccmrx &= (uint32_t)~TIM_CCMR1_OC1M;
699  tmpccmrx &= (uint32_t)~TIM_CCMR1_CC1S;
700  /* Select the Output Compare Mode */
701  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
702 
703  /* Reset the Output Polarity level */
704  tmpccer &= (uint32_t)~TIM_CCER_CC1P;
705  /* Set the Output Compare Polarity */
706  tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
707 
708  /* Set the Output State */
709  tmpccer |= TIM_OCInitStruct->TIM_OutputState;
710 
711  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM15) || (TIMx == TIM16) || (TIMx == TIM17))
712  {
717 
718  /* Reset the Output N Polarity level */
719  tmpccer &= (uint32_t)~TIM_CCER_CC1NP;
720  /* Set the Output N Polarity */
721  tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
722  /* Reset the Output N State */
723  tmpccer &= (uint32_t)~TIM_CCER_CC1NE;
724 
725  /* Set the Output N State */
726  tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
727  /* Reset the Output Compare and Output Compare N IDLE State */
728  tmpcr2 &= (uint32_t)~TIM_CR2_OIS1;
729  tmpcr2 &= (uint32_t)~TIM_CR2_OIS1N;
730  /* Set the Output Idle state */
731  tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
732  /* Set the Output N Idle state */
733  tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
734  }
735  /* Write to TIMx CR2 */
736  TIMx->CR2 = tmpcr2;
737 
738  /* Write to TIMx CCMR1 */
739  TIMx->CCMR1 = tmpccmrx;
740 
741  /* Set the Capture Compare Register value */
742  TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
743 
744  /* Write to TIMx CCER */
745  TIMx->CCER = tmpccer;
746 }
747 
756 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
757 {
758  uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
759 
760  /* Check the parameters */
762  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
764  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
765 
766  /* Disable the Channel 2: Reset the CC2E Bit */
767  TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
768 
769  /* Get the TIMx CCER register value */
770  tmpccer = TIMx->CCER;
771  /* Get the TIMx CR2 register value */
772  tmpcr2 = TIMx->CR2;
773 
774  /* Get the TIMx CCMR1 register value */
775  tmpccmrx = TIMx->CCMR1;
776 
777  /* Reset the Output Compare mode and Capture/Compare selection Bits */
778  tmpccmrx &= (uint32_t)~TIM_CCMR1_OC2M;
779  tmpccmrx &= (uint32_t)~TIM_CCMR1_CC2S;
780 
781  /* Select the Output Compare Mode */
782  tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8);
783 
784  /* Reset the Output Polarity level */
785  tmpccer &= (uint32_t)~TIM_CCER_CC2P;
786  /* Set the Output Compare Polarity */
787  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 4);
788 
789  /* Set the Output State */
790  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 4);
791 
792  if((TIMx == TIM1) || (TIMx == TIM8))
793  {
798 
799  /* Reset the Output N Polarity level */
800  tmpccer &= (uint32_t)~TIM_CCER_CC2NP;
801  /* Set the Output N Polarity */
802  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNPolarity << 4);
803  /* Reset the Output N State */
804  tmpccer &= (uint32_t)~TIM_CCER_CC2NE;
805 
806  /* Set the Output N State */
807  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputNState << 4);
808  /* Reset the Output Compare and Output Compare N IDLE State */
809  tmpcr2 &= (uint32_t)~TIM_CR2_OIS2;
810  tmpcr2 &= (uint32_t)~TIM_CR2_OIS2N;
811  /* Set the Output Idle state */
812  tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 2);
813  /* Set the Output N Idle state */
814  tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNIdleState << 2);
815  }
816  /* Write to TIMx CR2 */
817  TIMx->CR2 = tmpcr2;
818 
819  /* Write to TIMx CCMR1 */
820  TIMx->CCMR1 = tmpccmrx;
821 
822  /* Set the Capture Compare Register value */
823  TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
824 
825  /* Write to TIMx CCER */
826  TIMx->CCER = tmpccer;
827 }
828 
837 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
838 {
839  uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
840 
841  /* Check the parameters */
843  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
845  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
846 
847  /* Disable the Channel 3: Reset the CC2E Bit */
848  TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
849 
850  /* Get the TIMx CCER register value */
851  tmpccer = TIMx->CCER;
852  /* Get the TIMx CR2 register value */
853  tmpcr2 = TIMx->CR2;
854 
855  /* Get the TIMx CCMR2 register value */
856  tmpccmrx = TIMx->CCMR2;
857 
858  /* Reset the Output Compare mode and Capture/Compare selection Bits */
859  tmpccmrx &= (uint32_t)~TIM_CCMR2_OC3M;
860  tmpccmrx &= (uint32_t)~TIM_CCMR2_CC3S;
861  /* Select the Output Compare Mode */
862  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
863 
864  /* Reset the Output Polarity level */
865  tmpccer &= (uint32_t)~TIM_CCER_CC3P;
866  /* Set the Output Compare Polarity */
867  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 8);
868 
869  /* Set the Output State */
870  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 8);
871 
872  if((TIMx == TIM1) || (TIMx == TIM8))
873  {
878 
879  /* Reset the Output N Polarity level */
880  tmpccer &= (uint32_t)~TIM_CCER_CC3NP;
881  /* Set the Output N Polarity */
882  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNPolarity << 8);
883  /* Reset the Output N State */
884  tmpccer &= (uint32_t)~TIM_CCER_CC3NE;
885 
886  /* Set the Output N State */
887  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputNState << 8);
888  /* Reset the Output Compare and Output Compare N IDLE State */
889  tmpcr2 &= (uint32_t)~TIM_CR2_OIS3;
890  tmpcr2 &= (uint32_t)~TIM_CR2_OIS3N;
891  /* Set the Output Idle state */
892  tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 4);
893  /* Set the Output N Idle state */
894  tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNIdleState << 4);
895  }
896  /* Write to TIMx CR2 */
897  TIMx->CR2 = tmpcr2;
898 
899  /* Write to TIMx CCMR2 */
900  TIMx->CCMR2 = tmpccmrx;
901 
902  /* Set the Capture Compare Register value */
903  TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
904 
905  /* Write to TIMx CCER */
906  TIMx->CCER = tmpccer;
907 }
908 
917 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
918 {
919  uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
920 
921  /* Check the parameters */
923  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
925  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
926 
927  /* Disable the Channel 4: Reset the CC4E Bit */
928  TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
929 
930  /* Get the TIMx CCER register value */
931  tmpccer = TIMx->CCER;
932  /* Get the TIMx CR2 register value */
933  tmpcr2 = TIMx->CR2;
934 
935  /* Get the TIMx CCMR2 register value */
936  tmpccmrx = TIMx->CCMR2;
937 
938  /* Reset the Output Compare mode and Capture/Compare selection Bits */
939  tmpccmrx &= (uint32_t)~TIM_CCMR2_OC4M;
940  tmpccmrx &= (uint32_t)~TIM_CCMR2_CC4S;
941 
942  /* Select the Output Compare Mode */
943  tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8);
944 
945  /* Reset the Output Polarity level */
946  tmpccer &= (uint32_t)~TIM_CCER_CC4P;
947  /* Set the Output Compare Polarity */
948  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 12);
949 
950  /* Set the Output State */
951  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 12);
952 
953  if((TIMx == TIM1) || (TIMx == TIM8))
954  {
956  /* Reset the Output Compare IDLE State */
957  tmpcr2 &=(uint32_t) ~TIM_CR2_OIS4;
958  /* Set the Output Idle state */
959  tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 6);
960  }
961  /* Write to TIMx CR2 */
962  TIMx->CR2 = tmpcr2;
963 
964  /* Write to TIMx CCMR2 */
965  TIMx->CCMR2 = tmpccmrx;
966 
967  /* Set the Capture Compare Register value */
968  TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
969 
970  /* Write to TIMx CCER */
971  TIMx->CCER = tmpccer;
972 }
973 
982 void TIM_OC5Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
983 {
984  uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
985 
986  /* Check the parameters */
988  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
990  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
991 
992  /* Disable the Channel 5: Reset the CC5E Bit */
993  TIMx->CCER &= (uint32_t)~TIM_CCER_CC5E; /* to be verified*/
994 
995  /* Get the TIMx CCER register value */
996  tmpccer = TIMx->CCER;
997  /* Get the TIMx CR2 register value */
998  tmpcr2 = TIMx->CR2;
999 
1000  /* Get the TIMx CCMR3 register value */
1001  tmpccmrx = TIMx->CCMR3;
1002 
1003  /* Reset the Output Compare mode and Capture/Compare selection Bits */
1004  tmpccmrx &= (uint32_t)~TIM_CCMR3_OC5M;
1005 
1006  /* Select the Output Compare Mode */
1007  tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode);
1008 
1009  /* Reset the Output Polarity level */
1010  tmpccer &= (uint32_t)~TIM_CCER_CC5P;
1011  /* Set the Output Compare Polarity */
1012  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 16);
1013 
1014  /* Set the Output State */
1015  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 16);
1016 
1017  if((TIMx == TIM1) || (TIMx == TIM8))
1018  {
1019  assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
1020  /* Reset the Output Compare IDLE State */
1021  tmpcr2 &=(uint32_t) ~TIM_CR2_OIS5;
1022  /* Set the Output Idle state */
1023  tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 16);
1024  }
1025  /* Write to TIMx CR2 */
1026  TIMx->CR2 = tmpcr2;
1027 
1028  /* Write to TIMx CCMR2 */
1029  TIMx->CCMR3 = tmpccmrx;
1030 
1031  /* Set the Capture Compare Register value */
1032  TIMx->CCR5 = TIM_OCInitStruct->TIM_Pulse;
1033 
1034  /* Write to TIMx CCER */
1035  TIMx->CCER = tmpccer;
1036 }
1037 
1046 void TIM_OC6Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
1047 {
1048  uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
1049 
1050  /* Check the parameters */
1052  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
1053  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
1054  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
1055 
1056  /* Disable the Channel 5: Reset the CC5E Bit */
1057  TIMx->CCER &= (uint32_t)~TIM_CCER_CC6E; /* to be verified*/
1058 
1059  /* Get the TIMx CCER register value */
1060  tmpccer = TIMx->CCER;
1061  /* Get the TIMx CR2 register value */
1062  tmpcr2 = TIMx->CR2;
1063 
1064  /* Get the TIMx CCMR3 register value */
1065  tmpccmrx = TIMx->CCMR3;
1066 
1067  /* Reset the Output Compare mode and Capture/Compare selection Bits */
1068  tmpccmrx &= (uint32_t)~TIM_CCMR3_OC6M;
1069 
1070  /* Select the Output Compare Mode */
1071  tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8);
1072 
1073  /* Reset the Output Polarity level */
1074  tmpccer &= (uint32_t)~TIM_CCER_CC6P;
1075  /* Set the Output Compare Polarity */
1076  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 20);
1077 
1078  /* Set the Output State */
1079  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 20);
1080 
1081  if((TIMx == TIM1) || (TIMx == TIM8))
1082  {
1083  assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
1084  /* Reset the Output Compare IDLE State */
1085  tmpcr2 &=(uint32_t) ~TIM_CR2_OIS6;
1086  /* Set the Output Idle state */
1087  tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 18);
1088  }
1089  /* Write to TIMx CR2 */
1090  TIMx->CR2 = tmpcr2;
1091 
1092  /* Write to TIMx CCMR2 */
1093  TIMx->CCMR3 = tmpccmrx;
1094 
1095  /* Set the Capture Compare Register value */
1096  TIMx->CCR6 = TIM_OCInitStruct->TIM_Pulse;
1097 
1098  /* Write to TIMx CCER */
1099  TIMx->CCER = tmpccer;
1100 }
1101 
1111 {
1112  /* Check the parameters */
1114  assert_param(IS_FUNCTIONAL_STATE(NewState));
1115 
1116  if (NewState != DISABLE)
1117  {
1118  /* Set the GC5C1 Bit */
1119  TIMx->CCR5 |= TIM_CCR5_GC5C1;
1120  }
1121  else
1122  {
1123  /* Reset the GC5C1 Bit */
1124  TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C1;
1125  }
1126 }
1127 
1137 {
1138  /* Check the parameters */
1140  assert_param(IS_FUNCTIONAL_STATE(NewState));
1141 
1142  if (NewState != DISABLE)
1143  {
1144  /* Set the GC5C2 Bit */
1145  TIMx->CCR5 |= TIM_CCR5_GC5C2;
1146  }
1147  else
1148  {
1149  /* Reset the GC5C2 Bit */
1150  TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C2;
1151  }
1152 }
1153 
1154 
1164 {
1165  /* Check the parameters */
1167  assert_param(IS_FUNCTIONAL_STATE(NewState));
1168 
1169  if (NewState != DISABLE)
1170  {
1171  /* Set the GC5C3 Bit */
1172  TIMx->CCR5 |= TIM_CCR5_GC5C3;
1173  }
1174  else
1175  {
1176  /* Reset the GC5C3 Bit */
1177  TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C3;
1178  }
1179 }
1180 
1187 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
1188 {
1189  /* Set the default configuration */
1190  TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
1191  TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
1192  TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
1193  TIM_OCInitStruct->TIM_Pulse = 0x00000000;
1194  TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
1195  TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
1196  TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
1197  TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
1198 }
1199 
1229 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint32_t TIM_OCMode)
1230 {
1231  uint32_t tmp = 0;
1232  uint16_t tmp1 = 0;
1233 
1234  /* Check the parameters */
1236  assert_param(IS_TIM_CHANNEL(TIM_Channel));
1237  assert_param(IS_TIM_OCM(TIM_OCMode));
1238 
1239  tmp = (uint32_t) TIMx;
1240  tmp += CCMR_OFFSET;
1241 
1242  tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
1243 
1244  /* Disable the Channel: Reset the CCxE Bit */
1245  TIMx->CCER &= (uint16_t) ~tmp1;
1246 
1247  if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
1248  {
1249  tmp += (TIM_Channel>>1);
1250 
1251  /* Reset the OCxM bits in the CCMRx register */
1252  *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK;
1253 
1254  /* Configure the OCxM bits in the CCMRx register */
1255  *(__IO uint32_t *) tmp |= TIM_OCMode;
1256  }
1257  else
1258  {
1259  tmp += (uint32_t)(TIM_Channel - (uint32_t)4)>> (uint32_t)1;
1260 
1261  /* Reset the OCxM bits in the CCMRx register */
1262  *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK;
1263 
1264  /* Configure the OCxM bits in the CCMRx register */
1265  *(__IO uint32_t *) tmp |= (uint32_t)(TIM_OCMode << 8);
1266  }
1267 }
1268 
1275 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
1276 {
1277  /* Check the parameters */
1279 
1280  /* Set the Capture Compare1 Register value */
1281  TIMx->CCR1 = Compare1;
1282 }
1283 
1291 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
1292 {
1293  /* Check the parameters */
1295 
1296  /* Set the Capture Compare2 Register value */
1297  TIMx->CCR2 = Compare2;
1298 }
1299 
1306 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
1307 {
1308  /* Check the parameters */
1310 
1311  /* Set the Capture Compare3 Register value */
1312  TIMx->CCR3 = Compare3;
1313 }
1314 
1321 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
1322 {
1323  /* Check the parameters */
1325 
1326  /* Set the Capture Compare4 Register value */
1327  TIMx->CCR4 = Compare4;
1328 }
1329 
1336 void TIM_SetCompare5(TIM_TypeDef* TIMx, uint32_t Compare5)
1337 {
1338  /* Check the parameters */
1340 
1341  /* Set the Capture Compare5 Register value */
1342  TIMx->CCR5 = Compare5;
1343 }
1344 
1351 void TIM_SetCompare6(TIM_TypeDef* TIMx, uint32_t Compare6)
1352 {
1353  /* Check the parameters */
1355 
1356  /* Set the Capture Compare6 Register value */
1357  TIMx->CCR6 = Compare6;
1358 }
1359 
1369 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
1370 {
1371  uint32_t tmpccmr1 = 0;
1372 
1373  /* Check the parameters */
1375  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
1376  tmpccmr1 = TIMx->CCMR1;
1377 
1378  /* Reset the OC1M Bits */
1379  tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1M;
1380 
1381  /* Configure The Forced output Mode */
1382  tmpccmr1 |= TIM_ForcedAction;
1383 
1384  /* Write to TIMx CCMR1 register */
1385  TIMx->CCMR1 = tmpccmr1;
1386 }
1387 
1398 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
1399 {
1400  uint32_t tmpccmr1 = 0;
1401 
1402  /* Check the parameters */
1404  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
1405  tmpccmr1 = TIMx->CCMR1;
1406 
1407  /* Reset the OC2M Bits */
1408  tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC2M;
1409 
1410  /* Configure The Forced output Mode */
1411  tmpccmr1 |= ((uint32_t)TIM_ForcedAction << 8);
1412 
1413  /* Write to TIMx CCMR1 register */
1414  TIMx->CCMR1 = tmpccmr1;
1415 }
1416 
1426 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
1427 {
1428  uint32_t tmpccmr2 = 0;
1429 
1430  /* Check the parameters */
1432  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
1433 
1434  tmpccmr2 = TIMx->CCMR2;
1435 
1436  /* Reset the OC1M Bits */
1437  tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3M;
1438 
1439  /* Configure The Forced output Mode */
1440  tmpccmr2 |= TIM_ForcedAction;
1441 
1442  /* Write to TIMx CCMR2 register */
1443  TIMx->CCMR2 = tmpccmr2;
1444 }
1445 
1455 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
1456 {
1457  uint32_t tmpccmr2 = 0;
1458 
1459  /* Check the parameters */
1461  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
1462  tmpccmr2 = TIMx->CCMR2;
1463 
1464  /* Reset the OC2M Bits */
1465  tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC4M;
1466 
1467  /* Configure The Forced output Mode */
1468  tmpccmr2 |= ((uint32_t)TIM_ForcedAction << 8);
1469 
1470  /* Write to TIMx CCMR2 register */
1471  TIMx->CCMR2 = tmpccmr2;
1472 }
1473 
1483 void TIM_ForcedOC5Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
1484 {
1485  uint32_t tmpccmr3 = 0;
1486 
1487  /* Check the parameters */
1489  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
1490  tmpccmr3 = TIMx->CCMR3;
1491 
1492  /* Reset the OC5M Bits */
1493  tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC5M;
1494 
1495  /* Configure The Forced output Mode */
1496  tmpccmr3 |= (uint32_t)(TIM_ForcedAction);
1497 
1498  /* Write to TIMx CCMR3 register */
1499  TIMx->CCMR3 = tmpccmr3;
1500 }
1501 
1511 void TIM_ForcedOC6Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
1512 {
1513  uint32_t tmpccmr3 = 0;
1514 
1515  /* Check the parameters */
1517  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
1518  tmpccmr3 = TIMx->CCMR3;
1519 
1520  /* Reset the OC6M Bits */
1521  tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC6M;
1522 
1523  /* Configure The Forced output Mode */
1524  tmpccmr3 |= ((uint32_t)TIM_ForcedAction << 8);
1525 
1526  /* Write to TIMx CCMR3 register */
1527  TIMx->CCMR3 = tmpccmr3;
1528 }
1529 
1539 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
1540 {
1541  uint32_t tmpccmr1 = 0;
1542 
1543  /* Check the parameters */
1545  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
1546 
1547  tmpccmr1 = TIMx->CCMR1;
1548 
1549  /* Reset the OC1PE Bit */
1550  tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC1PE);
1551 
1552  /* Enable or Disable the Output Compare Preload feature */
1553  tmpccmr1 |= TIM_OCPreload;
1554 
1555  /* Write to TIMx CCMR1 register */
1556  TIMx->CCMR1 = tmpccmr1;
1557 }
1558 
1569 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
1570 {
1571  uint32_t tmpccmr1 = 0;
1572 
1573  /* Check the parameters */
1575  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
1576 
1577  tmpccmr1 = TIMx->CCMR1;
1578 
1579  /* Reset the OC2PE Bit */
1580  tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC2PE);
1581 
1582  /* Enable or Disable the Output Compare Preload feature */
1583  tmpccmr1 |= ((uint32_t)TIM_OCPreload << 8);
1584 
1585  /* Write to TIMx CCMR1 register */
1586  TIMx->CCMR1 = tmpccmr1;
1587 }
1588 
1598 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
1599 {
1600  uint32_t tmpccmr2 = 0;
1601 
1602  /* Check the parameters */
1604  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
1605 
1606  tmpccmr2 = TIMx->CCMR2;
1607 
1608  /* Reset the OC3PE Bit */
1609  tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC3PE);
1610 
1611  /* Enable or Disable the Output Compare Preload feature */
1612  tmpccmr2 |= TIM_OCPreload;
1613 
1614  /* Write to TIMx CCMR2 register */
1615  TIMx->CCMR2 = tmpccmr2;
1616 }
1617 
1627 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
1628 {
1629  uint32_t tmpccmr2 = 0;
1630 
1631  /* Check the parameters */
1633  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
1634 
1635  tmpccmr2 = TIMx->CCMR2;
1636 
1637  /* Reset the OC4PE Bit */
1638  tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC4PE);
1639 
1640  /* Enable or Disable the Output Compare Preload feature */
1641  tmpccmr2 |= ((uint32_t)TIM_OCPreload << 8);
1642 
1643  /* Write to TIMx CCMR2 register */
1644  TIMx->CCMR2 = tmpccmr2;
1645 }
1646 
1656 void TIM_OC5PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
1657 {
1658  uint32_t tmpccmr3 = 0;
1659 
1660  /* Check the parameters */
1662  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
1663 
1664  tmpccmr3 = TIMx->CCMR3;
1665 
1666  /* Reset the OC5PE Bit */
1667  tmpccmr3 &= (uint32_t)(~TIM_CCMR3_OC5PE);
1668 
1669  /* Enable or Disable the Output Compare Preload feature */
1670  tmpccmr3 |= (uint32_t)(TIM_OCPreload);
1671 
1672  /* Write to TIMx CCMR3 register */
1673  TIMx->CCMR3 = tmpccmr3;
1674 }
1675 
1685 void TIM_OC6PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
1686 {
1687  uint32_t tmpccmr3 = 0;
1688 
1689  /* Check the parameters */
1691  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
1692 
1693  tmpccmr3 = TIMx->CCMR3;
1694 
1695  /* Reset the OC5PE Bit */
1696  tmpccmr3 &= (uint32_t)(~TIM_CCMR3_OC6PE);
1697 
1698  /* Enable or Disable the Output Compare Preload feature */
1699  tmpccmr3 |= ((uint32_t)TIM_OCPreload << 8);
1700 
1701  /* Write to TIMx CCMR3 register */
1702  TIMx->CCMR3 = tmpccmr3;
1703 }
1704 
1714 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
1715 {
1716  uint32_t tmpccmr1 = 0;
1717 
1718  /* Check the parameters */
1720  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
1721 
1722  /* Get the TIMx CCMR1 register value */
1723  tmpccmr1 = TIMx->CCMR1;
1724 
1725  /* Reset the OC1FE Bit */
1726  tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1FE;
1727 
1728  /* Enable or Disable the Output Compare Fast Bit */
1729  tmpccmr1 |= TIM_OCFast;
1730 
1731  /* Write to TIMx CCMR1 */
1732  TIMx->CCMR1 = tmpccmr1;
1733 }
1734 
1745 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
1746 {
1747  uint32_t tmpccmr1 = 0;
1748 
1749  /* Check the parameters */
1751  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
1752 
1753  /* Get the TIMx CCMR1 register value */
1754  tmpccmr1 = TIMx->CCMR1;
1755 
1756  /* Reset the OC2FE Bit */
1757  tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC2FE);
1758 
1759  /* Enable or Disable the Output Compare Fast Bit */
1760  tmpccmr1 |= ((uint32_t)TIM_OCFast << 8);
1761 
1762  /* Write to TIMx CCMR1 */
1763  TIMx->CCMR1 = tmpccmr1;
1764 }
1765 
1775 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
1776 {
1777  uint32_t tmpccmr2 = 0;
1778 
1779  /* Check the parameters */
1781  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
1782 
1783  /* Get the TIMx CCMR2 register value */
1784  tmpccmr2 = TIMx->CCMR2;
1785 
1786  /* Reset the OC3FE Bit */
1787  tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3FE;
1788 
1789  /* Enable or Disable the Output Compare Fast Bit */
1790  tmpccmr2 |= TIM_OCFast;
1791 
1792  /* Write to TIMx CCMR2 */
1793  TIMx->CCMR2 = tmpccmr2;
1794 }
1795 
1805 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
1806 {
1807  uint32_t tmpccmr2 = 0;
1808 
1809  /* Check the parameters */
1811  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
1812 
1813  /* Get the TIMx CCMR2 register value */
1814  tmpccmr2 = TIMx->CCMR2;
1815 
1816  /* Reset the OC4FE Bit */
1817  tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC4FE);
1818 
1819  /* Enable or Disable the Output Compare Fast Bit */
1820  tmpccmr2 |= ((uint32_t)TIM_OCFast << 8);
1821 
1822  /* Write to TIMx CCMR2 */
1823  TIMx->CCMR2 = tmpccmr2;
1824 }
1825 
1835 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
1836 {
1837  uint32_t tmpccmr1 = 0;
1838 
1839  /* Check the parameters */
1841  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
1842 
1843  tmpccmr1 = TIMx->CCMR1;
1844 
1845  /* Reset the OC1CE Bit */
1846  tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1CE;
1847 
1848  /* Enable or Disable the Output Compare Clear Bit */
1849  tmpccmr1 |= TIM_OCClear;
1850 
1851  /* Write to TIMx CCMR1 register */
1852  TIMx->CCMR1 = tmpccmr1;
1853 }
1854 
1865 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
1866 {
1867  uint32_t tmpccmr1 = 0;
1868 
1869  /* Check the parameters */
1871  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
1872 
1873  tmpccmr1 = TIMx->CCMR1;
1874 
1875  /* Reset the OC2CE Bit */
1876  tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC2CE;
1877 
1878  /* Enable or Disable the Output Compare Clear Bit */
1879  tmpccmr1 |= ((uint32_t)TIM_OCClear << 8);
1880 
1881  /* Write to TIMx CCMR1 register */
1882  TIMx->CCMR1 = tmpccmr1;
1883 }
1884 
1894 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
1895 {
1896  uint32_t tmpccmr2 = 0;
1897 
1898  /* Check the parameters */
1900  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
1901 
1902  tmpccmr2 = TIMx->CCMR2;
1903 
1904  /* Reset the OC3CE Bit */
1905  tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3CE;
1906 
1907  /* Enable or Disable the Output Compare Clear Bit */
1908  tmpccmr2 |= TIM_OCClear;
1909 
1910  /* Write to TIMx CCMR2 register */
1911  TIMx->CCMR2 = tmpccmr2;
1912 }
1913 
1923 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
1924 {
1925  uint32_t tmpccmr2 = 0;
1926 
1927  /* Check the parameters */
1929  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
1930 
1931  tmpccmr2 = TIMx->CCMR2;
1932 
1933  /* Reset the OC4CE Bit */
1934  tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC4CE;
1935 
1936  /* Enable or Disable the Output Compare Clear Bit */
1937  tmpccmr2 |= ((uint32_t)TIM_OCClear << 8);
1938 
1939  /* Write to TIMx CCMR2 register */
1940  TIMx->CCMR2 = tmpccmr2;
1941 }
1942 
1952 void TIM_ClearOC5Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
1953 {
1954  uint32_t tmpccmr3 = 0;
1955 
1956  /* Check the parameters */
1958  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
1959 
1960  tmpccmr3 = TIMx->CCMR3;
1961 
1962  /* Reset the OC5CE Bit */
1963  tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC5CE;
1964 
1965  /* Enable or Disable the Output Compare Clear Bit */
1966  tmpccmr3 |= (uint32_t)(TIM_OCClear);
1967 
1968  /* Write to TIMx CCMR3 register */
1969  TIMx->CCMR3 = tmpccmr3;
1970 }
1971 
1981 void TIM_ClearOC6Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
1982 {
1983  uint32_t tmpccmr3 = 0;
1984 
1985  /* Check the parameters */
1987  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
1988 
1989  tmpccmr3 = TIMx->CCMR3;
1990 
1991  /* Reset the OC5CE Bit */
1992  tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC6CE;
1993 
1994  /* Enable or Disable the Output Compare Clear Bit */
1995  tmpccmr3 |= ((uint32_t)TIM_OCClear << 8);
1996 
1997  /* Write to TIMx CCMR3 register */
1998  TIMx->CCMR3 = tmpccmr3;
1999 }
2000 
2010 void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear)
2011 {
2012  /* Check the parameters */
2014  assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear));
2015 
2016  /* Set the TIM_OCReferenceClear source */
2017  TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS);
2018  TIMx->SMCR |= TIM_OCReferenceClear;
2019 }
2020 
2030 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
2031 {
2032  uint32_t tmpccer = 0;
2033 
2034  /* Check the parameters */
2036  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
2037 
2038  tmpccer = TIMx->CCER;
2039 
2040  /* Set or Reset the CC1P Bit */
2041  tmpccer &= (uint32_t)(~TIM_CCER_CC1P);
2042  tmpccer |= TIM_OCPolarity;
2043 
2044  /* Write to TIMx CCER register */
2045  TIMx->CCER = tmpccer;
2046 }
2047 
2057 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
2058 {
2059  uint32_t tmpccer = 0;
2060  /* Check the parameters */
2062  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
2063 
2064  tmpccer = TIMx->CCER;
2065 
2066  /* Set or Reset the CC1NP Bit */
2067  tmpccer &= (uint32_t)~TIM_CCER_CC1NP;
2068  tmpccer |= TIM_OCNPolarity;
2069 
2070  /* Write to TIMx CCER register */
2071  TIMx->CCER = tmpccer;
2072 }
2073 
2084 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
2085 {
2086  uint32_t tmpccer = 0;
2087 
2088  /* Check the parameters */
2090  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
2091 
2092  tmpccer = TIMx->CCER;
2093 
2094  /* Set or Reset the CC2P Bit */
2095  tmpccer &= (uint32_t)(~TIM_CCER_CC2P);
2096  tmpccer |= ((uint32_t)TIM_OCPolarity << 4);
2097 
2098  /* Write to TIMx CCER register */
2099  TIMx->CCER = tmpccer;
2100 }
2101 
2111 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
2112 {
2113  uint32_t tmpccer = 0;
2114 
2115  /* Check the parameters */
2117  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
2118 
2119  tmpccer = TIMx->CCER;
2120 
2121  /* Set or Reset the CC2NP Bit */
2122  tmpccer &= (uint32_t)~TIM_CCER_CC2NP;
2123  tmpccer |= ((uint32_t)TIM_OCNPolarity << 4);
2124 
2125  /* Write to TIMx CCER register */
2126  TIMx->CCER = tmpccer;
2127 }
2128 
2138 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
2139 {
2140  uint32_t tmpccer = 0;
2141 
2142  /* Check the parameters */
2144  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
2145 
2146  tmpccer = TIMx->CCER;
2147 
2148  /* Set or Reset the CC3P Bit */
2149  tmpccer &= (uint32_t)~TIM_CCER_CC3P;
2150  tmpccer |= ((uint32_t)TIM_OCPolarity << 8);
2151 
2152  /* Write to TIMx CCER register */
2153  TIMx->CCER = tmpccer;
2154 }
2155 
2165 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
2166 {
2167  uint32_t tmpccer = 0;
2168 
2169  /* Check the parameters */
2171  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
2172 
2173  tmpccer = TIMx->CCER;
2174 
2175  /* Set or Reset the CC3NP Bit */
2176  tmpccer &= (uint32_t)~TIM_CCER_CC3NP;
2177  tmpccer |= ((uint32_t)TIM_OCNPolarity << 8);
2178 
2179  /* Write to TIMx CCER register */
2180  TIMx->CCER = tmpccer;
2181 }
2182 
2192 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
2193 {
2194  uint32_t tmpccer = 0;
2195 
2196  /* Check the parameters */
2198  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
2199 
2200  tmpccer = TIMx->CCER;
2201 
2202  /* Set or Reset the CC4P Bit */
2203  tmpccer &= (uint32_t)~TIM_CCER_CC4P;
2204  tmpccer |= ((uint32_t)TIM_OCPolarity << 12);
2205 
2206  /* Write to TIMx CCER register */
2207  TIMx->CCER = tmpccer;
2208 }
2209 
2219 void TIM_OC5PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
2220 {
2221  uint32_t tmpccer = 0;
2222 
2223  /* Check the parameters */
2225  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
2226 
2227  tmpccer = TIMx->CCER;
2228 
2229  /* Set or Reset the CC5P Bit */
2230  tmpccer &= (uint32_t)~TIM_CCER_CC5P;
2231  tmpccer |= ((uint32_t)TIM_OCPolarity << 16);
2232 
2233  /* Write to TIMx CCER register */
2234  TIMx->CCER = tmpccer;
2235 }
2236 
2246 void TIM_OC6PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
2247 {
2248  uint32_t tmpccer = 0;
2249 
2250  /* Check the parameters */
2252  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
2253 
2254  tmpccer = TIMx->CCER;
2255 
2256  /* Set or Reset the CC6P Bit */
2257  tmpccer &= (uint32_t)~TIM_CCER_CC6P;
2258  tmpccer |= ((uint32_t)TIM_OCPolarity << 20);
2259 
2260  /* Write to TIMx CCER register */
2261  TIMx->CCER = tmpccer;
2262 }
2263 
2279 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
2280 {
2281  uint32_t tmp = 0;
2282 
2283  /* Check the parameters */
2285  assert_param(IS_TIM_CHANNEL(TIM_Channel));
2286  assert_param(IS_TIM_CCX(TIM_CCx));
2287 
2288  tmp = (uint32_t)CCER_CCE_SET << (uint32_t)TIM_Channel;
2289 
2290  /* Reset the CCxE Bit */
2291  TIMx->CCER &= (uint32_t)(~tmp);
2292 
2293  /* Set or reset the CCxE Bit */
2294  TIMx->CCER |= ((uint32_t)TIM_CCx << (uint32_t)TIM_Channel);
2295 }
2296 
2309 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
2310 {
2311  uint32_t tmp = 0;
2312 
2313  /* Check the parameters */
2316  assert_param(IS_TIM_CCXN(TIM_CCxN));
2317 
2318  tmp = (uint32_t)CCER_CCNE_SET << (uint32_t)TIM_Channel;
2319 
2320  /* Reset the CCxNE Bit */
2321  TIMx->CCER &= (uint32_t) ~tmp;
2322 
2323  /* Set or reset the CCxNE Bit */
2324  TIMx->CCER |= ((uint32_t)TIM_CCxN << (uint32_t)TIM_Channel);
2325 }
2391 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
2392 {
2393  /* Check the parameters */
2395  assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
2396  assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
2397  assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
2398  assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
2399 
2400  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
2401  {
2402  /* TI1 Configuration */
2403  TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
2404  TIM_ICInitStruct->TIM_ICSelection,
2405  TIM_ICInitStruct->TIM_ICFilter);
2406  /* Set the Input Capture Prescaler value */
2407  TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
2408  }
2409  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
2410  {
2411  /* TI2 Configuration */
2412  TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
2413  TIM_ICInitStruct->TIM_ICSelection,
2414  TIM_ICInitStruct->TIM_ICFilter);
2415  /* Set the Input Capture Prescaler value */
2416  TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
2417  }
2418  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
2419  {
2420  /* TI3 Configuration */
2421  TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
2422  TIM_ICInitStruct->TIM_ICSelection,
2423  TIM_ICInitStruct->TIM_ICFilter);
2424  /* Set the Input Capture Prescaler value */
2425  TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
2426  }
2427  else
2428  {
2429  /* TI4 Configuration */
2430  TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
2431  TIM_ICInitStruct->TIM_ICSelection,
2432  TIM_ICInitStruct->TIM_ICFilter);
2433  /* Set the Input Capture Prescaler value */
2434  TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
2435  }
2436 }
2437 
2444 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
2445 {
2446  /* Set the default configuration */
2447  TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
2448  TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
2449  TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
2450  TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
2451  TIM_ICInitStruct->TIM_ICFilter = 0x00;
2452 }
2453 
2463 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
2464 {
2465  uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
2466  uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
2467 
2468  /* Check the parameters */
2470 
2471  /* Select the Opposite Input Polarity */
2472  if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
2473  {
2474  icoppositepolarity = TIM_ICPolarity_Falling;
2475  }
2476  else
2477  {
2478  icoppositepolarity = TIM_ICPolarity_Rising;
2479  }
2480  /* Select the Opposite Input */
2481  if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
2482  {
2483  icoppositeselection = TIM_ICSelection_IndirectTI;
2484  }
2485  else
2486  {
2487  icoppositeselection = TIM_ICSelection_DirectTI;
2488  }
2489  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
2490  {
2491  /* TI1 Configuration */
2492  TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
2493  TIM_ICInitStruct->TIM_ICFilter);
2494  /* Set the Input Capture Prescaler value */
2495  TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
2496  /* TI2 Configuration */
2497  TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
2498  /* Set the Input Capture Prescaler value */
2499  TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
2500  }
2501  else
2502  {
2503  /* TI2 Configuration */
2504  TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
2505  TIM_ICInitStruct->TIM_ICFilter);
2506  /* Set the Input Capture Prescaler value */
2507  TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
2508  /* TI1 Configuration */
2509  TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
2510  /* Set the Input Capture Prescaler value */
2511  TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
2512  }
2513 }
2514 
2521 {
2522  /* Check the parameters */
2524 
2525  /* Get the Capture 1 Register value */
2526  return TIMx->CCR1;
2527 }
2528 
2536 {
2537  /* Check the parameters */
2539 
2540  /* Get the Capture 2 Register value */
2541  return TIMx->CCR2;
2542 }
2543 
2550 {
2551  /* Check the parameters */
2553 
2554  /* Get the Capture 3 Register value */
2555  return TIMx->CCR3;
2556 }
2557 
2564 {
2565  /* Check the parameters */
2567 
2568  /* Get the Capture 4 Register value */
2569  return TIMx->CCR4;
2570 }
2571 
2583 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
2584 {
2585  /* Check the parameters */
2587  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
2588 
2589  /* Reset the IC1PSC Bits */
2590  TIMx->CCMR1 &= (uint32_t)~TIM_CCMR1_IC1PSC;
2591 
2592  /* Set the IC1PSC value */
2593  TIMx->CCMR1 |= TIM_ICPSC;
2594 }
2595 
2608 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
2609 {
2610  /* Check the parameters */
2612  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
2613 
2614  /* Reset the IC2PSC Bits */
2615  TIMx->CCMR1 &= (uint32_t)~TIM_CCMR1_IC2PSC;
2616 
2617  /* Set the IC2PSC value */
2618  TIMx->CCMR1 |= (uint32_t)((uint32_t)TIM_ICPSC << 8);
2619 }
2620 
2632 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
2633 {
2634  /* Check the parameters */
2636  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
2637 
2638  /* Reset the IC3PSC Bits */
2639  TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC;
2640 
2641  /* Set the IC3PSC value */
2642  TIMx->CCMR2 |= TIM_ICPSC;
2643 }
2644 
2656 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
2657 {
2658  /* Check the parameters */
2660  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
2661 
2662  /* Reset the IC4PSC Bits */
2663  TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC;
2664 
2665  /* Set the IC4PSC value */
2666  TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
2667 }
2709 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
2710 {
2711  /* Check the parameters */
2713  assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
2714  assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
2715  assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
2716  assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
2719 
2720  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
2721  the OSSI State, the dead time value and the Automatic Output Enable Bit */
2722  TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
2723  TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
2724  TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
2725  TIM_BDTRInitStruct->TIM_AutomaticOutput;
2726 }
2727 
2739 void TIM_Break1Config(TIM_TypeDef* TIMx, uint32_t TIM_Break1Polarity, uint8_t TIM_Break1Filter)
2740 { /* Check the parameters */
2742  assert_param(IS_TIM_BREAK1_FILTER(TIM_Break1Filter));
2743 
2744  /* Reset the BKP and BKF Bits */
2745  TIMx->BDTR &= (uint32_t)~ (TIM_BDTR_BKP | TIM_BDTR_BKF);
2746  /* Configure the Break1 polarity and filter */
2747  TIMx->BDTR |= TIM_Break1Polarity |((uint32_t)TIM_Break1Filter << 16);
2748 }
2749 
2761 void TIM_Break2Config(TIM_TypeDef* TIMx, uint32_t TIM_Break2Polarity, uint8_t TIM_Break2Filter)
2762 {
2763  /* Check the parameters */
2765  assert_param(IS_TIM_BREAK2_FILTER(TIM_Break2Filter));
2766 
2767  /* Reset the BKP and BKF Bits */
2768  TIMx->BDTR &= (uint32_t)~ (TIM_BDTR_BK2P | TIM_BDTR_BK2F);
2769 
2770  /* Configure the Break1 polarity and filter */
2771  TIMx->BDTR |= TIM_Break2Polarity |((uint32_t)TIM_Break2Filter << 20);
2772 }
2773 
2782 {
2783  /* Check the parameters */
2785  assert_param(IS_FUNCTIONAL_STATE(NewState));
2786 
2787  if (NewState != DISABLE)
2788  {
2789  /* Enable the Break1 */
2790  TIMx->BDTR |= TIM_BDTR_BKE;
2791  }
2792  else
2793  {
2794  /* Disable the Break1 */
2795  TIMx->BDTR &= (uint32_t)~TIM_BDTR_BKE;
2796  }
2797 }
2798 
2807 {
2808  /* Check the parameters */
2810  assert_param(IS_FUNCTIONAL_STATE(NewState));
2811 
2812  if (NewState != DISABLE)
2813  {
2814  /* Enable the Break1 */
2815  TIMx->BDTR |= TIM_BDTR_BK2E;
2816  }
2817  else
2818  {
2819  /* Disable the Break1 */
2820  TIMx->BDTR &= (uint32_t)~TIM_BDTR_BK2E;
2821  }
2822 }
2823 
2830 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
2831 {
2832  /* Set the default configuration */
2833  TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
2834  TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
2835  TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
2836  TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
2837  TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
2838  TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
2839  TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
2840 }
2841 
2850 {
2851  /* Check the parameters */
2853  assert_param(IS_FUNCTIONAL_STATE(NewState));
2854 
2855  if (NewState != DISABLE)
2856  {
2857  /* Enable the TIM Main Output */
2858  TIMx->BDTR |= TIM_BDTR_MOE;
2859  }
2860  else
2861  {
2862  /* Disable the TIM Main Output */
2863  TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE;
2864  }
2865 }
2866 
2875 {
2876  /* Check the parameters */
2878  assert_param(IS_FUNCTIONAL_STATE(NewState));
2879 
2880  if (NewState != DISABLE)
2881  {
2882  /* Set the COM Bit */
2883  TIMx->CR2 |= TIM_CR2_CCUS;
2884  }
2885  else
2886  {
2887  /* Reset the COM Bit */
2888  TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS;
2889  }
2890 }
2891 
2900 {
2901  /* Check the parameters */
2903  assert_param(IS_FUNCTIONAL_STATE(NewState));
2904  if (NewState != DISABLE)
2905  {
2906  /* Set the CCPC Bit */
2907  TIMx->CR2 |= TIM_CR2_CCPC;
2908  }
2909  else
2910  {
2911  /* Reset the CCPC Bit */
2912  TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC;
2913  }
2914 }
2956 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
2957 {
2958  /* Check the parameters */
2960  assert_param(IS_TIM_IT(TIM_IT));
2961  assert_param(IS_FUNCTIONAL_STATE(NewState));
2962 
2963  if (NewState != DISABLE)
2964  {
2965  /* Enable the Interrupt sources */
2966  TIMx->DIER |= TIM_IT;
2967  }
2968  else
2969  {
2970  /* Disable the Interrupt sources */
2971  TIMx->DIER &= (uint16_t)~TIM_IT;
2972  }
2973 }
2974 
2994 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
2995 {
2996  /* Check the parameters */
2998  assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
2999 
3000  /* Set the event sources */
3001  TIMx->EGR = TIM_EventSource;
3002 }
3003 
3029 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint32_t TIM_FLAG)
3030 {
3031  ITStatus bitstatus = RESET;
3032  /* Check the parameters */
3034  assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
3035 
3036 
3037  if ((TIMx->SR & TIM_FLAG) != RESET)
3038  {
3039  bitstatus = SET;
3040  }
3041  else
3042  {
3043  bitstatus = RESET;
3044  }
3045  return bitstatus;
3046 }
3047 
3073 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
3074 {
3075  /* Check the parameters */
3077 
3078  /* Clear the flags */
3079  TIMx->SR = (uint16_t)~TIM_FLAG;
3080 }
3081 
3101 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
3102 {
3103  ITStatus bitstatus = RESET;
3104  uint16_t itstatus = 0x0, itenable = 0x0;
3105  /* Check the parameters */
3107  assert_param(IS_TIM_GET_IT(TIM_IT));
3108 
3109  itstatus = TIMx->SR & TIM_IT;
3110 
3111  itenable = TIMx->DIER & TIM_IT;
3112  if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
3113  {
3114  bitstatus = SET;
3115  }
3116  else
3117  {
3118  bitstatus = RESET;
3119  }
3120  return bitstatus;
3121 }
3122 
3142 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
3143 {
3144  /* Check the parameters */
3146 
3147  /* Clear the IT pending Bit */
3148  TIMx->SR = (uint16_t)~TIM_IT;
3149 }
3150 
3179 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
3180 {
3181  /* Check the parameters */
3183  assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
3184  assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
3185 
3186  /* Set the DMA Base and the DMA Burst Length */
3187  TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
3188 }
3189 
3206 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
3207 {
3208  /* Check the parameters */
3210  assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
3211  assert_param(IS_FUNCTIONAL_STATE(NewState));
3212 
3213  if (NewState != DISABLE)
3214  {
3215  /* Enable the DMA sources */
3216  TIMx->DIER |= TIM_DMASource;
3217  }
3218  else
3219  {
3220  /* Disable the DMA sources */
3221  TIMx->DIER &= (uint16_t)~TIM_DMASource;
3222  }
3223 }
3224 
3233 {
3234  /* Check the parameters */
3236  assert_param(IS_FUNCTIONAL_STATE(NewState));
3237 
3238  if (NewState != DISABLE)
3239  {
3240  /* Set the CCDS Bit */
3241  TIMx->CR2 |= TIM_CR2_CCDS;
3242  }
3243  else
3244  {
3245  /* Reset the CCDS Bit */
3246  TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS;
3247  }
3248 }
3272 {
3273  /* Check the parameters */
3275 
3276  /* Disable slave mode to clock the prescaler directly with the internal clock */
3277  TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;
3278 }
3279 
3292 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
3293 {
3294  /* Check the parameters */
3296  assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
3297 
3298  /* Select the Internal Trigger */
3299  TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
3300 
3301  /* Select the External clock mode1 */
3302  TIMx->SMCR |= TIM_SlaveMode_External1;
3303 }
3304 
3322 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
3323  uint16_t TIM_ICPolarity, uint16_t ICFilter)
3324 {
3325  /* Check the parameters */
3327  assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
3328  assert_param(IS_TIM_IC_FILTER(ICFilter));
3329 
3330  /* Configure the Timer Input Clock Source */
3331  if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
3332  {
3333  TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
3334  }
3335  else
3336  {
3337  TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
3338  }
3339  /* Select the Trigger source */
3340  TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
3341  /* Select the External clock mode1 */
3342  TIMx->SMCR |= TIM_SlaveMode_External1;
3343 }
3344 
3362 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
3363  uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
3364 {
3365  uint16_t tmpsmcr = 0;
3366 
3367  /* Check the parameters */
3369  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
3370  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
3371  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
3372  /* Configure the ETR Clock source */
3373  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
3374 
3375  /* Get the TIMx SMCR register value */
3376  tmpsmcr = TIMx->SMCR;
3377 
3378  /* Reset the SMS Bits */
3379  tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
3380 
3381  /* Select the External clock mode1 */
3382  tmpsmcr |= TIM_SlaveMode_External1;
3383 
3384  /* Select the Trigger selection : ETRF */
3385  tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
3386  tmpsmcr |= TIM_TS_ETRF;
3387 
3388  /* Write to TIMx SMCR */
3389  TIMx->SMCR = tmpsmcr;
3390 }
3391 
3409 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
3410  uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
3411 {
3412  /* Check the parameters */
3414  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
3415  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
3416  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
3417 
3418  /* Configure the ETR Clock source */
3419  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
3420 
3421  /* Enable the External clock mode2 */
3422  TIMx->SMCR |= TIM_SMCR_ECE;
3423 }
3476 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
3477 {
3478  uint16_t tmpsmcr = 0;
3479 
3480  /* Check the parameters */
3482  assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
3483 
3484  /* Get the TIMx SMCR register value */
3485  tmpsmcr = TIMx->SMCR;
3486 
3487  /* Reset the TS Bits */
3488  tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
3489 
3490  /* Set the Input Trigger source */
3491  tmpsmcr |= TIM_InputTriggerSource;
3492 
3493  /* Write to TIMx SMCR */
3494  TIMx->SMCR = tmpsmcr;
3495 }
3496 
3519 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
3520 {
3521  /* Check the parameters */
3523  assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
3524 
3525  /* Reset the MMS Bits */
3526  TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS;
3527  /* Select the TRGO source */
3528  TIMx->CR2 |= TIM_TRGOSource;
3529 }
3530 
3557 void TIM_SelectOutputTrigger2(TIM_TypeDef* TIMx, uint32_t TIM_TRGO2Source)
3558 {
3559  /* Check the parameters */
3561  assert_param(IS_TIM_TRGO2_SOURCE(TIM_TRGO2Source));
3562 
3563  /* Reset the MMS Bits */
3564  TIMx->CR2 &= (uint32_t)~TIM_CR2_MMS2;
3565  /* Select the TRGO source */
3566  TIMx->CR2 |= TIM_TRGO2Source;
3567 }
3568 
3584 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode)
3585 {
3586  /* Check the parameters */
3588  assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
3589 
3590  /* Reset the SMS Bits */
3591  TIMx->SMCR &= (uint32_t)~TIM_SMCR_SMS;
3592 
3593  /* Select the Slave Mode */
3594  TIMx->SMCR |= (uint32_t)TIM_SlaveMode;
3595 }
3596 
3607 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
3608 {
3609  /* Check the parameters */
3611  assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
3612 
3613  /* Reset the MSM Bit */
3614  TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM;
3615 
3616  /* Set or Reset the MSM Bit */
3617  TIMx->SMCR |= TIM_MasterSlaveMode;
3618 }
3619 
3637 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
3638  uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
3639 {
3640  uint16_t tmpsmcr = 0;
3641 
3642  /* Check the parameters */
3644  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
3645  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
3646  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
3647 
3648  tmpsmcr = TIMx->SMCR;
3649 
3650  /* Reset the ETR Bits */
3651  tmpsmcr &= SMCR_ETR_MASK;
3652 
3653  /* Set the Prescaler, the Filter value and the Polarity */
3654  tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
3655 
3656  /* Write to TIMx SMCR */
3657  TIMx->SMCR = tmpsmcr;
3658 }
3695 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
3696  uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
3697 {
3698  uint16_t tmpsmcr = 0;
3699  uint16_t tmpccmr1 = 0;
3700  uint16_t tmpccer = 0;
3701 
3702  /* Check the parameters */
3704  assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
3705  assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
3706  assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
3707 
3708  /* Get the TIMx SMCR register value */
3709  tmpsmcr = TIMx->SMCR;
3710 
3711  /* Get the TIMx CCMR1 register value */
3712  tmpccmr1 = TIMx->CCMR1;
3713 
3714  /* Get the TIMx CCER register value */
3715  tmpccer = TIMx->CCER;
3716 
3717  /* Set the encoder Mode */
3718  tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
3719  tmpsmcr |= TIM_EncoderMode;
3720 
3721  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
3722  tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S);
3723  tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
3724 
3725  /* Set the TI1 and the TI2 Polarities */
3726  tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P);
3727  tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
3728 
3729  /* Write to TIMx SMCR */
3730  TIMx->SMCR = tmpsmcr;
3731 
3732  /* Write to TIMx CCMR1 */
3733  TIMx->CCMR1 = tmpccmr1;
3734 
3735  /* Write to TIMx CCER */
3736  TIMx->CCER = tmpccer;
3737 }
3738 
3748 {
3749  /* Check the parameters */
3751  assert_param(IS_FUNCTIONAL_STATE(NewState));
3752 
3753  if (NewState != DISABLE)
3754  {
3755  /* Set the TI1S Bit */
3756  TIMx->CR2 |= TIM_CR2_TI1S;
3757  }
3758  else
3759  {
3760  /* Reset the TI1S Bit */
3761  TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S;
3762  }
3763 }
3803 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
3804 {
3805  /* Check the parameters */
3807  assert_param(IS_TIM_REMAP(TIM_Remap));
3808 
3809  /* Set the Timer remapping configuration */
3810  TIMx->OR = TIM_Remap;
3811 }
3834 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
3835  uint16_t TIM_ICFilter)
3836 {
3837  uint32_t tmpccmr1 = 0, tmpccer = 0;
3838 
3839  /* Disable the Channel 1: Reset the CC1E Bit */
3840  TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
3841  tmpccmr1 = TIMx->CCMR1;
3842  tmpccer = TIMx->CCER;
3843 
3844  /* Select the Input and set the filter */
3845  tmpccmr1 &= ((uint32_t)~TIM_CCMR1_CC1S) & ((uint32_t)~TIM_CCMR1_IC1F);
3846  tmpccmr1 |= (uint32_t)(TIM_ICSelection | (uint32_t)((uint32_t)TIM_ICFilter << 4));
3847 
3848  /* Select the Polarity and set the CC1E Bit */
3849  tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
3850  tmpccer |= (uint32_t)(TIM_ICPolarity | (uint32_t)TIM_CCER_CC1E);
3851 
3852  /* Write to TIMx CCMR1 and CCER registers */
3853  TIMx->CCMR1 = tmpccmr1;
3854  TIMx->CCER = tmpccer;
3855 }
3856 
3875 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
3876  uint16_t TIM_ICFilter)
3877 {
3878  uint32_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
3879 
3880  /* Disable the Channel 2: Reset the CC2E Bit */
3881  TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
3882  tmpccmr1 = TIMx->CCMR1;
3883  tmpccer = TIMx->CCER;
3884  tmp = (uint16_t)(TIM_ICPolarity << 4);
3885 
3886  /* Select the Input and set the filter */
3887  tmpccmr1 &= ((uint32_t)~TIM_CCMR1_CC2S) & ((uint32_t)~TIM_CCMR1_IC2F);
3888  tmpccmr1 |= (uint32_t)((uint32_t)TIM_ICFilter << 12);
3889  tmpccmr1 |= (uint32_t)((uint32_t)TIM_ICSelection << 8);
3890 
3891  /* Select the Polarity and set the CC2E Bit */
3892  tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
3893  tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
3894 
3895  /* Write to TIMx CCMR1 and CCER registers */
3896  TIMx->CCMR1 = tmpccmr1 ;
3897  TIMx->CCER = tmpccer;
3898 }
3899 
3917 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
3918  uint16_t TIM_ICFilter)
3919 {
3920  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
3921 
3922  /* Disable the Channel 3: Reset the CC3E Bit */
3923  TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
3924  tmpccmr2 = TIMx->CCMR2;
3925  tmpccer = TIMx->CCER;
3926  tmp = (uint16_t)(TIM_ICPolarity << 8);
3927 
3928  /* Select the Input and set the filter */
3929  tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F);
3930  tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
3931 
3932  /* Select the Polarity and set the CC3E Bit */
3933  tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
3934  tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
3935 
3936  /* Write to TIMx CCMR2 and CCER registers */
3937  TIMx->CCMR2 = tmpccmr2;
3938  TIMx->CCER = tmpccer;
3939 }
3940 
3958 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
3959  uint16_t TIM_ICFilter)
3960 {
3961  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
3962 
3963  /* Disable the Channel 4: Reset the CC4E Bit */
3964  TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
3965  tmpccmr2 = TIMx->CCMR2;
3966  tmpccer = TIMx->CCER;
3967  tmp = (uint16_t)(TIM_ICPolarity << 12);
3968 
3969  /* Select the Input and set the filter */
3970  tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
3971  tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
3972  tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
3973 
3974  /* Select the Polarity and set the CC4E Bit */
3975  tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
3976  tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
3977 
3978  /* Write to TIMx CCMR2 and CCER registers */
3979  TIMx->CCMR2 = tmpccmr2;
3980  TIMx->CCER = tmpccer ;
3981 }
3982 
3995 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE)
#define TIM_CCMR1_OC1FE
Definition: stm32f4xx.h:10528
void TIM_SelectGC5C3(TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIM Group Channel 5 and Channel 3, OC3REFC is the logical AND of OC3REFC and OC5REF...
#define IS_TIM_COUNTER_MODE(MODE)
FlagStatus
Definition: stm32f4xx.h:706
void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIMx&#39;s Hall sensor interface.
void TIM_Break1Cmd(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIM Break1 input.
void TIM_SelectOutputTrigger2(TIM_TypeDef *TIMx, uint32_t TIM_TRGO2Source)
Selects the TIMx Trigger Output Mode2 (TRGO2).
#define IS_TIM_CKD_DIV(DIV)
#define TIM_PSCReloadMode_Immediate
#define IS_TIM_OC_MODE(MODE)
#define TIM_TS_ETRF
#define RCC_APB2Periph_TIM17
#define TIM_CCER_CC3NE
Definition: stm32f4xx.h:10636
uint16_t TIM_OutputNState
Definition: stm32f4xx_tim.h:92
#define TIM4
Definition: stm32f4xx.h:2039
uint32_t TIM_GetCapture3(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 3 value.
#define IS_TIM_EVENT_SOURCE(SOURCE)
#define IS_TIM_SLAVE_MODE(MODE)
void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 3 prescaler.
#define IS_TIM_LIST3_PERIPH(PERIPH)
#define TIM_OSSIState_Disable
#define TIM_AutomaticOutput_Disable
void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct.
void TIM_SetCompare5(TIM_TypeDef *TIMx, uint32_t Compare5)
Sets the TIMx Capture Compare5 Register value.
#define TIM_ICSelection_DirectTI
#define IS_TIM_BREAK1_FILTER(FILTER)
#define TIM_LOCKLevel_OFF
static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI1 as Input.
#define TIM_CCER_CC4P
Definition: stm32f4xx.h:10639
FunctionalState
Definition: stm32f4xx.h:708
#define TIM1
Definition: stm32f4xx.h:2078
void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.
#define TIM_CCMR1_OC1M
Definition: stm32f4xx.h:10531
#define TIM_CR2_CCDS
Definition: stm32f4xx.h:10440
#define IS_TIM_TRGO_SOURCE(SOURCE)
void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 1 waveform to active or inactive level.
void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF4 signal on an external event.
#define IS_TIM_EXT_POLARITY(POLARITY)
uint32_t TIM_GetCapture1(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 1 value.
__IO uint16_t CCER
Definition: stm32f4xx.h:1684
void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Configures the TIMx Internal Trigger as External Clock.
void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeB...
#define TIM_CCMR2_CC4S
Definition: stm32f4xx.h:10589
void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR4.
#define TIM_Channel_3
void TIM_SetCompare1(TIM_TypeDef *TIMx, uint32_t Compare1)
Sets the TIMx Capture Compare1 Register value.
#define TIM_BDTR_BKP
Definition: stm32f4xx.h:10684
void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
Enables or disables the TIM Capture Compare Channel x.
#define TIM_CCER_CC1NP
Definition: stm32f4xx.h:10629
#define TIM3
Definition: stm32f4xx.h:2038
#define TIM_CR2_OIS3N
Definition: stm32f4xx.h:10453
void TIM_OC6PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 6 polarity.
void TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
Sets the TIMx Counter Register value.
void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
Configures the TIMx&#39;s DMA interface.
void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 2 waveform to active or inactive level.
void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode)
Sets or Resets the TIMx Master/Slave Mode.
void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Selects the Input Trigger source.
#define IS_TIM_OUTPUTN_STATE(STATE)
#define IS_TIM_BREAK_STATE(STATE)
void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState)
Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
#define TIM_CCMR1_OC2FE
Definition: stm32f4xx.h:10542
void TIM_Break2Config(TIM_TypeDef *TIMx, uint32_t TIM_Break2Polarity, uint8_t TIM_Break2Filter)
Configures the Break2 feature.
#define TIM_OCNIdleState_Reset
void TIM_RemapConfig(TIM_TypeDef *TIMx, uint16_t TIM_Remap)
Configures the TIM16 Remapping input Capabilities.
#define TIM2
Definition: stm32f4xx.h:2037
#define TIM_OutputNState_Disable
#define TIM8
Definition: stm32f4xx.h:2079
#define CCMR_OFFSET
#define TIM_CCMR1_CC1S
Definition: stm32f4xx.h:10524
#define IS_TIM_PRESCALER_RELOAD(RELOAD)
uint16_t TIM_AutomaticOutput
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Fills each TIM_TimeBaseInitStruct member with its default value.
#define TIM_ICSelection_IndirectTI
#define TIM_CR1_CEN
Definition: stm32f4xx.h:10421
#define TIM_CCER_CC3P
Definition: stm32f4xx.h:10635
#define IS_TIM_GET_IT(IT)
__IO uint16_t PSC
Definition: stm32f4xx.h:1687
#define IS_TIM_BREAK2_FILTER(FILTER)
void TIM_DeInit(TIM_TypeDef *TIMx)
Deinitializes the TIMx peripheral registers to their default reset values.
#define TIM_ICPolarity_Falling
#define TIM_CCMR2_IC3F
Definition: stm32f4xx.h:10609
#define IS_TIM_UPDATE_SOURCE(SOURCE)
#define TIM_CCMR2_CC3S
Definition: stm32f4xx.h:10575
#define TIM_SlaveMode_External1
ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT)
Checks whether the TIM interrupt has occurred or not.
#define TIM_CCER_CC1E
Definition: stm32f4xx.h:10626
void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode1.
__IO uint16_t CCMR1
Definition: stm32f4xx.h:1680
#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE)
#define TIM_CR1_CMS
Definition: stm32f4xx.h:10427
#define TIM_Channel_2
void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD)
Sets the TIMx Clock Division value.
#define CCMR_OC13M_MASK
#define TIM_CR2_OIS1N
Definition: stm32f4xx.h:10449
#define IS_TIM_ENCODER_MODE(MODE)
void assert_param(int val)
#define TIM_CR2_OIS3
Definition: stm32f4xx.h:10452
#define IS_TIM_OCFAST_STATE(STATE)
void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 4 Fast feature.
#define IS_TIM_IC_PRESCALER(PRESCALER)
#define IS_TIM_OCM(MODE)
#define IS_TIM_CCX(CCX)
void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource)
Selects the TIMx Trigger Output Mode.
FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint32_t TIM_FLAG)
Checks whether the specified TIM flag is set or not.
#define IS_TIM_GET_FLAG(FLAG)
#define TIM17
Definition: stm32f10x.h:1424
#define TIM_CCMR2_OC4FE
Definition: stm32f4xx.h:10593
#define TIM_CCMR2_OC3FE
Definition: stm32f4xx.h:10579
#define TIM_CCMR2_OC3CE
Definition: stm32f4xx.h:10587
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
#define RCC_APB2Periph_TIM16
uint16_t TIM_ICPolarity
void TIM_SelectOCREFClear(TIM_TypeDef *TIMx, uint16_t TIM_OCReferenceClear)
Selects the OCReference Clear source.
__IO uint32_t CCR3
Definition: stm32f4xx.h:1694
#define TIM_CCMR1_OC2PE
Definition: stm32f4xx.h:10543
#define TIM15
Definition: stm32f10x.h:1422
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Fills each TIM_BDTRInitStruct member with its default value.
#define IS_TIM_BREAK_POLARITY(POLARITY)
uint32_t TIM_GetCapture2(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 2 value.
#define SMCR_ETR_MASK
#define TIM_CR2_OIS2N
Definition: stm32f4xx.h:10451
#define RCC_APB2Periph_TIM15
void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 1N polarity.
#define IS_TIM_OSSI_STATE(STATE)
__IO uint32_t CCR1
Definition: stm32f4xx.h:1692
void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 4 waveform to active or inactive level.
void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource)
Configures the TIMx event to be generate by software.
#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL)
void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measur...
Definition: stm32f4xx.h:706
#define TIM_OSSRState_Disable
#define IS_TIM_TRGO2_SOURCE(SOURCE)
void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 2 polarity.
#define TIM_CR1_UDIS
Definition: stm32f4xx.h:10422
#define IS_TIM_LIST1_PERIPH(PERIPH)
uint16_t TIM_ICPrescaler
void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF2 signal on an external event.
void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode)
Specifies the TIMx Counter Mode to be used.
#define TIM_CR1_URS
Definition: stm32f4xx.h:10423
enum FlagStatus ITStatus
#define IS_TIM_LOCK_LEVEL(LEVEL)
uint16_t TIM_OCPolarity
Definition: stm32f4xx_tim.h:99
#define TIM_CCER_CC4NP
Definition: stm32f4xx.h:10640
void TIM_SetCompare6(TIM_TypeDef *TIMx, uint32_t Compare6)
Sets the TIMx Capture Compare6 Register value.
#define TIM_CCMR1_IC1F
Definition: stm32f4xx.h:10558
void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the specified TIM peripheral.
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
__IO uint16_t DCR
Definition: stm32f4xx.h:1698
#define TIM_CCMR2_OC4CE
Definition: stm32f4xx.h:10601
void TIM_SetCompare3(TIM_TypeDef *TIMx, uint32_t Compare3)
Sets the TIMx Capture Compare3 Register value.
void TIM_OC6Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel6 according to the specified parameters in the TIM_OCInitStruct.
This file contains all the functions prototypes for the RCC firmware library.
#define TIM_TIxExternalCLK1Source_TI2
uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx)
Gets the TIMx Prescaler value.
void TIM_SetCompare4(TIM_TypeDef *TIMx, uint32_t Compare4)
Sets the TIMx Capture Compare4 Register value.
#define TIM6
Definition: stm32f4xx.h:2041
#define TIM_CCMR1_CC2S_0
Definition: stm32f4xx.h:10539
#define IS_TIM_REMAP(TIM_REMAP)
static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI2 as Input.
#define __IO
Definition: core_cm0.h:198
#define TIM_CCER_CC3E
Definition: stm32f4xx.h:10634
#define IS_TIM_OSSR_STATE(STATE)
#define TIM_CCMR1_OC2CE
Definition: stm32f4xx.h:10550
void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF1 signal on an external event.
void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 4 prescaler.
void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 1 Fast feature.
#define TIM_CKD_DIV1
#define IS_TIM_LIST2_PERIPH(PERIPH)
void TIM_UIFRemap(TIM_TypeDef *TIMx, FunctionalState NewState)
Sets or resets the update interrupt flag (UIF)status bit Remapping. when sets, reading TIMx_CNT regis...
#define TIM_CR2_CCPC
Definition: stm32f4xx.h:10438
This file contains all the functions prototypes for the TIM firmware library.
#define IS_TIM_CHANNEL(CHANNEL)
#define TIM_SMCR_ECE
Definition: stm32f4xx.h:10479
#define CCER_CCE_SET
void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables TIMx peripheral Preload register on ARR.
void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 3N polarity.
uint32_t TIM_GetCapture4(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 4 value.
#define TIM_CR2_MMS
Definition: stm32f4xx.h:10442
#define TIM_CCMR2_OC4PE
Definition: stm32f4xx.h:10594
void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIM peripheral Main Outputs.
#define IS_TIM_EXT_FILTER(EXTFILTER)
void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIM peripheral Commutation event.
static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI3 as Input.
#define TIM_Channel_1
#define TIM_CCMR2_OC3M
Definition: stm32f4xx.h:10582
#define TIM_ICPolarity_Rising
void TIM_Break2Cmd(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIM Break2 input.
#define TIM_CR1_DIR
Definition: stm32f4xx.h:10425
#define TIM_CCER_CC2NP
Definition: stm32f4xx.h:10633
#define IS_TIM_OCCLEAR_STATE(STATE)
void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct)
Fills each TIM_ICInitStruct member with its default value.
void TIM_SelectGC5C2(TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIM Group Channel 5 and Channel 2, OC2REFC is the logical AND of OC2REFC and OC5REF...
void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF3 signal on an external event.
#define IS_TIM_CCXN(CCXN)
#define IS_TIM_IC_POLARITY(POLARITY)
#define IS_TIM_DMA_SOURCE(SOURCE)
__IO uint32_t ARR
Definition: stm32f4xx.h:1689
void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode2.
#define TIM_CCER_CC2P
Definition: stm32f4xx.h:10631
void TIM_Break1Config(TIM_TypeDef *TIMx, uint32_t TIM_Break1Polarity, uint8_t TIM_Break1Filter)
Configures the Break1 feature.
#define TIM_CCER_CC3NP
Definition: stm32f4xx.h:10637
void TIM_ClearOC5Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF5 signal on an external event.
void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR1.
#define TIM_CCER_CC2E
Definition: stm32f4xx.h:10630
#define IS_TIM_DMA_LENGTH(LENGTH)
void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource)
Configures the TIMx Update Request Interrupt source.
#define IS_TIM_ALL_PERIPH(PERIPH)
TIM Time Base Init structure definition.
Definition: stm32f4xx_tim.h:55
void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIMx peripheral Capture Compare DMA source.
#define TIM_ICPSC_DIV1
#define TIM_OutputState_Disable
#define TIM_CCER_CC4E
Definition: stm32f4xx.h:10638
void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or Disables the TIMx Update event.
#define TIM_OCMode_Timing
uint16_t TIM_OCNPolarity
void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState)
Enables or disables the specified TIM interrupts.
#define TIM_BDTR_MOE
Definition: stm32f4xx.h:10686
void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 1 prescaler.
void TIM_SetCompare2(TIM_TypeDef *TIMx, uint32_t Compare2)
Sets the TIMx Capture Compare2 Register value.
#define TIM_CR1_ARPE
Definition: stm32f4xx.h:10431
void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
Configures the TIMx Prescaler.
void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
Configures the TIMx Encoder Interface.
#define IS_TIM_LIST7_PERIPH(PERIPH)
#define TIM_SMCR_TS
Definition: stm32f4xx.h:10462
void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 3 Fast feature.
#define TIM_SMCR_MSM
Definition: stm32f4xx.h:10467
#define TIM_CR1_OPM
Definition: stm32f4xx.h:10424
TIM Input Capture Init structure definition.
void TIM_OC6PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR6.
__IO uint16_t BDTR
Definition: stm32f4xx.h:1696
void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct.
uint16_t TIM_BreakPolarity
void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR2.
void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint32_t TIM_OCMode)
Selects the TIM Output Compare Mode.
__IO uint32_t CCR4
Definition: stm32f4xx.h:1695
void TIM_OC5PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR5.
#define TIM_CCMR2_OC4M
Definition: stm32f4xx.h:10596
uint16_t TIM_OutputState
Definition: stm32f4xx_tim.h:89
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
#define IS_TIM_IC_SELECTION(SELECTION)
void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct.
#define TIM_CCMR1_OC1CE
Definition: stm32f4xx.h:10536
void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter)
Configures the TIMx Trigger as External Clock.
#define TIM_CCER_CC1NE
Definition: stm32f4xx.h:10628
#define TIM_CCER_CC2NE
Definition: stm32f4xx.h:10632
void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct.
__IO uint16_t OR
Definition: stm32f4xx.h:1702
uint16_t TIM_ICSelection
#define TIM_CCMR1_IC2F
Definition: stm32f4xx.h:10568
void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 3 polarity.
void TIM_ForcedOC6Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 6 waveform to active or inactive level.
void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Clears the TIMx&#39;s pending flags.
#define TIM_CCMR1_CC2S
Definition: stm32f4xx.h:10538
#define TIM_CR2_TI1S
Definition: stm32f4xx.h:10447
#define IS_TIM_OCNIDLE_STATE(STATE)
__IO uint16_t SR
Definition: stm32f4xx.h:1676
uint16_t TIM_OCNIdleState
#define TIM_CCMR2_IC3PSC
Definition: stm32f4xx.h:10605
#define TIM_CCMR2_OC3PE
Definition: stm32f4xx.h:10580
#define IS_TIM_TRIGGER_SELECTION(SELECTION)
void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 2N polarity.
#define TIM_CR2_OIS2
Definition: stm32f4xx.h:10450
#define TIM_OCPolarity_High
void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
Enables or disables the TIM Capture Compare Channel xN.
#define IS_TIM_IC_FILTER(ICFILTER)
void TIM_ForcedOC5Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 5 waveform to active or inactive level.
#define TIM_BreakPolarity_Low
#define IS_TIM_IT(IT)
#define CCMR_OC24M_MASK
#define TIM_SMCR_SMS
Definition: stm32f4xx.h:10457
void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 4 polarity.
void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
__IO uint16_t CCMR2
Definition: stm32f4xx.h:1682
void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR3.
__IO uint16_t CR2
Definition: stm32f4xx.h:1670
#define IS_TIM_LIST4_PERIPH(PERIPH)
#define TIM_CCMR1_IC1PSC
Definition: stm32f4xx.h:10554
void TIM_OC5Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel5 according to the specified parameters in the TIM_OCInitStruct.
void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint32_t TIM_SlaveMode)
Selects the TIMx Slave Mode.
void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint32_t Autoreload)
Sets the TIMx Autoreload Register value.
#define TIM_OCIdleState_Reset
#define TIM_UpdateSource_Global
#define IS_TIM_LIST6_PERIPH(TIMx)
__IO uint16_t CR1
Definition: stm32f4xx.h:1668
void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 1 polarity.
#define TIM_Break_Disable
#define IS_TIM_OC_POLARITY(POLARITY)
#define IS_TIM_OUTPUT_STATE(STATE)
#define IS_TIM_DMA_BASE(BASE)
#define TIM_CR2_CCUS
Definition: stm32f4xx.h:10439
void TIM_ClearOC6Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF6 signal on an external event.
void TIM_InternalClockConfig(TIM_TypeDef *TIMx)
Configures the TIMx internal Clock.
void TIM_OC5PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 5 polarity.
__IO uint16_t DIER
Definition: stm32f4xx.h:1674
#define TIM_BDTR_BKE
Definition: stm32f4xx.h:10683
#define TIM_CR2_OIS1
Definition: stm32f4xx.h:10448
void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 3 waveform to active or inactive level.
TIM Output Compare Init structure definition.
Definition: stm32f4xx_tim.h:84
#define TIM_CR2_OIS4
Definition: stm32f4xx.h:10454
#define TIM_CR1_CKD
Definition: stm32f4xx.h:10433
void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct)
Fills each TIM_OCInitStruct member with its default value.
void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 2 Fast feature.
#define IS_TIM_MSM_STATE(STATE)
#define TIM_CCMR1_OC1PE
Definition: stm32f4xx.h:10529
#define TIM_CCMR2_IC4PSC
Definition: stm32f4xx.h:10615
#define CCER_CCNE_SET
#define TIM_CCER_CC1P
Definition: stm32f4xx.h:10627
BDTR structure definition.
__IO uint16_t SMCR
Definition: stm32f4xx.h:1672
void TIM_SelectGC5C1(TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIM Group Channel 5 and Channel 1, OC1REFC is the logical AND of OC1REFC and OC5REF...
#define IS_TIM_OCIDLE_STATE(STATE)
#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION)
#define TIM_CounterMode_Up
__IO uint32_t CNT
Definition: stm32f4xx.h:1686
#define IS_TIM_OPM_MODE(MODE)
void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output ena...
void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT)
Clears the TIMx&#39;s interrupt pending bits.
static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI4 as Input.
__IO uint32_t CCR2
Definition: stm32f4xx.h:1693
#define IS_TIM_OCPRELOAD_STATE(STATE)
#define TIM_CCMR1_CC1S_0
Definition: stm32f4xx.h:10525
uint32_t TIM_GetCounter(TIM_TypeDef *TIMx)
Gets the TIMx Counter value.
#define IS_TIM_OCN_POLARITY(POLARITY)
#define IS_TIM_FORCED_ACTION(ACTION)
__IO uint16_t EGR
Definition: stm32f4xx.h:1678
#define TIM_CCMR1_OC2M
Definition: stm32f4xx.h:10545
uint16_t TIM_OCIdleState
#define TIM_CCMR1_IC2PSC
Definition: stm32f4xx.h:10564
#define IS_TIM_EXT_PRESCALER(PRESCALER)
void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 2 prescaler.
#define IS_TIM_LIST8_PERIPH(PERIPH)
void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode)
Selects the TIMx&#39;s One Pulse Mode.
void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
Enables or disables the TIMx&#39;s DMA Requests.
#define TIM7
Definition: stm32f4xx.h:2042
__IO uint16_t RCR
Definition: stm32f4xx.h:1690
#define TIM16
Definition: stm32f10x.h:1423


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19