stm32f30x_spi.c
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1 
122 /* Includes ------------------------------------------------------------------*/
123 #include "stm32f30x_spi.h"
124 #include "stm32f30x_rcc.h"
125 
135 /* Private typedef -----------------------------------------------------------*/
136 /* Private define ------------------------------------------------------------*/
137 /* SPI registers Masks */
138 #define CR1_CLEAR_MASK ((uint16_t)0x3040)
139 #define CR2_LDMA_MASK ((uint16_t)0x9FFF)
140 
141 #define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040)
142 
143 /* Private macro -------------------------------------------------------------*/
144 /* Private variables ---------------------------------------------------------*/
145 /* Private function prototypes -----------------------------------------------*/
146 /* Private functions ---------------------------------------------------------*/
147 
191 {
192  /* Check the parameters */
194 
195  if (SPIx == SPI1)
196  {
197  /* Enable SPI1 reset state */
199  /* Release SPI1 from reset state */
201  }
202  else if (SPIx == SPI2)
203  {
204  /* Enable SPI2 reset state */
206  /* Release SPI2 from reset state */
208  }
209  else
210  {
211  if (SPIx == SPI3)
212  {
213  /* Enable SPI3 reset state */
215  /* Release SPI3 from reset state */
217  }
218  }
219 }
220 
226 void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
227 {
228 /*--------------- Reset SPI init structure parameters values -----------------*/
229  /* Initialize the SPI_Direction member */
231  /* Initialize the SPI_Mode member */
232  SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
233  /* Initialize the SPI_DataSize member */
234  SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
235  /* Initialize the SPI_CPOL member */
236  SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
237  /* Initialize the SPI_CPHA member */
238  SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
239  /* Initialize the SPI_NSS member */
240  SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
241  /* Initialize the SPI_BaudRatePrescaler member */
243  /* Initialize the SPI_FirstBit member */
244  SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
245  /* Initialize the SPI_CRCPolynomial member */
246  SPI_InitStruct->SPI_CRCPolynomial = 7;
247 }
248 
257 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
258 {
259  uint16_t tmpreg = 0;
260 
261  /* check the parameters */
263 
264  /* Check the SPI parameters */
266  assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
267  assert_param(IS_SPI_DATA_SIZE(SPI_InitStruct->SPI_DataSize));
268  assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
269  assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
270  assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
272  assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
274 
275  /* Configuring the SPI in master mode */
276  if(SPI_InitStruct->SPI_Mode == SPI_Mode_Master)
277  {
278 /*---------------------------- SPIx CR1 Configuration ------------------------*/
279  /* Get the SPIx CR1 value */
280  tmpreg = SPIx->CR1;
281  /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
282  tmpreg &= CR1_CLEAR_MASK;
283  /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
284  master/slave mode, CPOL and CPHA */
285  /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
286  /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
287  /* Set LSBFirst bit according to SPI_FirstBit value */
288  /* Set BR bits according to SPI_BaudRatePrescaler value */
289  /* Set CPOL bit according to SPI_CPOL value */
290  /* Set CPHA bit according to SPI_CPHA value */
291  tmpreg |= (uint16_t)((uint16_t)(SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode) |
292  (uint16_t)((uint16_t)(SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA) |
293  (uint16_t)((uint16_t)(SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler) |
294  SPI_InitStruct->SPI_FirstBit)));
295  /* Write to SPIx CR1 */
296  SPIx->CR1 = tmpreg;
297  /*-------------------------Data Size Configuration -----------------------*/
298  /* Get the SPIx CR2 value */
299  tmpreg = SPIx->CR2;
300  /* Clear DS[3:0] bits */
301  tmpreg &= (uint16_t)~SPI_CR2_DS;
302  /* Configure SPIx: Data Size */
303  tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize);
304  /* Write to SPIx CR2 */
305  SPIx->CR2 = tmpreg;
306  }
307  /* Configuring the SPI in slave mode */
308  else
309  {
310 /*---------------------------- Data size Configuration -----------------------*/
311  /* Get the SPIx CR2 value */
312  tmpreg = SPIx->CR2;
313  /* Clear DS[3:0] bits */
314  tmpreg &= (uint16_t)~SPI_CR2_DS;
315  /* Configure SPIx: Data Size */
316  tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize);
317  /* Write to SPIx CR2 */
318  SPIx->CR2 = tmpreg;
319 /*---------------------------- SPIx CR1 Configuration ------------------------*/
320  /* Get the SPIx CR1 value */
321  tmpreg = SPIx->CR1;
322  /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
323  tmpreg &= CR1_CLEAR_MASK;
324  /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
325  master/salve mode, CPOL and CPHA */
326  /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
327  /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
328  /* Set LSBFirst bit according to SPI_FirstBit value */
329  /* Set BR bits according to SPI_BaudRatePrescaler value */
330  /* Set CPOL bit according to SPI_CPOL value */
331  /* Set CPHA bit according to SPI_CPHA value */
332  tmpreg |= (uint16_t)((uint16_t)(SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode) |
333  (uint16_t)((uint16_t)(SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA) |
334  (uint16_t)((uint16_t)(SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler) |
335  SPI_InitStruct->SPI_FirstBit)));
336 
337  /* Write to SPIx CR1 */
338  SPIx->CR1 = tmpreg;
339  }
340 
341  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
342  SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
343 
344 /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
345  /* Write to SPIx CRCPOLY */
346  SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
347 }
348 
354 void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
355 {
356 /*--------------- Reset I2S init structure parameters values -----------------*/
357  /* Initialize the I2S_Mode member */
358  I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
359 
360  /* Initialize the I2S_Standard member */
361  I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
362 
363  /* Initialize the I2S_DataFormat member */
364  I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
365 
366  /* Initialize the I2S_MCLKOutput member */
367  I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
368 
369  /* Initialize the I2S_AudioFreq member */
370  I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
371 
372  /* Initialize the I2S_CPOL member */
373  I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
374 }
375 
391 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
392 {
393  uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
394  uint32_t tmp = 0;
395  RCC_ClocksTypeDef RCC_Clocks;
396  uint32_t sourceclock = 0;
397 
398  /* Check the I2S parameters */
400  assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
401  assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
404  assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
405  assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
406 
407 /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
408  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
409  SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK;
410  SPIx->I2SPR = 0x0002;
411 
412  /* Get the I2SCFGR register value */
413  tmpreg = SPIx->I2SCFGR;
414 
415  /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
416  if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
417  {
418  i2sodd = (uint16_t)0;
419  i2sdiv = (uint16_t)2;
420  }
421  /* If the requested audio frequency is not the default, compute the prescaler */
422  else
423  {
424  /* Check the frame length (For the Prescaler computing) */
425  if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
426  {
427  /* Packet length is 16 bits */
428  packetlength = 1;
429  }
430  else
431  {
432  /* Packet length is 32 bits */
433  packetlength = 2;
434  }
435 
436  /* I2S Clock source is System clock: Get System Clock frequency */
437  RCC_GetClocksFreq(&RCC_Clocks);
438 
439  /* Get the source clock value: based on System Clock value */
440  sourceclock = RCC_Clocks.SYSCLK_Frequency;
441 
442  /* Compute the Real divider depending on the MCLK output state with a floating point */
443  if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
444  {
445  /* MCLK output is enabled */
446  tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
447  }
448  else
449  {
450  /* MCLK output is disabled */
451  tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
452  }
453 
454  /* Remove the floating point */
455  tmp = tmp / 10;
456 
457  /* Check the parity of the divider */
458  i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
459 
460  /* Compute the i2sdiv prescaler */
461  i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
462 
463  /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
464  i2sodd = (uint16_t) (i2sodd << 8);
465  }
466 
467  /* Test if the divider is 1 or 0 or greater than 0xFF */
468  if ((i2sdiv < 2) || (i2sdiv > 0xFF))
469  {
470  /* Set the default values */
471  i2sdiv = 2;
472  i2sodd = 0;
473  }
474 
475  /* Write to SPIx I2SPR register the computed value */
476  SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
477 
478  /* Configure the I2S with the SPI_InitStruct values */
479  tmpreg |= (uint16_t)((uint16_t)(SPI_I2SCFGR_I2SMOD | I2S_InitStruct->I2S_Mode) | \
480  (uint16_t)((uint16_t)((uint16_t)(I2S_InitStruct->I2S_Standard |I2S_InitStruct->I2S_DataFormat) |\
481  I2S_InitStruct->I2S_CPOL)));
482 
483  /* Write to SPIx I2SCFGR */
484  SPIx->I2SCFGR = tmpreg;
485 }
486 
494 void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
495 {
496  /* Check the parameters */
499 
500  if (NewState != DISABLE)
501  {
502  /* Enable the selected SPI peripheral */
503  SPIx->CR1 |= SPI_CR1_SPE;
504  }
505  else
506  {
507  /* Disable the selected SPI peripheral */
508  SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
509  }
510 }
511 
525 {
526  /* Check the parameters */
529 
530  if (NewState != DISABLE)
531  {
532  /* Enable the TI mode for the selected SPI peripheral */
533  SPIx->CR2 |= SPI_CR2_FRF;
534  }
535  else
536  {
537  /* Disable the TI mode for the selected SPI peripheral */
538  SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRF);
539  }
540 }
541 
550 void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
551 {
552  /* Check the parameters */
555  if (NewState != DISABLE)
556  {
557  /* Enable the selected SPI peripheral in I2S mode */
558  SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
559  }
560  else
561  {
562  /* Disable the selected SPI peripheral in I2S mode */
563  SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
564  }
565 }
566 
587 void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
588 {
589  uint16_t tmpreg = 0;
590 
591  /* Check the parameters */
593  assert_param(IS_SPI_DATA_SIZE(SPI_DataSize));
594  /* Read the CR2 register */
595  tmpreg = SPIx->CR2;
596  /* Clear DS[3:0] bits */
597  tmpreg &= (uint16_t)~SPI_CR2_DS;
598  /* Set new DS[3:0] bits value */
599  tmpreg |= SPI_DataSize;
600  SPIx->CR2 = tmpreg;
601 }
602 
614 void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold)
615 {
616  /* Check the parameters */
618  assert_param(IS_SPI_RX_FIFO_THRESHOLD(SPI_RxFIFOThreshold));
619 
620  /* Clear FRXTH bit */
621  SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRXTH);
622 
623  /* Set new FRXTH bit value */
624  SPIx->CR2 |= SPI_RxFIFOThreshold;
625 }
626 
636 void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
637 {
638  /* Check the parameters */
640  assert_param(IS_SPI_DIRECTION(SPI_Direction));
641  if (SPI_Direction == SPI_Direction_Tx)
642  {
643  /* Set the Tx only mode */
644  SPIx->CR1 |= SPI_Direction_Tx;
645  }
646  else
647  {
648  /* Set the Rx only mode */
649  SPIx->CR1 &= SPI_Direction_Rx;
650  }
651 }
652 
664 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
665 {
666  /* Check the parameters */
668  assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
669 
670  if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
671  {
672  /* Set NSS pin internally by software */
673  SPIx->CR1 |= SPI_NSSInternalSoft_Set;
674  }
675  else
676  {
677  /* Reset NSS pin internally by software */
679  }
680 }
681 
701 void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct)
702 {
703  uint16_t tmpreg = 0, tmp = 0;
704 
705  /* Check the I2S parameters */
707  assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
708  assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
710  assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
711 
712 /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
713  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
714  I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK;
715  I2Sxext->I2SPR = 0x0002;
716 
717  /* Get the I2SCFGR register value */
718  tmpreg = I2Sxext->I2SCFGR;
719 
720  /* Get the mode to be configured for the extended I2S */
721  if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx))
722  {
723  tmp = I2S_Mode_SlaveRx;
724  }
725  else
726  {
727  if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx))
728  {
729  tmp = I2S_Mode_SlaveTx;
730  }
731  }
732 
733 
734  /* Configure the I2S with the SPI_InitStruct values */
735  tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \
736  (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
737  (uint16_t)I2S_InitStruct->I2S_CPOL))));
738 
739  /* Write to SPIx I2SCFGR */
740  I2Sxext->I2SCFGR = tmpreg;
741 }
742 
753 {
754  /* Check the parameters */
757  if (NewState != DISABLE)
758  {
759  /* Enable the selected SPI SS output */
760  SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;
761  }
762  else
763  {
764  /* Disable the selected SPI SS output */
765  SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
766  }
767 }
768 
782 {
783  /* Check the parameters */
786 
787  if (NewState != DISABLE)
788  {
789  /* Enable the NSS pulse management mode */
790  SPIx->CR2 |= SPI_CR2_NSSP;
791  }
792  else
793  {
794  /* Disable the NSS pulse management mode */
795  SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_NSSP);
796  }
797 }
798 
830 void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data)
831 {
832  uint32_t spixbase = 0x00;
833 
834  /* Check the parameters */
836 
837  spixbase = (uint32_t)SPIx;
838  spixbase += 0x0C;
839 
840  *(__IO uint8_t *) spixbase = Data;
841 }
842 
850 void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data)
851 {
852  /* Check the parameters */
854 
855  SPIx->DR = (uint16_t)Data;
856 }
857 
864 {
865  uint32_t spixbase = 0x00;
866 
867  /* Check the parameters */
869 
870  spixbase = (uint32_t)SPIx;
871  spixbase += 0x0C;
872 
873  return *(__IO uint8_t *) spixbase;
874 }
875 
883 {
884  /* Check the parameters */
886 
887  return SPIx->DR;
888 }
964 void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength)
965 {
966  /* Check the parameters */
968  assert_param(IS_SPI_CRC_LENGTH(SPI_CRCLength));
969 
970  /* Clear CRCL bit */
971  SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCL);
972 
973  /* Set new CRCL bit value */
974  SPIx->CR1 |= SPI_CRCLength;
975 }
976 
985 {
986  /* Check the parameters */
989 
990  if (NewState != DISABLE)
991  {
992  /* Enable the selected SPI CRC calculation */
993  SPIx->CR1 |= SPI_CR1_CRCEN;
994  }
995  else
996  {
997  /* Disable the selected SPI CRC calculation */
998  SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
999  }
1000 }
1001 
1008 {
1009  /* Check the parameters */
1011 
1012  /* Enable the selected SPI CRC transmission */
1013  SPIx->CR1 |= SPI_CR1_CRCNEXT;
1014 }
1015 
1025 uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
1026 {
1027  uint16_t crcreg = 0;
1028  /* Check the parameters */
1030  assert_param(IS_SPI_CRC(SPI_CRC));
1031 
1032  if (SPI_CRC != SPI_CRC_Rx)
1033  {
1034  /* Get the Tx CRC register */
1035  crcreg = SPIx->TXCRCR;
1036  }
1037  else
1038  {
1039  /* Get the Rx CRC register */
1040  crcreg = SPIx->RXCRCR;
1041  }
1042  /* Return the selected CRC register */
1043  return crcreg;
1044 }
1045 
1052 {
1053  /* Check the parameters */
1055 
1056  /* Return the CRC polynomial register */
1057  return SPIx->CRCPR;
1058 }
1059 
1088 void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
1089 {
1090  /* Check the parameters */
1092  assert_param(IS_FUNCTIONAL_STATE(NewState));
1093  assert_param(IS_SPI_I2S_DMA_REQ(SPI_I2S_DMAReq));
1094 
1095  if (NewState != DISABLE)
1096  {
1097  /* Enable the selected SPI DMA requests */
1098  SPIx->CR2 |= SPI_I2S_DMAReq;
1099  }
1100  else
1101  {
1102  /* Disable the selected SPI DMA requests */
1103  SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
1104  }
1105 }
1106 
1125 void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer)
1126 {
1127  /* Check the parameters */
1129  assert_param(IS_SPI_LAST_DMA_TRANSFER(SPI_LastDMATransfer));
1130 
1131  /* Clear LDMA_TX and LDMA_RX bits */
1132  SPIx->CR2 &= CR2_LDMA_MASK;
1133 
1134  /* Set new LDMA_TX and LDMA_RX bits value */
1135  SPIx->CR2 |= SPI_LastDMATransfer;
1136 }
1137 
1224 void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
1225 {
1226  uint16_t itpos = 0, itmask = 0 ;
1227 
1228  /* Check the parameters */
1230  assert_param(IS_FUNCTIONAL_STATE(NewState));
1231  assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
1232 
1233  /* Get the SPI IT index */
1234  itpos = SPI_I2S_IT >> 4;
1235 
1236  /* Set the IT mask */
1237  itmask = (uint16_t)1 << (uint16_t)itpos;
1238 
1239  if (NewState != DISABLE)
1240  {
1241  /* Enable the selected SPI interrupt */
1242  SPIx->CR2 |= itmask;
1243  }
1244  else
1245  {
1246  /* Disable the selected SPI interrupt */
1247  SPIx->CR2 &= (uint16_t)~itmask;
1248  }
1249 }
1250 
1261 {
1262  /* Get the SPIx Transmission FIFO level bits */
1263  return (uint16_t)((SPIx->SR & SPI_SR_FTLVL));
1264 }
1265 
1276 {
1277  /* Get the SPIx Reception FIFO level bits */
1278  return (uint16_t)((SPIx->SR & SPI_SR_FRLVL));
1279 }
1280 
1298 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
1299 {
1300  FlagStatus bitstatus = RESET;
1301  /* Check the parameters */
1303  assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
1304 
1305  /* Check the status of the specified SPI flag */
1306  if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
1307  {
1308  /* SPI_I2S_FLAG is set */
1309  bitstatus = SET;
1310  }
1311  else
1312  {
1313  /* SPI_I2S_FLAG is reset */
1314  bitstatus = RESET;
1315  }
1316  /* Return the SPI_I2S_FLAG status */
1317  return bitstatus;
1318 }
1319 
1334 void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
1335 {
1336  /* Check the parameters */
1338  assert_param(IS_SPI_CLEAR_FLAG(SPI_I2S_FLAG));
1339 
1340  /* Clear the selected SPI CRC Error (CRCERR) flag */
1341  SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
1342 }
1343 
1358 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
1359 {
1360  ITStatus bitstatus = RESET;
1361  uint16_t itpos = 0, itmask = 0, enablestatus = 0;
1362 
1363  /* Check the parameters */
1365  assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
1366 
1367  /* Get the SPI_I2S_IT index */
1368  itpos = 0x01 << (SPI_I2S_IT & 0x0F);
1369 
1370  /* Get the SPI_I2S_IT IT mask */
1371  itmask = SPI_I2S_IT >> 4;
1372 
1373  /* Set the IT mask */
1374  itmask = 0x01 << itmask;
1375 
1376  /* Get the SPI_I2S_IT enable bit status */
1377  enablestatus = (SPIx->CR2 & itmask) ;
1378 
1379  /* Check the status of the specified SPI interrupt */
1380  if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
1381  {
1382  /* SPI_I2S_IT is set */
1383  bitstatus = SET;
1384  }
1385  else
1386  {
1387  /* SPI_I2S_IT is reset */
1388  bitstatus = RESET;
1389  }
1390  /* Return the SPI_I2S_IT status */
1391  return bitstatus;
1392 }
1393 
1410 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
FlagStatus
Definition: stm32f4xx.h:706
#define I2S_DataFormat_16b
uint16_t SPI_DataSize
Definition: stm32f4xx_spi.h:62
#define I2S_Mode_SlaveTx
#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD)
#define IS_SPI_NSS_INTERNAL(INTERNAL)
void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPIx peripheral according to the specified parameters in the I2S_InitStruct.
uint16_t SPI_Mode
Definition: stm32f4xx_spi.h:59
#define IS_SPI_I2S_GET_IT(IT)
#define SPI2
Definition: stm32f4xx.h:2050
#define IS_SPI_ALL_PERIPH(PERIPH)
FunctionalState
Definition: stm32f4xx.h:708
#define SPI_Mode_Slave
#define IS_SPI_CLEAR_FLAG(FLAG)
#define I2SCFGR_CLEAR_MASK
#define SPI1
Definition: stm32f4xx.h:2087
#define IS_I2S_AUDIO_FREQ(FREQ)
#define SPI3
Definition: stm32f4xx.h:2051
#define SPI_Mode_Master
This file contains all the functions prototypes for the SPI firmware library.
void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct)
Fills each I2S_InitStruct member with its default value.
uint16_t SPI_BaudRatePrescaler
Definition: stm32f4xx_spi.h:75
#define I2S_MCLKOutput_Disable
uint16_t SPI_CPOL
Definition: stm32f4xx_spi.h:65
#define CR2_LDMA_MASK
uint16_t I2S_Standard
Definition: stm32f4xx_spi.h:97
uint16_t SPI_Direction
Definition: stm32f4xx_spi.h:56
#define I2S_Mode_SlaveRx
void SPI_CRCLengthConfig(SPI_TypeDef *SPIx, uint16_t SPI_CRCLength)
Configures the CRC calculation length for the selected SPI.
#define SPI_Direction_Tx
uint16_t SPI_CRCPolynomial
Definition: stm32f4xx_spi.h:84
void SPI_I2S_DeInit(SPI_TypeDef *SPIx)
Deinitializes the SPIx peripheral registers to their default reset values.
void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
Enables or disables the specified SPI/I2S interrupts.
void SPI_TransmitCRC(SPI_TypeDef *SPIx)
Transmits the SPIx CRC value.
__IO uint16_t CRCPR
Definition: stm32f4xx.h:1590
void assert_param(int val)
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
Checks whether the specified SPI/I2S interrupt has occurred or not.
void I2S_FullDuplexConfig(SPI_TypeDef *I2Sxext, I2S_InitTypeDef *I2S_InitStruct)
Configures the full duplex mode for the I2Sx peripheral using its extension I2Sxext according to the ...
__IO uint16_t CR1
Definition: stm32f4xx.h:1582
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
Checks whether the specified SPI flag is set or not.
#define CR1_CLEAR_MASK
#define IS_SPI_DATA_SIZE(SIZE)
uint16_t I2S_Mode
Definition: stm32f4xx_spi.h:94
#define IS_SPI_DIRECTION(DIRECTION)
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
uint8_t SPI_ReceiveData8(SPI_TypeDef *SPIx)
Returns the most recent received data by the SPIx peripheral.
Serial Peripheral Interface.
Definition: stm32f4xx.h:1580
__IO uint16_t RXCRCR
Definition: stm32f4xx.h:1592
#define SPI_CR1_SPE
Definition: stm32f4xx.h:10057
uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef *SPIx)
Returns the most recent received data by the SPIx peripheral.
#define SPI_CR1_CRCNEXT
Definition: stm32f4xx.h:10063
void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
Clears the SPIx CRC Error (CRCERR) flag.
void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the CRC value calculation of the transferred bytes.
Definition: stm32f4xx.h:706
uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC)
Returns the transmit or the receive CRC register value for the specified SPI.
enum FlagStatus ITStatus
#define IS_SPI_FIRST_BIT(BIT)
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
Configures the data size for the selected SPI.
#define SPI_CR1_CRCEN
Definition: stm32f4xx.h:10064
This file contains all the functions prototypes for the RCC firmware library.
#define SPI_NSSInternalSoft_Set
#define IS_I2S_DATA_FORMAT(FORMAT)
#define I2S_CPOL_Low
#define IS_I2S_CPOL(CPOL)
void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the SS output for the selected SPI.
#define __IO
Definition: core_cm0.h:198
uint32_t I2S_AudioFreq
#define I2S_Mode_MasterTx
void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
Enables or disables the SPIx/I2Sx DMA interface.
uint16_t I2S_MCLKOutput
#define SPI_BaudRatePrescaler_2
#define SPI_Direction_Rx
#define IS_I2S_MODE(MODE)
SPI Init structure definition.
Definition: stm32f4xx_spi.h:54
uint16_t SPI_NSS
Definition: stm32f4xx_spi.h:71
#define SPI_CRC_Rx
#define SPI_Direction_2Lines_FullDuplex
#define I2S_Mode_MasterRx
#define IS_SPI_MODE(MODE)
#define SPI_CPHA_1Edge
void SPI_SendData8(SPI_TypeDef *SPIx, uint8_t Data)
Transmits a Data through the SPIx peripheral.
void SPI_LastDMATransferCmd(SPI_TypeDef *SPIx, uint16_t SPI_LastDMATransfer)
Configures the number of data to transfer type(Even/Odd) for the DMA last transfers and for the selec...
#define I2S_Standard_Phillips
__IO uint16_t TXCRCR
Definition: stm32f4xx.h:1594
__IO uint16_t I2SPR
Definition: stm32f4xx.h:1598
#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER)
#define IS_SPI_CPHA(CPHA)
#define SPI_NSSInternalSoft_Reset
#define SPI_CR2_FRF
void SPI_NSSPulseModeCmd(SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the NSS pulse management mode.
#define SPI_DataSize_8b
void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the specified SPI peripheral.
#define IS_SPI_I2S_DMA_REQ(REQ)
void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
Initializes the SPIx peripheral according to the specified parameters in the SPI_InitStruct.
void SPI_I2S_SendData16(SPI_TypeDef *SPIx, uint16_t Data)
Transmits a Data through the SPIx/I2Sx peripheral.
#define IS_I2S_STANDARD(STANDARD)
#define IS_SPI_I2S_GET_FLAG(FLAG)
void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct)
Fills each SPI_InitStruct member with its default value.
void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the specified SPI peripheral (in I2S mode).
#define IS_SPI_23_PERIPH(PERIPH)
void SPI_RxFIFOThresholdConfig(SPI_TypeDef *SPIx, uint16_t SPI_RxFIFOThreshold)
Configures the FIFO reception threshold for the selected SPI.
#define IS_SPI_I2S_CONFIG_IT(IT)
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
Returns the CRC Polynomial register value for the specified SPI.
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
Configures internally by software the NSS pin for the selected SPI.
uint16_t SPI_FirstBit
Definition: stm32f4xx_spi.h:81
#define IS_SPI_CRC_LENGTH(LENGTH)
#define SPI_I2SCFGR_I2SMOD
Definition: stm32f4xx.h:10118
__IO uint16_t SR
Definition: stm32f4xx.h:1586
#define IS_SPI_CPOL(CPOL)
I2S Init structure definition.
Definition: stm32f4xx_spi.h:91
__IO uint16_t I2SCFGR
Definition: stm32f4xx.h:1596
#define SPI_CPOL_Low
uint16_t SPI_CPHA
Definition: stm32f4xx_spi.h:68
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER)
#define SPI_FirstBit_MSB
#define IS_I2S_EXT_PERIPH(PERIPH)
uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef *SPIx)
Returns the current SPIx Reception FIFO filled level.
uint16_t I2S_DataFormat
#define I2S_MCLKOutput_Enable
#define SPI_CR2_SSOE
Definition: stm32f4xx.h:10071
#define IS_SPI_ALL_PERIPH_EXT(PERIPH)
void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks)
Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2.
#define IS_SPI_DIRECTION_MODE(MODE)
#define IS_SPI_NSS(NSS)
__IO uint16_t DR
Definition: stm32f4xx.h:1588
#define SPI_NSS_Hard
void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction)
Selects the data transfer direction in bidirectional mode for the specified SPI.
#define IS_SPI_CRC(CRC)
#define IS_I2S_MCLK_OUTPUT(OUTPUT)
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL)
#define IS_SPI_23_PERIPH_EXT(PERIPH)
#define I2S_AudioFreq_Default
__IO uint16_t CR2
Definition: stm32f4xx.h:1584
#define SPI_I2SCFGR_I2SE
Definition: stm32f4xx.h:10117
void SPI_TIModeCmd(SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the TI Mode.
uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef *SPIx)
Returns the current SPIx Transmission FIFO filled level.


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19