stm32f30x_pwr.c
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1 
35 /* Includes ------------------------------------------------------------------*/
36 #include "stm32f30x_pwr.h"
37 #include "stm32f30x_rcc.h"
38 
48 /* Private typedef -----------------------------------------------------------*/
49 /* Private define ------------------------------------------------------------*/
50 /* --------- PWR registers bit address in the alias region ---------- */
51 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
52 
53 /* --- CR Register ---*/
54 
55 /* Alias word address of DBP bit */
56 #define CR_OFFSET (PWR_OFFSET + 0x00)
57 #define DBP_BitNumber 0x08
58 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
59 
60 /* Alias word address of PVDE bit */
61 #define PVDE_BitNumber 0x04
62 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
63 
64 /* ------------------ PWR registers bit mask ------------------------ */
65 
66 /* CR register bit mask */
67 #define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
68 #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
69 
70 /* Private macro -------------------------------------------------------------*/
71 /* Private variables ---------------------------------------------------------*/
72 /* Private function prototypes -----------------------------------------------*/
73 /* Private functions ---------------------------------------------------------*/
74 
100 void PWR_DeInit(void)
101 {
104 }
105 
115 {
116  /* Check the parameters */
118  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
119 }
120 
158 void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
159 {
160  uint32_t tmpreg = 0;
161 
162  /* Check the parameters */
163  assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
164 
165  tmpreg = PWR->CR;
166 
167  /* Clear PLS[7:5] bits */
168  tmpreg &= CR_PLS_MASK;
169 
170  /* Set PLS[7:5] bits according to PWR_PVDLevel value */
171  tmpreg |= PWR_PVDLevel;
172 
173  /* Store the new value */
174  PWR->CR = tmpreg;
175 }
176 
184 {
185  /* Check the parameters */
187  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
188 }
189 
219 void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)
220 {
221  /* Check the parameters */
222  assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));
224 
225  if (NewState != DISABLE)
226  {
227  /* Enable the EWUPx pin */
228  PWR->CSR |= PWR_WakeUpPin;
229  }
230  else
231  {
232  /* Disable the EWUPx pin */
233  PWR->CSR &= ~PWR_WakeUpPin;
234  }
235 }
236 
351 void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry)
352 {
353  /* Check the parameters */
354  assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
355 
356  /* Clear SLEEPDEEP bit of Cortex System Control Register */
357  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
358 
359  /* Select SLEEP mode entry -------------------------------------------------*/
360  if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)
361  {
362  /* Request Wait For Interrupt */
363  __WFI();
364  }
365  else
366  {
367  /* Request Wait For Event */
368  __WFE();
369  }
370 }
371 
391 void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
392 {
393  uint32_t tmpreg = 0;
394 
395  /* Check the parameters */
396  assert_param(IS_PWR_REGULATOR(PWR_Regulator));
397  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
398 
399  /* Select the regulator state in STOP mode ---------------------------------*/
400  tmpreg = PWR->CR;
401  /* Clear PDDS and LPDSR bits */
402  tmpreg &= CR_DS_MASK;
403 
404  /* Set LPDSR bit according to PWR_Regulator value */
405  tmpreg |= PWR_Regulator;
406 
407  /* Store the new value */
408  PWR->CR = tmpreg;
409 
410  /* Set SLEEPDEEP bit of Cortex System Control Register */
411  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
412 
413  /* Select STOP mode entry --------------------------------------------------*/
414  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
415  {
416  /* Request Wait For Interrupt */
417  __WFI();
418  }
419  else
420  {
421  /* Request Wait For Event */
422  __WFE();
423  }
424  /* Reset SLEEPDEEP bit of Cortex System Control Register */
425  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
426 }
427 
439 {
440  /* Clear Wakeup flag */
441  PWR->CR |= PWR_CR_CWUF;
442 
443  /* Select STANDBY mode */
444  PWR->CR |= PWR_CR_PDDS;
445 
446  /* Set SLEEPDEEP bit of Cortex System Control Register */
447  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
448 
449 /* This option is used to ensure that store operations are completed */
450 #if defined ( __CC_ARM )
451  __force_stores();
452 #endif
453  /* Request Wait For Interrupt */
454  __WFI();
455 }
456 
488 FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
489 {
490  FlagStatus bitstatus = RESET;
491  /* Check the parameters */
492  assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
493 
494  if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
495  {
496  bitstatus = SET;
497  }
498  else
499  {
500  bitstatus = RESET;
501  }
502  /* Return the flag status */
503  return bitstatus;
504 }
505 
514 void PWR_ClearFlag(uint32_t PWR_FLAG)
515 {
516  /* Check the parameters */
517  assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
518 
519  PWR->CR |= PWR_FLAG << 2;
520 }
521 
538 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
FlagStatus
Definition: stm32f4xx.h:706
FunctionalState
Definition: stm32f4xx.h:708
#define SCB_SCR_SLEEPDEEP_Msk
Definition: core_cm0.h:412
#define IS_PWR_CLEAR_FLAG(FLAG)
#define CR_PLS_MASK
Definition: stm32f30x_pwr.c:68
#define IS_PWR_WAKEUP_PIN(PIN)
Definition: stm32f30x_pwr.h:83
void assert_param(int val)
#define PWR_CR_CWUF
Definition: stm32f4xx.h:8354
void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry)
Enters Sleep mode.
#define IS_PWR_PVD_LEVEL(LEVEL)
Definition: stm32f4xx_pwr.h:68
#define CR_DS_MASK
Definition: stm32f30x_pwr.c:67
void PWR_BackupAccessCmd(FunctionalState NewState)
Enables or disables access to the RTC and backup registers.
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).
#define IS_PWR_STOP_ENTRY(ENTRY)
Definition: stm32f4xx_pwr.h:95
#define PWR_SLEEPEntry_WFI
This file contains all the functions prototypes for the PWR firmware library.
void PWR_PVDCmd(FunctionalState NewState)
Enables or disables the Power Voltage Detector(PVD).
Definition: stm32f4xx.h:706
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
Checks whether the specified PWR flag is set or not.
#define SCB
Definition: core_cm0.h:503
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
This file contains all the functions prototypes for the RCC firmware library.
void PWR_EnterSTANDBYMode(void)
Enters STANDBY mode.
#define __IO
Definition: core_cm0.h:198
#define CR_DBP_BB
Definition: stm32f30x_pwr.c:58
void PWR_ClearFlag(uint32_t PWR_FLAG)
Clears the PWR&#39;s pending flags.
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
Enters STOP mode.
#define IS_PWR_SLEEP_ENTRY(ENTRY)
#define PWR
Definition: stm32f4xx.h:2074
void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)
Enables or disables the WakeUp Pin functionality.
void PWR_DeInit(void)
Deinitializes the PWR peripheral registers to their default reset values.
#define PWR_CR_PDDS
Definition: stm32f4xx.h:8353
#define CR_PVDE_BB
Definition: stm32f30x_pwr.c:62
#define IS_PWR_REGULATOR(REGULATOR)
Definition: stm32f4xx_pwr.h:83
#define PWR_STOPEntry_WFI
Definition: stm32f4xx_pwr.h:93
#define IS_PWR_GET_FLAG(FLAG)


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19