stm32f30x_i2c.c
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1 
78 /* Includes ------------------------------------------------------------------*/
79 #include "stm32f30x_i2c.h"
80 #include "stm32f30x_rcc.h"
81 
91 /* Private typedef -----------------------------------------------------------*/
92 /* Private define ------------------------------------------------------------*/
93 
94 #define CR1_CLEAR_MASK ((uint32_t)0x00CFE0FF) /*<! I2C CR1 clear register Mask */
95 #define CR2_CLEAR_MASK ((uint32_t)0x07FF7FFF) /*<! I2C CR2 clear register Mask */
96 #define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! I2C TIMING clear register Mask */
97 #define ERROR_IT_MASK ((uint32_t)0x00003F00) /*<! I2C Error interrupt register Mask */
98 #define TC_IT_MASK ((uint32_t)0x000000C0) /*<! I2C TC interrupt register Mask */
99 
100 /* Private macro -------------------------------------------------------------*/
101 /* Private variables ---------------------------------------------------------*/
102 /* Private function prototypes -----------------------------------------------*/
103 /* Private functions ---------------------------------------------------------*/
104 
146 {
147  /* Check the parameters */
149 
150  if (I2Cx == I2C1)
151  {
152  /* Enable I2C1 reset state */
154  /* Release I2C1 from reset state */
156  }
157  else
158  {
159  /* Enable I2C2 reset state */
161  /* Release I2C2 from reset state */
163  }
164 }
165 
174 void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
175 {
176  uint32_t tmpreg = 0;
177 
178  /* Check the parameters */
182  assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
184  assert_param(IS_I2C_ACK(I2C_InitStruct->I2C_Ack));
186 
187  /* Disable I2Cx Peripheral */
188  I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
189 
190  /*---------------------------- I2Cx FILTERS Configuration ------------------*/
191  /* Get the I2Cx CR1 value */
192  tmpreg = I2Cx->CR1;
193  /* Clear I2Cx CR1 register */
194  tmpreg &= CR1_CLEAR_MASK;
195  /* Configure I2Cx: analog and digital filter */
196  /* Set ANFOFF bit according to I2C_AnalogFilter value */
197  /* Set DFN bits according to I2C_DigitalFilter value */
198  tmpreg |= (uint32_t)I2C_InitStruct->I2C_AnalogFilter |(I2C_InitStruct->I2C_DigitalFilter << 8);
199 
200  /* Write to I2Cx CR1 */
201  I2Cx->CR1 = tmpreg;
202 
203  /*---------------------------- I2Cx TIMING Configuration -------------------*/
204  /* Configure I2Cx: Timing */
205  /* Set TIMINGR bits according to I2C_Timing */
206  /* Write to I2Cx TIMING */
207  I2Cx->TIMINGR = I2C_InitStruct->I2C_Timing & TIMING_CLEAR_MASK;
208 
209  /* Enable I2Cx Peripheral */
210  I2Cx->CR1 |= I2C_CR1_PE;
211 
212  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
213  /* Clear tmpreg local variable */
214  tmpreg = 0;
215  /* Clear OAR1 register */
216  I2Cx->OAR1 = (uint32_t)tmpreg;
217  /* Clear OAR2 register */
218  I2Cx->OAR2 = (uint32_t)tmpreg;
219  /* Configure I2Cx: Own Address1 and acknowledged address */
220  /* Set OA1MODE bit according to I2C_AcknowledgedAddress value */
221  /* Set OA1 bits according to I2C_OwnAddress1 value */
222  tmpreg = (uint32_t)((uint32_t)I2C_InitStruct->I2C_AcknowledgedAddress | \
223  (uint32_t)I2C_InitStruct->I2C_OwnAddress1);
224  /* Write to I2Cx OAR1 */
225  I2Cx->OAR1 = tmpreg;
226  /* Enable Own Address1 acknowledgement */
227  I2Cx->OAR1 |= I2C_OAR1_OA1EN;
228 
229  /*---------------------------- I2Cx MODE Configuration ---------------------*/
230  /* Configure I2Cx: mode */
231  /* Set SMBDEN and SMBHEN bits according to I2C_Mode value */
232  tmpreg = I2C_InitStruct->I2C_Mode;
233  /* Write to I2Cx CR1 */
234  I2Cx->CR1 |= tmpreg;
235 
236  /*---------------------------- I2Cx ACK Configuration ----------------------*/
237  /* Get the I2Cx CR2 value */
238  tmpreg = I2Cx->CR2;
239  /* Clear I2Cx CR2 register */
240  tmpreg &= CR2_CLEAR_MASK;
241  /* Configure I2Cx: acknowledgement */
242  /* Set NACK bit according to I2C_Ack value */
243  tmpreg |= I2C_InitStruct->I2C_Ack;
244  /* Write to I2Cx CR2 */
245  I2Cx->CR2 = tmpreg;
246 }
247 
253 void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
254 {
255  /*---------------- Reset I2C init structure parameters values --------------*/
256  /* Initialize the I2C_Timing member */
257  I2C_InitStruct->I2C_Timing = 0;
258  /* Initialize the I2C_AnalogFilter member */
259  I2C_InitStruct->I2C_AnalogFilter = I2C_AnalogFilter_Enable;
260  /* Initialize the I2C_DigitalFilter member */
261  I2C_InitStruct->I2C_DigitalFilter = 0;
262  /* Initialize the I2C_Mode member */
263  I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
264  /* Initialize the I2C_OwnAddress1 member */
265  I2C_InitStruct->I2C_OwnAddress1 = 0;
266  /* Initialize the I2C_Ack member */
267  I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
268  /* Initialize the I2C_AcknowledgedAddress member */
270 }
271 
280 {
281  /* Check the parameters */
284  if (NewState != DISABLE)
285  {
286  /* Enable the selected I2C peripheral */
287  I2Cx->CR1 |= I2C_CR1_PE;
288  }
289  else
290  {
291  /* Disable the selected I2C peripheral */
292  I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
293  }
294 }
295 
296 
303 {
304  /* Check the parameters */
306 
307  /* Disable peripheral */
308  I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
309 
310  /* Perform a dummy read to delay the disable of peripheral for minimum
311  3 APB clock cycles to perform the software reset functionality */
312  *(__IO uint32_t *)(uint32_t)I2Cx;
313 
314  /* Enable peripheral */
315  I2Cx->CR1 |= I2C_CR1_PE;
316 }
317 
334 void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState)
335 {
336  /* Check the parameters */
340 
341  if (NewState != DISABLE)
342  {
343  /* Enable the selected I2C interrupts */
344  I2Cx->CR1 |= I2C_IT;
345  }
346  else
347  {
348  /* Disable the selected I2C interrupts */
349  I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_IT);
350  }
351 }
352 
361 {
362  /* Check the parameters */
365 
366  if (NewState != DISABLE)
367  {
368  /* Enable clock stretching */
369  I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_NOSTRETCH);
370  }
371  else
372  {
373  /* Disable clock stretching */
374  I2Cx->CR1 |= I2C_CR1_NOSTRETCH;
375  }
376 }
377 
386 {
387  /* Check the parameters */
390 
391  if (NewState != DISABLE)
392  {
393  /* Enable wakeup from stop mode */
394  I2Cx->CR1 |= I2C_CR1_WUPEN;
395  }
396  else
397  {
398  /* Disable wakeup from stop mode */
399  I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_WUPEN);
400  }
401 }
402 
411 {
412  /* Check the parameters */
415 
416  if (NewState != DISABLE)
417  {
418  /* Enable own address 2 */
419  I2Cx->OAR2 |= I2C_OAR2_OA2EN;
420  }
421  else
422  {
423  /* Disable own address 2 */
424  I2Cx->OAR2 &= (uint32_t)~((uint32_t)I2C_OAR2_OA2EN);
425  }
426 }
427 
444 void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask)
445 {
446  uint32_t tmpreg = 0;
447 
448  /* Check the parameters */
452 
453  /* Get the old register value */
454  tmpreg = I2Cx->OAR2;
455 
456  /* Reset I2Cx OA2 bit [7:1] and OA2MSK bit [1:0] */
457  tmpreg &= (uint32_t)~((uint32_t)(I2C_OAR2_OA2 | I2C_OAR2_OA2MSK));
458 
459  /* Set I2Cx SADD */
460  tmpreg |= (uint32_t)(((uint32_t)Address & I2C_OAR2_OA2) | \
461  (((uint32_t)Mask << 8) & I2C_OAR2_OA2MSK)) ;
462 
463  /* Store the new register value */
464  I2Cx->OAR2 = tmpreg;
465 }
466 
475 {
476  /* Check the parameters */
479 
480  if (NewState != DISABLE)
481  {
482  /* Enable general call mode */
483  I2Cx->CR1 |= I2C_CR1_GCEN;
484  }
485  else
486  {
487  /* Disable general call mode */
488  I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_GCEN);
489  }
490 }
491 
500 {
501  /* Check the parameters */
504 
505  if (NewState != DISABLE)
506  {
507  /* Enable slave byte control */
508  I2Cx->CR1 |= I2C_CR1_SBC;
509  }
510  else
511  {
512  /* Disable slave byte control */
513  I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_SBC);
514  }
515 }
516 
524 void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address)
525 {
526  uint32_t tmpreg = 0;
527 
528  /* Check the parameters */
531 
532  /* Get the old register value */
533  tmpreg = I2Cx->CR2;
534 
535  /* Reset I2Cx SADD bit [9:0] */
536  tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_SADD);
537 
538  /* Set I2Cx SADD */
539  tmpreg |= (uint32_t)((uint32_t)Address & I2C_CR2_SADD);
540 
541  /* Store the new register value */
542  I2Cx->CR2 = tmpreg;
543 }
544 
554 {
555  /* Check the parameters */
558 
559  if (NewState != DISABLE)
560  {
561  /* Enable 10-bit addressing mode */
562  I2Cx->CR2 |= I2C_CR2_ADD10;
563  }
564  else
565  {
566  /* Disable 10-bit addressing mode */
567  I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_ADD10);
568  }
569 }
570 
619 {
620  /* Check the parameters */
623 
624  if (NewState != DISABLE)
625  {
626  /* Enable Auto end mode */
627  I2Cx->CR2 |= I2C_CR2_AUTOEND;
628  }
629  else
630  {
631  /* Disable Auto end mode */
632  I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_AUTOEND);
633  }
634 }
635 
644 {
645  /* Check the parameters */
648 
649  if (NewState != DISABLE)
650  {
651  /* Enable Auto Reload mode */
652  I2Cx->CR2 |= I2C_CR2_RELOAD;
653  }
654  else
655  {
656  /* Disable Auto Reload mode */
657  I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RELOAD);
658  }
659 }
660 
667 void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes)
668 {
669  uint32_t tmpreg = 0;
670 
671  /* Check the parameters */
673 
674  /* Get the old register value */
675  tmpreg = I2Cx->CR2;
676 
677  /* Reset I2Cx Nbytes bit [7:0] */
678  tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_NBYTES);
679 
680  /* Set I2Cx Nbytes */
681  tmpreg |= (uint32_t)(((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES);
682 
683  /* Store the new register value */
684  I2Cx->CR2 = tmpreg;
685 }
686 
696 void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction)
697 {
698 /* Check the parameters */
700  assert_param(IS_I2C_DIRECTION(I2C_Direction));
701 
702  /* Test on the direction to set/reset the read/write bit */
703  if (I2C_Direction == I2C_Direction_Transmitter)
704  {
705  /* Request a write Transfer */
706  I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RD_WRN);
707  }
708  else
709  {
710  /* Request a read Transfer */
711  I2Cx->CR2 |= I2C_CR2_RD_WRN;
712  }
713 }
714 
723 {
724  /* Check the parameters */
727 
728  if (NewState != DISABLE)
729  {
730  /* Generate a START condition */
731  I2Cx->CR2 |= I2C_CR2_START;
732  }
733  else
734  {
735  /* Disable the START condition generation */
736  I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_START);
737  }
738 }
739 
748 {
749  /* Check the parameters */
752 
753  if (NewState != DISABLE)
754  {
755  /* Generate a STOP condition */
756  I2Cx->CR2 |= I2C_CR2_STOP;
757  }
758  else
759  {
760  /* Disable the STOP condition generation */
761  I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_STOP);
762  }
763 }
764 
775 {
776  /* Check the parameters */
779 
780  if (NewState != DISABLE)
781  {
782  /* Enable 10-bit header only mode */
783  I2Cx->CR2 |= I2C_CR2_HEAD10R;
784  }
785  else
786  {
787  /* Disable 10-bit header only mode */
788  I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_HEAD10R);
789  }
790 }
791 
800 {
801  /* Check the parameters */
804 
805  if (NewState != DISABLE)
806  {
807  /* Enable ACK generation */
808  I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_NACK);
809  }
810  else
811  {
812  /* Enable NACK generation */
813  I2Cx->CR2 |= I2C_CR2_NACK;
814  }
815 }
816 
823 {
824  /* Check the parameters */
826 
827  /* Return the slave matched address in the SR1 register */
828  return (uint8_t)(((uint32_t)I2Cx->ISR & I2C_ISR_ADDCODE) >> 16) ;
829 }
830 
837 {
838  uint32_t tmpreg = 0;
839  uint16_t direction = 0;
840 
841  /* Check the parameters */
843 
844  /* Return the slave matched address in the SR1 register */
845  tmpreg = (uint32_t)(I2Cx->ISR & I2C_ISR_DIR);
846 
847  /* If write transfer is requested */
848  if (tmpreg == 0)
849  {
850  /* write transfer is requested */
851  direction = I2C_Direction_Transmitter;
852  }
853  else
854  {
855  /* Read transfer is requested */
856  direction = I2C_Direction_Receiver;
857  }
858  return direction;
859 }
860 
880 void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode)
881 {
882  uint32_t tmpreg = 0;
883 
884  /* Check the parameters */
887  assert_param(IS_RELOAD_END_MODE(ReloadEndMode));
888  assert_param(IS_START_STOP_MODE(StartStopMode));
889 
890  /* Get the CR2 register value */
891  tmpreg = I2Cx->CR2;
892 
893  /* clear tmpreg specific bits */
894  tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
895 
896  /* update tmpreg */
897  tmpreg |= (uint32_t)(((uint32_t)Address & I2C_CR2_SADD) | (((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES) | \
898  (uint32_t)ReloadEndMode | (uint32_t)StartStopMode);
899 
900  /* update CR2 register */
901  I2Cx->CR2 = tmpreg;
902 }
903 
952 {
953  /* Check the parameters */
956 
957  if (NewState != DISABLE)
958  {
959  /* Enable SMBus alert */
960  I2Cx->CR1 |= I2C_CR1_ALERTEN;
961  }
962  else
963  {
964  /* Disable SMBus alert */
965  I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_ALERTEN);
966  }
967 }
968 
977 {
978  /* Check the parameters */
981 
982  if (NewState != DISABLE)
983  {
984  /* Enable Clock Timeout */
985  I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIMOUTEN;
986  }
987  else
988  {
989  /* Disable Clock Timeout */
990  I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMOUTEN);
991  }
992 }
993 
1002 {
1003  /* Check the parameters */
1005  assert_param(IS_FUNCTIONAL_STATE(NewState));
1006 
1007  if (NewState != DISABLE)
1008  {
1009  /* Enable Clock Timeout */
1010  I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TEXTEN;
1011  }
1012  else
1013  {
1014  /* Disable Clock Timeout */
1015  I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TEXTEN);
1016  }
1017 }
1018 
1028 {
1029  /* Check the parameters */
1031  assert_param(IS_FUNCTIONAL_STATE(NewState));
1032 
1033  if (NewState != DISABLE)
1034  {
1035  /* Enable Clock Timeout */
1036  I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIDLE;
1037  }
1038  else
1039  {
1040  /* Disable Clock Timeout */
1041  I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIDLE);
1042  }
1043 }
1044 
1052 void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
1053 {
1054  uint32_t tmpreg = 0;
1055 
1056  /* Check the parameters */
1058  assert_param(IS_I2C_TIMEOUT(Timeout));
1059 
1060  /* Get the old register value */
1061  tmpreg = I2Cx->TIMEOUTR;
1062 
1063  /* Reset I2Cx TIMEOUTA bit [11:0] */
1064  tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTA);
1065 
1066  /* Set I2Cx TIMEOUTA */
1067  tmpreg |= (uint32_t)((uint32_t)Timeout & I2C_TIMEOUTR_TIMEOUTA) ;
1068 
1069  /* Store the new register value */
1070  I2Cx->TIMEOUTR = tmpreg;
1071 }
1072 
1079 void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
1080 {
1081  uint32_t tmpreg = 0;
1082 
1083  /* Check the parameters */
1085  assert_param(IS_I2C_TIMEOUT(Timeout));
1086 
1087  /* Get the old register value */
1088  tmpreg = I2Cx->TIMEOUTR;
1089 
1090  /* Reset I2Cx TIMEOUTB bit [11:0] */
1091  tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTB);
1092 
1093  /* Set I2Cx TIMEOUTB */
1094  tmpreg |= (uint32_t)(((uint32_t)Timeout << 16) & I2C_TIMEOUTR_TIMEOUTB) ;
1095 
1096  /* Store the new register value */
1097  I2Cx->TIMEOUTR = tmpreg;
1098 }
1099 
1108 {
1109  /* Check the parameters */
1111  assert_param(IS_FUNCTIONAL_STATE(NewState));
1112 
1113  if (NewState != DISABLE)
1114  {
1115  /* Enable PEC calculation */
1116  I2Cx->CR1 |= I2C_CR1_PECEN;
1117  }
1118  else
1119  {
1120  /* Disable PEC calculation */
1121  I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PECEN);
1122  }
1123 }
1124 
1133 {
1134  /* Check the parameters */
1136  assert_param(IS_FUNCTIONAL_STATE(NewState));
1137 
1138  if (NewState != DISABLE)
1139  {
1140  /* Enable PEC transmission/reception request */
1141  I2Cx->CR1 |= I2C_CR2_PECBYTE;
1142  }
1143  else
1144  {
1145  /* Disable PEC transmission/reception request */
1146  I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR2_PECBYTE);
1147  }
1148 }
1149 
1156 {
1157  /* Check the parameters */
1159 
1160  /* Return the slave matched address in the SR1 register */
1161  return (uint8_t)((uint32_t)I2Cx->PECR & I2C_PECR_PEC);
1162 }
1163 
1201 uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
1202 {
1203  __IO uint32_t tmp = 0;
1204 
1205  /* Check the parameters */
1207  assert_param(IS_I2C_REGISTER(I2C_Register));
1208 
1209  tmp = (uint32_t)I2Cx;
1210  tmp += I2C_Register;
1211 
1212  /* Return the selected register value */
1213  return (*(__IO uint32_t *) tmp);
1214 }
1215 
1244 void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
1245 {
1246  /* Check the parameters */
1248 
1249  /* Write in the DR register the data to be sent */
1250  I2Cx->TXDR = (uint8_t)Data;
1251 }
1252 
1259 {
1260  /* Check the parameters */
1262 
1263  /* Return the data in the DR register */
1264  return (uint8_t)I2Cx->RXDR;
1265 }
1266 
1301 void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState)
1302 {
1303  /* Check the parameters */
1305  assert_param(IS_FUNCTIONAL_STATE(NewState));
1306  assert_param(IS_I2C_DMA_REQ(I2C_DMAReq));
1307 
1308  if (NewState != DISABLE)
1309  {
1310  /* Enable the selected I2C DMA requests */
1311  I2Cx->CR1 |= I2C_DMAReq;
1312  }
1313  else
1314  {
1315  /* Disable the selected I2C DMA requests */
1316  I2Cx->CR1 &= (uint32_t)~I2C_DMAReq;
1317  }
1318 }
1422 {
1423  uint32_t tmpreg = 0;
1424  FlagStatus bitstatus = RESET;
1425 
1426  /* Check the parameters */
1428  assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
1429 
1430  /* Get the ISR register value */
1431  tmpreg = I2Cx->ISR;
1432 
1433  /* Get flag status */
1434  tmpreg &= I2C_FLAG;
1435 
1436  if(tmpreg != 0)
1437  {
1438  /* I2C_FLAG is set */
1439  bitstatus = SET;
1440  }
1441  else
1442  {
1443  /* I2C_FLAG is reset */
1444  bitstatus = RESET;
1445  }
1446  return bitstatus;
1447 }
1448 
1465 void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
1466 {
1467  /* Check the parameters */
1469  assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
1470 
1471  /* Clear the selected flag */
1472  I2Cx->ICR = I2C_FLAG;
1473  }
1474 
1496 {
1497  uint32_t tmpreg = 0;
1498  ITStatus bitstatus = RESET;
1499  uint32_t enablestatus = 0;
1500 
1501  /* Check the parameters */
1503  assert_param(IS_I2C_GET_IT(I2C_IT));
1504 
1505  /* Check if the interrupt source is enabled or not */
1506  /* If Error interrupt */
1507  if((uint32_t)(I2C_IT & ERROR_IT_MASK))
1508  {
1509  enablestatus = (uint32_t)((I2C_CR1_ERRIE) & (I2Cx->CR1));
1510  }
1511  /* If TC interrupt */
1512  else if((uint32_t)(I2C_IT & TC_IT_MASK))
1513  {
1514  enablestatus = (uint32_t)((I2C_CR1_TCIE) & (I2Cx->CR1));
1515  }
1516  else
1517  {
1518  enablestatus = (uint32_t)((I2C_IT) & (I2Cx->CR1));
1519  }
1520 
1521  /* Get the ISR register value */
1522  tmpreg = I2Cx->ISR;
1523 
1524  /* Get flag status */
1525  tmpreg &= I2C_IT;
1526 
1527  /* Check the status of the specified I2C flag */
1528  if((tmpreg != RESET) && enablestatus)
1529  {
1530  /* I2C_IT is set */
1531  bitstatus = SET;
1532  }
1533  else
1534  {
1535  /* I2C_IT is reset */
1536  bitstatus = RESET;
1537  }
1538 
1539  /* Return the I2C_IT status */
1540  return bitstatus;
1541 }
1542 
1559 void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
1560 {
1561  /* Check the parameters */
1563  assert_param(IS_I2C_CLEAR_IT(I2C_IT));
1564 
1565  /* Clear the selected flag */
1566  I2Cx->ICR = I2C_IT;
1567 }
1568 
1585 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
#define IS_I2C_SLAVE_ADDRESS(ADDRESS)
#define IS_I2C_ACK(ACK)
FlagStatus
Definition: stm32f4xx.h:706
uint16_t I2C_Ack
Definition: stm32f4xx_i2c.h:68
#define IS_I2C_CLEAR_FLAG(FLAG)
void I2C_ClockTimeoutCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables I2C Clock Timeout (SCL Timeout detection).
#define I2C_CR1_PE
Definition: stm32f4xx.h:6789
void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables I2C Extended Clock Timeout (SCL cumulative Timeout detection).
#define IS_I2C_CONFIG_IT(IT)
FunctionalState
Definition: stm32f4xx.h:708
#define IS_I2C_ANALOG_FILTER(FILTER)
Definition: stm32f30x_i2c.h:96
void I2C_MasterRequestConfig(I2C_TypeDef *I2Cx, uint16_t I2C_Direction)
Configures the type of transfer request for the master.
uint16_t I2C_AcknowledgedAddress
Definition: stm32f4xx_i2c.h:71
#define IS_I2C_REGISTER(REGISTER)
void I2C_TransferHandling(I2C_TypeDef *I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set)...
uint16_t I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
Returns the I2C slave received request.
#define IS_I2C_TIMEOUT(TIMEOUT)
#define I2C_Mode_I2C
void I2C_ITConfig(I2C_TypeDef *I2Cx, uint32_t I2C_IT, FunctionalState NewState)
Enables or disables the specified I2C interrupts.
#define IS_I2C_DMA_REQ(REQ)
void I2C_DMACmd(I2C_TypeDef *I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState)
Enables or disables the I2C DMA interface.
__IO uint16_t CR2
Definition: stm32f4xx.h:1324
#define IS_I2C_OWN_ADDRESS2(ADDRESS2)
void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2C communication Acknowledge.
void I2C_NumberOfBytesConfig(I2C_TypeDef *I2Cx, uint8_t Number_Bytes)
Configures the number of bytes to be transmitted/received.
__IO uint16_t OAR1
Definition: stm32f4xx.h:1326
void I2C_AutoEndCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the I2C automatic end mode (stop condition is automatically sent when nbytes data...
uint16_t I2C_OwnAddress1
Definition: stm32f4xx_i2c.h:65
void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication START condition.
void assert_param(int val)
void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the I2C general call mode.
static I2C_TypeDef * I2Cx
Definition: drv_i2c.c:64
uint32_t I2C_DigitalFilter
Definition: stm32f30x_i2c.h:63
FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
Checks whether the specified I2C flag is set or not.
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
#define IS_RELOAD_END_MODE(MODE)
#define CR1_CLEAR_MASK
Definition: stm32f30x_i2c.c:94
#define I2C_Direction_Transmitter
#define I2C_CR1_NOSTRETCH
Definition: stm32f4xx.h:6795
#define I2C_AcknowledgedAddress_7bit
#define I2C_AnalogFilter_Enable
Definition: stm32f30x_i2c.h:93
Definition: stm32f4xx.h:706
void I2C_DeInit(I2C_TypeDef *I2Cx)
Deinitializes the I2Cx peripheral registers to their default reset values.
enum FlagStatus ITStatus
void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint16_t Address, uint8_t Mask)
Configures the I2C slave own address 2 and mask.
void I2C_StopModeCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables I2C wakeup from stop mode.
#define IS_I2C_DIGITAL_FILTER(FILTER)
Definition: stm32f4xx_i2c.h:90
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Clears the I2Cx&#39;s interrupt pending bits.
This file contains all the functions prototypes for the RCC firmware library.
void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct)
Fills each I2C_InitStruct member with its default value.
#define __IO
Definition: core_cm0.h:198
void I2C_IdleClockTimeoutCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables I2C Idle Clock Timeout (Bus idle SCL and SDA high detection). ...
ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Checks whether the specified I2C interrupt has occurred or not.
#define ERROR_IT_MASK
Definition: stm32f30x_i2c.c:97
#define IS_I2C_OWN_ADDRESS1(ADDRESS1)
#define TIMING_CLEAR_MASK
Definition: stm32f30x_i2c.c:96
void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C peripheral.
void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables I2C PEC calculation.
#define IS_I2C_MODE(MODE)
void I2C_ReloadCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the I2C nbytes reload mode.
#define IS_I2C_DIRECTION(DIRECTION)
uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx)
Returns the I2C PEC.
void I2C_SlaveAddressConfig(I2C_TypeDef *I2Cx, uint16_t Address)
Configures the slave address to be transmitted after start generation.
void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
Initializes the I2Cx peripheral according to the specified parameters in the I2C_InitStruct.
void I2C_10BitAddressHeaderCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the I2C 10-bit header only mode with read direction.
uint8_t I2C_GetAddressMatched(I2C_TypeDef *I2Cx)
Returns the I2C slave matched address .
#define IS_I2C_OWN_ADDRESS2_MASK(MASK)
void I2C_TimeoutAConfig(I2C_TypeDef *I2Cx, uint16_t Timeout)
Configures the I2C Bus Timeout A (SCL Timeout when TIDLE = 0 or Bus idle SCL and SDA high when TIDLE ...
This file contains all the functions prototypes for the I2C firmware library.
uint32_t I2C_Timing
Definition: stm32f30x_i2c.h:56
__IO uint16_t OAR2
Definition: stm32f4xx.h:1328
void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the I2C own address 2.
I2C Init structure definition.
Definition: stm32f4xx_i2c.h:54
#define CR2_CLEAR_MASK
Definition: stm32f30x_i2c.c:95
void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the I2C Clock stretching.
void I2C_SlaveByteControlCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the I2C slave byte control.
#define IS_I2C_GET_IT(IT)
void I2C_TimeoutBConfig(I2C_TypeDef *I2Cx, uint16_t Timeout)
Configures the I2C Bus Timeout B (SCL cumulative Timeout).
#define IS_I2C_CLEAR_IT(IT)
void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication STOP condition.
void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
Clears the I2Cx&#39;s pending flags.
void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data)
Sends a data byte through the I2Cx peripheral.
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS)
#define IS_START_STOP_MODE(MODE)
#define IS_I2C_GET_FLAG(FLAG)
Inter-integrated Circuit Interface.
Definition: stm32f4xx.h:1320
uint32_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register)
Reads the specified I2C register and returns its value.
#define I2C_Direction_Receiver
__IO uint16_t CR1
Definition: stm32f4xx.h:1322
#define TC_IT_MASK
Definition: stm32f30x_i2c.c:98
uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx)
Returns the most recent received data by the I2Cx peripheral.
#define I2C1
Definition: stm32f4xx.h:2060
uint32_t I2C_AnalogFilter
Definition: stm32f30x_i2c.h:60
uint16_t I2C_Mode
Definition: stm32f4xx_i2c.h:59
void I2C_10BitAddressingModeCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the I2C 10-bit addressing mode for the master.
void I2C_SMBusAlertCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables I2C SMBus alert.
void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx)
Enables or disables the specified I2C software reset.
#define I2C_Ack_Disable
void I2C_PECRequestCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables I2C PEC transmission/reception request.
#define IS_I2C_ALL_PERIPH(PERIPH)
Definition: stm32f4xx_i2c.h:82


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19