stm32f30x_hrtim.c
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1 
124 /* Includes ------------------------------------------------------------------*/
125 #include "stm32f30x_hrtim.h"
126 
136 /* Private typedef -----------------------------------------------------------*/
137 /* Private define ------------------------------------------------------------*/
138 #define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
139  HRTIM_FLTR_FLT2EN |\
140  HRTIM_FLTR_FLT3EN |\
141  HRTIM_FLTR_FLT4EN | \
142  HRTIM_FLTR_FLT5EN)
143 
144 #define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER |\
145  HRTIM_TIMUPDATETRIGGER_TIMER_A |\
146  HRTIM_TIMUPDATETRIGGER_TIMER_B |\
147  HRTIM_TIMUPDATETRIGGER_TIMER_C |\
148  HRTIM_TIMUPDATETRIGGER_TIMER_D |\
149  HRTIM_TIMUPDATETRIGGER_TIMER_E)
150 
151 #define HRTIM_TIM_OFFSET (uint32_t)0x00000080
152 /* Private macro -------------------------------------------------------------*/
153 /* Private variables ---------------------------------------------------------*/
154 static uint32_t TimerIdxToTimerId[] =
155 {
162 };
163 
164 /* Private function prototypes -----------------------------------------------*/
165 /* Private functions ---------------------------------------------------------*/
166 static void HRTIM_MasterBase_Config(HRTIM_TypeDef* HRTIMx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruc);
167 static void HRTIM_TimingUnitBase_Config(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
168 static void HRTIM_MasterWaveform_Config(HRTIM_TypeDef * HRTIMx, HRTIM_TimerInitTypeDef * TimerInit);
169 static void HRTIM_TimingUnitWaveform_Config(HRTIM_TypeDef * HRTIMx,
170  uint32_t TimerIdx,
171  HRTIM_TimerInitTypeDef * TimerInit);
172 static void HRTIM_CompareUnitConfig(HRTIM_TypeDef * HRTIMx,
173  uint32_t TimerIdx,
174  uint32_t CompareUnit,
175  HRTIM_CompareCfgTypeDef * CompareCfg);
176 static void HRTIM_CaptureUnitConfig(HRTIM_TypeDef * HRTIMx,
177  uint32_t TimerIdx,
178  uint32_t CaptureUnit,
179  uint32_t Event);
180 static void HRTIM_OutputConfig(HRTIM_TypeDef * HRTIMx,
181  uint32_t TimerIdx,
182  uint32_t Output,
183  HRTIM_OutputCfgTypeDef * OutputCfg);
184 static void HRTIM_ExternalEventConfig(HRTIM_TypeDef * HRTIMx,
185  uint32_t Event,
186  HRTIM_EventCfgTypeDef * EventCfg);
187 static void HRTIM_TIM_ResetConfig(HRTIM_TypeDef * HRTIMx,
188  uint32_t TimerIdx,
189  uint32_t Event);
228 void HRTIM_SimpleBase_Init(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
229 {
230  /* Check the parameters */
232  assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
233 
234  if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
235  {
236  /* Configure master timer */
237  HRTIM_MasterBase_Config(HRTIMx, HRTIM_BaseInitStruct);
238  }
239  else
240  {
241  /* Configure timing unit */
242  HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
243  }
244 }
245 
251 #ifdef __GNUC__
252 # pragma GCC diagnostic push
253 # pragma GCC diagnostic ignored "-Wunused-parameter"
254 #endif
255 void HRTIM_DeInit(HRTIM_TypeDef* HRTIMx)
256 {
257  /* Check the parameters */
260  }
261 #ifdef __GNUC__
262 # pragma GCC diagnostic pop
263 #endif
264 
275 void HRTIM_SimpleOC_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
276 {
277  /* Check the parameters */
279  assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
280 
281  /* Configure timing unit */
282  HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
283 }
284 
295 void HRTIM_SimplePWM_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
296 {
297  /* Check the parameters */
299  assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
300 
301  /* Configure timing unit */
302  HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
303 }
304 
313 void HRTIM_SimpleCapture_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
314 {
315  /* Check the parameters */
317  assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
318 
319  /* Configure timing unit */
320  HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
321 }
322 
334 void HRTIM_SimpleOnePulse_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
335 {
336  /* Check the parameters */
338  assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
339 
340  /* Configure timing unit */
341  HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
342 }
343 
354 void HRTIM_Waveform_Init(HRTIM_TypeDef * HRTIMx,
355  uint32_t TimerIdx,
356  HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct,
357  HRTIM_TimerInitTypeDef* HRTIM_TimerInitStruct)
358 {
359  /* Check the parameters */
360  assert_param(IS_HRTIM_HALFMODE(HRTIM_TimerInitStruct->HalfModeEnable));
361  assert_param(IS_HRTIM_SYNCSTART(HRTIM_TimerInitStruct->StartOnSync));
362  assert_param(IS_HRTIM_SYNCRESET(HRTIM_TimerInitStruct->ResetOnSync));
363  assert_param(IS_HRTIM_DACSYNC(HRTIM_TimerInitStruct->DACSynchro));
364  assert_param(IS_HRTIM_PRELOAD(HRTIM_TimerInitStruct->PreloadEnable));
365  assert_param(IS_HRTIM_TIMERBURSTMODE(HRTIM_TimerInitStruct->BurstMode));
367 
368  if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
369  {
370  /* Check parameters */
371  assert_param(IS_HRTIM_UPDATEGATING_MASTER(HRTIM_TimerInitStruct->UpdateGating));
372 
373  /* Configure master timer */
374  HRTIM_MasterBase_Config(HRTIMx, HRTIM_BaseInitStruct);
375  HRTIM_MasterWaveform_Config(HRTIMx, HRTIM_TimerInitStruct);
376  }
377  else
378  {
379  /* Check parameters */
380  assert_param(IS_HRTIM_UPDATEGATING_TIM(HRTIM_TimerInitStruct->UpdateGating));
381 
382  /* Configure timing unit */
383  HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
384  HRTIM_TimingUnitWaveform_Config(HRTIMx, TimerIdx, HRTIM_TimerInitStruct);
385  }
386 }
387 
424 void HRTIM_DLLCalibrationStart(HRTIM_TypeDef * HRTIMx, uint32_t CalibrationRate)
425 {
426  uint32_t HRTIM_dllcr;
427 
428  /* Check the parameters */
429  assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
430 
431  /* Configure DLL Calibration */
432  HRTIM_dllcr = (HRTIMx->HRTIM_COMMON).DLLCR;
433 
434  if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
435  {
436  /* One shot DLL calibration */
437  HRTIM_dllcr &= ~(HRTIM_DLLCR_CALEN);
438  HRTIM_dllcr |= HRTIM_DLLCR_CAL;
439  }
440  else
441  {
442  /* Periodic DLL calibration */
443  HRTIM_dllcr &= ~(HRTIM_DLLCR_CALRTE | HRTIM_DLLCR_CAL);
444  HRTIM_dllcr |= (CalibrationRate | HRTIM_DLLCR_CALEN);
445  }
446 
447  /* Update HRTIMx register */
448  HRTIMx->HRTIM_COMMON.DLLCR = HRTIM_dllcr;
449 
450 }
460 void HRTIM_SimpleBaseStart(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx)
461 {
462  /* Check the parameters */
464 
465  /* Enable the timer counter */
466  __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
467 }
468 
478 void HRTIM_SimpleBaseStop(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx)
479 {
480  /* Check the parameters */
481  assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
482 
483  /* Disable the timer counter */
484  __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
485 }
486 
507 void HRTIM_SimpleOCStart(HRTIM_TypeDef * HRTIMx,
508  uint32_t TimerIdx,
509  uint32_t OCChannel)
510 {
511  /* Check the parameters */
512  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
513 
514  /* Enable the timer output */
515  (HRTIMx->HRTIM_COMMON).OENR |= OCChannel;
516 
517  /* Enable the timer counter */
518  __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
519 
520 }
521 
542 void HRTIM_SimpleOCStop(HRTIM_TypeDef * HRTIMx,
543  uint32_t TimerIdx,
544  uint32_t OCChannel)
545 {
546  /* Check the parameters */
547  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
548 
549  /* Disable the timer output */
550  HRTIMx->HRTIM_COMMON.DISR |= OCChannel;
551 
552  /* Disable the timer counter */
553  __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
554 }
555 
576 void HRTIM_SimplePWMStart(HRTIM_TypeDef * HRTIMx,
577  uint32_t TimerIdx,
578  uint32_t PWMChannel)
579 {
580  /* Check the parameters */
581  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
582 
583  /* Enable the timer output */
584  HRTIMx->HRTIM_COMMON.OENR |= PWMChannel;
585 
586  /* Enable the timer counter */
587  __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
588 }
589 
610 void HRTIM_SimplePWMStop(HRTIM_TypeDef * HRTIMx,
611  uint32_t TimerIdx,
612  uint32_t PWMChannel)
613 {
614  /* Check the parameters */
615  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
616 
617  /* Disable the timer output */
618  HRTIMx->HRTIM_COMMON.DISR |= PWMChannel;
619 
620  /* Disable the timer counter */
621  __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
622 }
623 
639 #ifdef __GNUC__
640 # pragma GCC diagnostic push
641 # pragma GCC diagnostic ignored "-Wunused-parameter"
642 #endif
643 void HRTIM_SimpleCaptureStart(HRTIM_TypeDef * HRTIMx,
644  uint32_t TimerIdx,
645  uint32_t CaptureChannel)
646 {
647  /* Enable the timer counter */
648  __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
649 
650 }
651 #ifdef __GNUC__
652 # pragma GCC diagnostic pop
653 #endif
654 
667 void HRTIM_SimpleCaptureStop(HRTIM_TypeDef * HRTIMx,
668  uint32_t TimerIdx,
669  uint32_t CaptureChannel)
670 {
671  /* Check the parameters */
673  assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
674 
675  /* Set the capture unit trigger */
676  switch (CaptureChannel)
677  {
678  case HRTIM_CAPTUREUNIT_1:
679  {
680  HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
681  }
682  break;
683  case HRTIM_CAPTUREUNIT_2:
684  {
685  HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
686  }
687  break;
688  default:
689  break;
690  }
691 
692  /* Disable the timer counter */
693  if ((HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
694  (HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
695  {
696  __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
697  }
698 
699 }
700 
721 void HRTIM_SimpleOnePulseStart(HRTIM_TypeDef * HRTIMx,
722  uint32_t TimerIdx,
723  uint32_t OnePulseChannel)
724 {
725  /* Check the parameters */
726  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
727 
728  /* Enable the timer output */
729  HRTIMx->HRTIM_COMMON.OENR |= OnePulseChannel;
730 
731  /* Enable the timer counter */
732  __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
733 }
734 
755 void HRTIM_SimpleOnePulseStop(HRTIM_TypeDef * HRTIMx,
756  uint32_t TimerIdx,
757  uint32_t OnePulseChannel)
758 {
759  /* Check the parameters */
760  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
761 
762  /* Disable the timer output */
763  HRTIMx->HRTIM_COMMON.DISR |= OnePulseChannel;
764 
765  /* Disable the timer counter */
766  __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
767 }
768 
783 void HRTIM_WaveformCounterStart(HRTIM_TypeDef * HRTIMx,
784  uint32_t TimersToStart)
785 {
786  /* Enable timer(s) counter */
787  HRTIMx->HRTIM_MASTER.MCR |= TimersToStart;
788 }
789 
804 void HRTIM_WaveformCounterStop(HRTIM_TypeDef * HRTIMx,
805  uint32_t TimersToStop)
806 {
807  /* Disable timer(s) counter */
808  HRTIMx->HRTIM_MASTER.MCR &= ~TimersToStop;
809 }
810 
829 void HRTIM_WaveformOutputStart(HRTIM_TypeDef * HRTIMx,
830  uint32_t OutputsToStart)
831 {
832  /* Enable the HRTIM outputs */
833  HRTIMx->HRTIM_COMMON.OENR = OutputsToStart;
834 }
835 
854 void HRTIM_WaveformOutputStop(HRTIM_TypeDef * HRTIMx,
855  uint32_t OutputsToStop)
856 {
857  /* Disable the HRTIM outputs */
858  HRTIMx->HRTIM_COMMON.DISR = OutputsToStop;
859 }
860 
894 void HRTIM_ITConfig(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT, FunctionalState NewState)
895 {
897 
898  switch(TimerIdx)
899  {
901  {
902  if(NewState != DISABLE)
903  {
904  HRTIMx->HRTIM_MASTER.MDIER |= HRTIM_IT;
905  }
906  else
907  {
908  HRTIMx->HRTIM_MASTER.MDIER &= ~HRTIM_IT;
909  }
910  }
911  break;
917  {
918  if(NewState != DISABLE)
919  {
920  HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER |= HRTIM_IT;
921  }
922  else
923  {
924  HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER &= ~HRTIM_IT;
925  }
926  }
927  break;
928 
929  default:
930  break;
931  }
932 }
933 
951 void HRTIM_ITCommonConfig(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT, FunctionalState NewState)
952 {
953  if(NewState != DISABLE)
954  {
955  HRTIMx->HRTIM_COMMON.IER |= HRTIM_CommonIT;
956  }
957  else
958  {
959  HRTIMx->HRTIM_COMMON.IER &= ~HRTIM_CommonIT;
960  }
961 }
962 
994 void HRTIM_ClearFlag(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG)
995 {
997 
998  switch(TimerIdx)
999  {
1001  {
1002  HRTIMx->HRTIM_MASTER.MICR |= HRTIM_FLAG;
1003  }
1004  break;
1010  {
1011  HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxICR |= HRTIM_FLAG;
1012  }
1013  break;
1014 
1015  default:
1016  break;
1017  }
1018 }
1019 
1035 void HRTIM_ClearCommonFlag(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG)
1036 {
1037  HRTIMx->HRTIM_COMMON.ICR |= HRTIM_CommonFLAG;
1038 }
1039 
1071 void HRTIM_ClearITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT)
1072 {
1073  assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1074 
1075  switch(TimerIdx)
1076  {
1078  {
1079  HRTIMx->HRTIM_MASTER.MICR |= HRTIM_IT;
1080  }
1081  break;
1087  {
1088  HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxICR |= HRTIM_IT;
1089  }
1090  break;
1091 
1092  default:
1093  break;
1094  }
1095 }
1096 
1112 void HRTIM_ClearCommonITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT)
1113 {
1114  HRTIMx->HRTIM_COMMON.ICR |= HRTIM_CommonIT;
1115 }
1116 
1117 
1149 FlagStatus HRTIM_GetFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG)
1150 {
1151  assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1152 
1153  FlagStatus bitstatus = RESET;
1154 
1155  switch(TimerIdx)
1156  {
1158  {
1159  if ((HRTIMx->HRTIM_MASTER.MISR & HRTIM_FLAG) != RESET)
1160  {
1161  bitstatus = SET;
1162  }
1163  else
1164  {
1165  bitstatus = RESET;
1166  }
1167  }
1168  break;
1169 
1175  {
1176  if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_FLAG) != RESET)
1177  {
1178  bitstatus = SET;
1179  }
1180  else
1181  {
1182  bitstatus = RESET;
1183  }
1184  }
1185  break;
1186 
1187  default:
1188  break;
1189  }
1190  return bitstatus;
1191 }
1192 
1208 FlagStatus HRTIM_GetCommonFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG)
1209 {
1210  FlagStatus bitstatus = RESET;
1211 
1212  if((HRTIMx->HRTIM_COMMON.ISR & HRTIM_CommonFLAG) != RESET)
1213  {
1214  bitstatus = SET;
1215  }
1216  else
1217  {
1218  bitstatus = RESET;
1219  }
1220  return bitstatus;
1221 }
1222 
1254 ITStatus HRTIM_GetITStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT)
1255 {
1256  ITStatus bitstatus = RESET;
1257  uint16_t itstatus = 0x0, itenable = 0x0;
1258 
1259  assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1260 
1261  switch(TimerIdx)
1262  {
1264  {
1265  itstatus = HRTIMx->HRTIM_MASTER.MISR & HRTIM_IT;
1266 
1267  itenable = HRTIMx->HRTIM_MASTER.MDIER & HRTIM_IT;
1268  if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
1269  {
1270  bitstatus = SET;
1271  }
1272  else
1273  {
1274  bitstatus = RESET;
1275  }
1276  }
1277  break;
1278 
1284  {
1285  itstatus = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_IT;
1286 
1287  itenable = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER & HRTIM_IT;
1288  if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
1289  {
1290  bitstatus = SET;
1291  }
1292  else
1293  {
1294  bitstatus = RESET;
1295  }
1296  }
1297  break;
1298 
1299  default:
1300  break;
1301  }
1302  return bitstatus;
1303 }
1304 
1320 ITStatus HRTIM_GetCommonITStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT)
1321 {
1322  ITStatus bitstatus = RESET;
1323  uint16_t itstatus = 0x0, itenable = 0x0;
1324 
1325  itstatus = HRTIMx->HRTIM_COMMON.ISR & HRTIM_CommonIT;
1326  itenable = HRTIMx->HRTIM_COMMON.IER & HRTIM_CommonIT;
1327 
1328  if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
1329  {
1330  bitstatus = SET;
1331  }
1332  else
1333  {
1334  bitstatus = RESET;
1335  }
1336 
1337  return bitstatus;
1338 }
1339 
1373 void HRTIM_DMACmd(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_DMA, FunctionalState NewState)
1374 {
1375  assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1376 
1377  switch(TimerIdx)
1378  {
1380  {
1381  if(NewState != DISABLE)
1382  {
1383  HRTIMx->HRTIM_MASTER.MDIER |= HRTIM_DMA;
1384  }
1385  else
1386  {
1387  HRTIMx->HRTIM_MASTER.MDIER &= ~HRTIM_DMA;
1388  }
1389  }
1390  break;
1396  {
1397  if(NewState != DISABLE)
1398  {
1399  HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER |= HRTIM_DMA;
1400  }
1401  else
1402  {
1403  HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER &= ~HRTIM_DMA;
1404  }
1405  }
1406  break;
1407 
1408  default:
1409  break;
1410  }
1411 }
1412 
1460 void HRTIM_SimpleOCChannelConfig(HRTIM_TypeDef * HRTIMx,
1461  uint32_t TimerIdx,
1462  uint32_t OCChannel,
1463  HRTIM_BasicOCChannelCfgTypeDef* pBasicOCChannelCfg)
1464 {
1465  uint32_t CompareUnit = HRTIM_COMPAREUNIT_1;
1466  HRTIM_CompareCfgTypeDef CompareCfg;
1467  HRTIM_OutputCfgTypeDef OutputCfg;
1468 
1469  /* Check parameters */
1470  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1471  assert_param(IS_HRTIM_BASICOCMODE(pBasicOCChannelCfg->Mode));
1472  assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicOCChannelCfg->Polarity));
1473  assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicOCChannelCfg->IdleState));
1474 
1475  /* Configure timer compare unit */
1476  switch (OCChannel)
1477  {
1478  case HRTIM_OUTPUT_TA1:
1479  case HRTIM_OUTPUT_TB1:
1480  case HRTIM_OUTPUT_TC1:
1481  case HRTIM_OUTPUT_TD1:
1482  case HRTIM_OUTPUT_TE1:
1483  {
1484  CompareUnit = HRTIM_COMPAREUNIT_1;
1485  }
1486  break;
1487  case HRTIM_OUTPUT_TA2:
1488  case HRTIM_OUTPUT_TB2:
1489  case HRTIM_OUTPUT_TC2:
1490  case HRTIM_OUTPUT_TD2:
1491  case HRTIM_OUTPUT_TE2:
1492  {
1493  CompareUnit = HRTIM_COMPAREUNIT_2;
1494  }
1495  break;
1496  default:
1497  break;
1498  }
1499 
1500  CompareCfg.CompareValue = pBasicOCChannelCfg->Pulse;
1502  CompareCfg.AutoDelayedTimeout = 0;
1503 
1504  HRTIM_CompareUnitConfig(HRTIMx,
1505  TimerIdx,
1506  CompareUnit,
1507  &CompareCfg);
1508 
1509  /* Configure timer output */
1510  OutputCfg.Polarity = pBasicOCChannelCfg->Polarity;
1511  OutputCfg.IdleState = pBasicOCChannelCfg->IdleState;
1513  OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
1516 
1517  switch (pBasicOCChannelCfg->Mode)
1518  {
1520  {
1521  if (CompareUnit == HRTIM_COMPAREUNIT_1)
1522  {
1523  OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1524  }
1525  else
1526  {
1527  OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1528  }
1529  OutputCfg.ResetSource = OutputCfg.SetSource;
1530  }
1531  break;
1533  {
1534  if (CompareUnit == HRTIM_COMPAREUNIT_1)
1535  {
1536  OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1537  }
1538  else
1539  {
1540  OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1541  }
1542  OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1543  }
1544  break;
1546  {
1547  if (CompareUnit == HRTIM_COMPAREUNIT_1)
1548  {
1550  }
1551  else
1552  {
1554  }
1555  OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1556  }
1557  break;
1558  default:
1559  break;
1560  }
1561 
1562  HRTIM_OutputConfig(HRTIMx, TimerIdx, OCChannel, &OutputCfg);
1563 }
1564 
1592 void HRTIM_SimplePWMChannelConfig(HRTIM_TypeDef * HRTIMx,
1593  uint32_t TimerIdx,
1594  uint32_t PWMChannel,
1595  HRTIM_BasicPWMChannelCfgTypeDef* pBasicPWMChannelCfg)
1596 {
1597  uint32_t CompareUnit = HRTIM_COMPAREUNIT_1;
1598  HRTIM_CompareCfgTypeDef CompareCfg;
1599  HRTIM_OutputCfgTypeDef OutputCfg;
1600 
1601  /* Check parameters */
1602  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
1603  assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicPWMChannelCfg->Polarity));
1604  assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicPWMChannelCfg->IdleState));
1605 
1606  /* Configure timer compare unit */
1607  switch (PWMChannel)
1608  {
1609  case HRTIM_OUTPUT_TA1:
1610  case HRTIM_OUTPUT_TB1:
1611  case HRTIM_OUTPUT_TC1:
1612  case HRTIM_OUTPUT_TD1:
1613  case HRTIM_OUTPUT_TE1:
1614  {
1615  CompareUnit = HRTIM_COMPAREUNIT_1;
1616  }
1617  break;
1618  case HRTIM_OUTPUT_TA2:
1619  case HRTIM_OUTPUT_TB2:
1620  case HRTIM_OUTPUT_TC2:
1621  case HRTIM_OUTPUT_TD2:
1622  case HRTIM_OUTPUT_TE2:
1623  {
1624  CompareUnit = HRTIM_COMPAREUNIT_2;
1625  }
1626  break;
1627  default:
1628  break;
1629  }
1630 
1631  CompareCfg.CompareValue = pBasicPWMChannelCfg->Pulse;
1633  CompareCfg.AutoDelayedTimeout = 0;
1634 
1635  HRTIM_CompareUnitConfig(HRTIMx,
1636  TimerIdx,
1637  CompareUnit,
1638  &CompareCfg);
1639 
1640  /* Configure timer output */
1641  OutputCfg.Polarity = pBasicPWMChannelCfg->Polarity;
1642  OutputCfg.IdleState = pBasicPWMChannelCfg->IdleState;
1644  OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
1647 
1648  if (CompareUnit == HRTIM_COMPAREUNIT_1)
1649  {
1650  OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1651  }
1652  else
1653  {
1654  OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1655  }
1656  OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
1657 
1658  HRTIM_OutputConfig(HRTIMx, TimerIdx, PWMChannel, &OutputCfg);
1659 }
1660 
1678 void HRTIM_SimpleCaptureChannelConfig(HRTIM_TypeDef * HRTIMx,
1679  uint32_t TimerIdx,
1680  uint32_t CaptureChannel,
1681  HRTIM_BasicCaptureChannelCfgTypeDef* pBasicCaptureChannelCfg)
1682 {
1683  HRTIM_EventCfgTypeDef EventCfg;
1684 
1685  /* Check parameters */
1687  assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
1688  assert_param(IS_HRTIM_EVENT(pBasicCaptureChannelCfg->Event));
1689  assert_param(IS_HRTIM_EVENTPOLARITY(pBasicCaptureChannelCfg->EventPolarity));
1690  assert_param(IS_HRTIM_EVENTSENSITIVITY(pBasicCaptureChannelCfg->EventSensitivity));
1691  assert_param(IS_HRTIM_EVENTFILTER(pBasicCaptureChannelCfg->EventFilter));
1692 
1693  /* Configure external event channel */
1695  EventCfg.Filter = pBasicCaptureChannelCfg->EventFilter;
1696  EventCfg.Polarity = pBasicCaptureChannelCfg->EventPolarity;
1697  EventCfg.Sensitivity = pBasicCaptureChannelCfg->EventSensitivity;
1698  EventCfg.Source = HRTIM_EVENTSRC_1;
1699 
1701  pBasicCaptureChannelCfg->Event,
1702  &EventCfg);
1703 
1704  /* Memorize capture trigger (will be configured when the capture is started */
1705  HRTIM_CaptureUnitConfig(HRTIMx,
1706  TimerIdx,
1707  CaptureChannel,
1708  pBasicCaptureChannelCfg->Event);
1709 }
1710 
1742 void HRTIM_SimpleOnePulseChannelConfig(HRTIM_TypeDef * HRTIMx,
1743  uint32_t TimerIdx,
1744  uint32_t OnePulseChannel,
1745  HRTIM_BasicOnePulseChannelCfgTypeDef* pBasicOnePulseChannelCfg)
1746 {
1747  uint32_t CompareUnit = HRTIM_COMPAREUNIT_1;
1748  HRTIM_CompareCfgTypeDef CompareCfg;
1749  HRTIM_OutputCfgTypeDef OutputCfg;
1750  HRTIM_EventCfgTypeDef EventCfg;
1751 
1752  /* Check parameters */
1753  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
1754  assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicOnePulseChannelCfg->OutputPolarity));
1755  assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicOnePulseChannelCfg->OutputIdleState));
1756  assert_param(IS_HRTIM_EVENT(pBasicOnePulseChannelCfg->Event));
1757  assert_param(IS_HRTIM_EVENTPOLARITY(pBasicOnePulseChannelCfg->EventPolarity));
1758  assert_param(IS_HRTIM_EVENTSENSITIVITY(pBasicOnePulseChannelCfg->EventSensitivity));
1759  assert_param(IS_HRTIM_EVENTFILTER(pBasicOnePulseChannelCfg->EventFilter));
1760 
1761  /* Configure timer compare unit */
1762  switch (OnePulseChannel)
1763  {
1764  case HRTIM_OUTPUT_TA1:
1765  case HRTIM_OUTPUT_TB1:
1766  case HRTIM_OUTPUT_TC1:
1767  case HRTIM_OUTPUT_TD1:
1768  case HRTIM_OUTPUT_TE1:
1769  {
1770  CompareUnit = HRTIM_COMPAREUNIT_1;
1771  }
1772  break;
1773  case HRTIM_OUTPUT_TA2:
1774  case HRTIM_OUTPUT_TB2:
1775  case HRTIM_OUTPUT_TC2:
1776  case HRTIM_OUTPUT_TD2:
1777  case HRTIM_OUTPUT_TE2:
1778  {
1779  CompareUnit = HRTIM_COMPAREUNIT_2;
1780  }
1781  break;
1782  default:
1783  break;
1784  }
1785 
1786  CompareCfg.CompareValue = pBasicOnePulseChannelCfg->Pulse;
1788  CompareCfg.AutoDelayedTimeout = 0;
1789 
1790  HRTIM_CompareUnitConfig(HRTIMx,
1791  TimerIdx,
1792  CompareUnit,
1793  &CompareCfg);
1794 
1795  /* Configure timer output */
1796  OutputCfg.Polarity = pBasicOnePulseChannelCfg->OutputPolarity;
1797  OutputCfg.IdleState = pBasicOnePulseChannelCfg->OutputIdleState;
1799  OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
1802 
1803  if (CompareUnit == HRTIM_COMPAREUNIT_1)
1804  {
1805  OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1806  }
1807  else
1808  {
1809  OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1810  }
1811  OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
1812 
1813  HRTIM_OutputConfig(HRTIMx,
1814  TimerIdx,
1815  OnePulseChannel,
1816  &OutputCfg);
1817 
1818  /* Configure external event channel */
1820  EventCfg.Filter = pBasicOnePulseChannelCfg->EventFilter;
1821  EventCfg.Polarity = pBasicOnePulseChannelCfg->EventPolarity;
1822  EventCfg.Sensitivity = pBasicOnePulseChannelCfg->EventSensitivity;
1823  EventCfg.Source = HRTIM_EVENTSRC_1;
1824 
1826  pBasicOnePulseChannelCfg->Event,
1827  &EventCfg);
1828 
1829  /* Configure the timer reset register */
1830  HRTIM_TIM_ResetConfig(HRTIMx,
1831  TimerIdx,
1832  pBasicOnePulseChannelCfg->Event);
1833 }
1834 
1846 void HRTIM_WaveformTimerConfig(HRTIM_TypeDef * HRTIMx,
1847  uint32_t TimerIdx,
1848  HRTIM_TimerCfgTypeDef * pTimerCfg)
1849 {
1850  uint32_t HRTIM_timcr;
1851  uint32_t HRTIM_timfltr;
1852  uint32_t HRTIM_timoutr;
1853  uint32_t HRTIM_timrstr;
1854 
1855  /* Check parameters */
1865 
1866  /* Configure timing unit (Timer A to Timer E) */
1867  HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
1868  HRTIM_timfltr = HRTIMx->HRTIM_TIMERx[TimerIdx].FLTxR;
1869  HRTIM_timoutr = HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR;
1870  HRTIM_timrstr = HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR;
1871 
1872  /* Set the push-pull mode */
1873  HRTIM_timcr &= ~(HRTIM_TIMCR_PSHPLL);
1874  HRTIM_timcr |= pTimerCfg->PushPull;
1875 
1876  /* Enable/Disable registers update on timer counter reset */
1877  HRTIM_timcr &= ~(HRTIM_TIMCR_TRSTU);
1878  HRTIM_timcr |= pTimerCfg->ResetUpdate;
1879 
1880  /* Set the timer update trigger */
1881  HRTIM_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
1882  HRTIM_timcr |= pTimerCfg->UpdateTrigger;
1883 
1884  /* Enable/Disable the fault channel at timer level */
1885  HRTIM_timfltr &= ~(HRTIM_FLTR_FLTxEN);
1886  HRTIM_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
1887 
1888  /* Lock/Unlock fault sources at timer level */
1889  HRTIM_timfltr &= ~(HRTIM_FLTR_FLTCLK);
1890  HRTIM_timfltr |= pTimerCfg->FaultLock;
1891 
1892  /* Enable/Disable dead time insertion at timer level */
1893  HRTIM_timoutr &= ~(HRTIM_OUTR_DTEN);
1894  HRTIM_timoutr |= pTimerCfg->DeadTimeInsertion;
1895 
1896  /* Enable/Disable delayed protection at timer level */
1897  HRTIM_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN);
1898  HRTIM_timoutr |= pTimerCfg->DelayedProtectionMode;
1899 
1900  /* Set the timer counter reset trigger */
1901  HRTIM_timrstr = pTimerCfg->ResetTrigger;
1902 
1903  /* Update the HRTIMx registers */
1904  HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
1905  HRTIMx->HRTIM_TIMERx[TimerIdx].FLTxR = HRTIM_timfltr;
1906  HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR = HRTIM_timoutr;
1907  HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_timrstr;
1908  }
1909 
1932  void HRTIM_WaveformCompareConfig(HRTIM_TypeDef * HRTIMx,
1933  uint32_t TimerIdx,
1934  uint32_t CompareUnit,
1935  HRTIM_CompareCfgTypeDef* pCompareCfg)
1936 {
1937  uint32_t HRTIM_timcr;
1938 
1939  /* Check parameters */
1942 
1943  /* Configure the compare unit */
1944  switch (CompareUnit)
1945  {
1946  case HRTIM_COMPAREUNIT_1:
1947  {
1948  /* Set the compare value */
1949  HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
1950  }
1951  break;
1952  case HRTIM_COMPAREUNIT_2:
1953  {
1954  /* Set the compare value */
1955  HRTIMx->HRTIM_TIMERx[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
1956 
1957  if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
1958  {
1959  /* Configure auto-delayed mode */
1960  HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
1961  HRTIM_timcr &= ~HRTIM_TIMCR_DELCMP2;
1962  HRTIM_timcr |= pCompareCfg->AutoDelayedMode;
1963  HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
1964 
1965  /* Set the compare value for timeout compare unit (if any) */
1967  {
1968  HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
1969  }
1971  {
1972  HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
1973  }
1974  }
1975  }
1976  break;
1977  case HRTIM_COMPAREUNIT_3:
1978  {
1979  /* Set the compare value */
1980  HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
1981  }
1982  break;
1983  case HRTIM_COMPAREUNIT_4:
1984  {
1985  /* Set the compare value */
1986  HRTIMx->HRTIM_TIMERx[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
1987 
1988  if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
1989  {
1990  /* Configure auto-delayed mode */
1991  HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
1992  HRTIM_timcr &= ~HRTIM_TIMCR_DELCMP4;
1993  HRTIM_timcr |= (pCompareCfg->AutoDelayedMode << 2);
1994  HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
1995 
1996  /* Set the compare value for timeout compare unit (if any) */
1998  {
1999  HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
2000  }
2002  {
2003  HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
2004  }
2005  }
2006  }
2007  break;
2008  default:
2009  break;
2010  }
2011 }
2012 
2025 void HRTIM_MasterSetCompare(HRTIM_TypeDef * HRTIMx,
2026  uint32_t CompareUnit,
2027  uint32_t Compare)
2028 {
2029  /* Check parameters */
2030  assert_param(IS_HRTIM_COMPAREUNIT(CompareUnit));
2031 
2032  /* Configure the compare unit */
2033  switch (CompareUnit)
2034  {
2035  case HRTIM_COMPAREUNIT_1:
2036  {
2037  /* Set the compare value */
2038  HRTIMx->HRTIM_MASTER.MCMP1R = Compare;
2039  }
2040  break;
2041  case HRTIM_COMPAREUNIT_2:
2042  {
2043  /* Set the compare value */
2044  HRTIMx->HRTIM_MASTER.MCMP2R = Compare;
2045  }
2046  break;
2047  case HRTIM_COMPAREUNIT_3:
2048  {
2049  /* Set the compare value */
2050  HRTIMx->HRTIM_MASTER.MCMP3R = Compare;
2051  }
2052  break;
2053  case HRTIM_COMPAREUNIT_4:
2054  {
2055  /* Set the compare value */
2056  HRTIMx->HRTIM_MASTER.MCMP4R = Compare;
2057  }
2058  break;
2059  default:
2060  break;
2061  }
2062 }
2063 
2076 void HRTIM_SlaveSetCompare(HRTIM_TypeDef * HRTIMx,
2077  uint32_t TimerIdx,
2078  uint32_t CompareUnit,
2079  uint32_t Compare)
2080 {
2081  /* Check parameters */
2082  assert_param(IS_HRTIM_COMPAREUNIT(CompareUnit));
2083 
2084  /* Configure the compare unit */
2085  switch (CompareUnit)
2086  {
2087  case HRTIM_COMPAREUNIT_1:
2088  {
2089  /* Set the compare value */
2090  HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = Compare;
2091  }
2092  break;
2093  case HRTIM_COMPAREUNIT_2:
2094  {
2095  /* Set the compare value */
2096  HRTIMx->HRTIM_TIMERx[TimerIdx].CMP2xR = Compare;
2097  }
2098  break;
2099  case HRTIM_COMPAREUNIT_3:
2100  {
2101  /* Set the compare value */
2102  HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = Compare;
2103  }
2104  break;
2105  case HRTIM_COMPAREUNIT_4:
2106  {
2107  /* Set the compare value */
2108  HRTIMx->HRTIM_TIMERx[TimerIdx].CMP4xR = Compare;
2109  }
2110  break;
2111  default:
2112  break;
2113  }
2114 }
2128 void HRTIM_WaveformCaptureConfig(HRTIM_TypeDef * HRTIMx,
2129  uint32_t TimerIdx,
2130  uint32_t CaptureUnit,
2131  HRTIM_CaptureCfgTypeDef* pCaptureCfg)
2132 {
2133  /* Configure the capture unit */
2134  switch (CaptureUnit)
2135  {
2136  case HRTIM_CAPTUREUNIT_1:
2137  {
2138  HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = pCaptureCfg->Trigger;
2139  }
2140  break;
2141  case HRTIM_CAPTUREUNIT_2:
2142  {
2143  HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = pCaptureCfg->Trigger;
2144  }
2145  break;
2146  default:
2147  break;
2148  }
2149 }
2150 
2172 void HRTIM_WaveformOutputConfig(HRTIM_TypeDef * HRTIMx,
2173  uint32_t TimerIdx,
2174  uint32_t Output,
2175  HRTIM_OutputCfgTypeDef * pOutputCfg)
2176 {
2177  /* Check parameters */
2178  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
2185 
2186  /* Configure the timer output */
2187  HRTIM_OutputConfig(HRTIMx, TimerIdx, Output, pOutputCfg);
2188 }
2189 
2211 void HRTIM_TimerEventFilteringConfig(HRTIM_TypeDef * HRTIMx,
2212  uint32_t TimerIdx,
2213  uint32_t Event,
2214  HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
2215 {
2216  uint32_t HRTIM_eefr;
2217 
2218  /* Check parameters */
2220  assert_param(IS_HRTIM_EVENT(Event));
2221  assert_param(IS_HRTIM_TIMEVENTFILTER(pTimerEventFilteringCfg->Filter));
2222  assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
2223 
2224  /* Configure timer event filtering capabilities */
2225  switch (Event)
2226  {
2228  {
2229  HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = 0;
2230  HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = 0;
2231  }
2232  break;
2233  case HRTIM_EVENT_1:
2234  {
2235  HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
2236  HRTIM_eefr &= ~(HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH);
2237  HRTIM_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
2238  HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
2239  }
2240  break;
2241  case HRTIM_EVENT_2:
2242  {
2243  HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
2244  HRTIM_eefr &= ~(HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH);
2245  HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6);
2246  HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
2247  }
2248  break;
2249  case HRTIM_EVENT_3:
2250  {
2251  HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
2252  HRTIM_eefr &= ~(HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH);
2253  HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12);
2254  HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
2255  }
2256  break;
2257  case HRTIM_EVENT_4:
2258  {
2259  HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
2260  HRTIM_eefr &= ~(HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH);
2261  HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18);
2262  HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
2263  }
2264  break;
2265  case HRTIM_EVENT_5:
2266  {
2267  HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
2268  HRTIM_eefr &= ~(HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH);
2269  HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24);
2270  HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
2271  }
2272  break;
2273  case HRTIM_EVENT_6:
2274  {
2275  HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
2276  HRTIM_eefr &= ~(HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH);
2277  HRTIM_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
2278  HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
2279  }
2280  break;
2281  case HRTIM_EVENT_7:
2282  {
2283  HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
2284  HRTIM_eefr &= ~(HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH);
2285  HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6);
2286  HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
2287  }
2288  break;
2289  case HRTIM_EVENT_8:
2290  {
2291  HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
2292  HRTIM_eefr &= ~(HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH);
2293  HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12);
2294  HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
2295  }
2296  break;
2297  case HRTIM_EVENT_9:
2298  {
2299  HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
2300  HRTIM_eefr &= ~(HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH);
2301  HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18);
2302  HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
2303  }
2304  break;
2305  case HRTIM_EVENT_10:
2306  {
2307  HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
2308  HRTIM_eefr &= ~(HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH);
2309  HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24);
2310  HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
2311  }
2312  break;
2313  default:
2314  break;
2315  }
2316 }
2317 
2327 void HRTIM_DeadTimeConfig(HRTIM_TypeDef * HRTIMx,
2328  uint32_t TimerIdx,
2329  HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
2330 {
2331  uint32_t HRTIM_dtr;
2332 
2333  /* Check parameters */
2341 
2342  HRTIM_dtr = HRTIMx->HRTIM_TIMERx[TimerIdx].DTxR;
2343 
2344  /* Clear timer dead times configuration */
2345  HRTIM_dtr &= ~(HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
2346  HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_SDTF |
2347  HRTIM_DTR_SDTR | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK);
2348 
2349  /* Set timer dead times configuration */
2350  HRTIM_dtr |= (pDeadTimeCfg->Prescaler << 10);
2351  HRTIM_dtr |= pDeadTimeCfg->RisingValue;
2352  HRTIM_dtr |= pDeadTimeCfg->RisingSign;
2353  HRTIM_dtr |= pDeadTimeCfg->RisingSignLock;
2354  HRTIM_dtr |= pDeadTimeCfg->RisingLock;
2355  HRTIM_dtr |= (pDeadTimeCfg->FallingValue << 16);
2356  HRTIM_dtr |= pDeadTimeCfg->FallingSign;
2357  HRTIM_dtr |= pDeadTimeCfg->FallingSignLock;
2358  HRTIM_dtr |= pDeadTimeCfg->FallingLock;
2359 
2360  /* Update the HRTIMx registers */
2361  HRTIMx->HRTIM_TIMERx[TimerIdx].DTxR = HRTIM_dtr;
2362 }
2363 
2373 void HRTIM_ChopperModeConfig(HRTIM_TypeDef * HRTIMx,
2374  uint32_t TimerIdx,
2375  HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
2376 {
2377  uint32_t HRTIM_chpr;
2378 
2379  /* Check parameters */
2381 
2382  HRTIM_chpr = HRTIMx->HRTIM_TIMERx[TimerIdx].CHPxR;
2383 
2384  /* Clear timer chopper mode configuration */
2385  HRTIM_chpr &= ~(HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW);
2386 
2387  /* Set timer chopper mode configuration */
2388  HRTIM_chpr |= pChopperModeCfg->CarrierFreq;
2389  HRTIM_chpr |= (pChopperModeCfg->DutyCycle << 4);
2390  HRTIM_chpr |= (pChopperModeCfg->StartPulse << 7);
2391 
2392  /* Update the HRTIMx registers */
2393  HRTIMx->HRTIM_TIMERx[TimerIdx].CHPxR = HRTIM_chpr;
2394 }
2395 
2428 void HRTIM_BurstDMAConfig(HRTIM_TypeDef * HRTIMx,
2429  uint32_t TimerIdx,
2430  uint32_t RegistersToUpdate)
2431 {
2432  /* Check parameters */
2433  assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
2434 
2435  /* Set the burst DMA timer update register */
2436  switch (TimerIdx)
2437  {
2439  {
2440  HRTIMx->HRTIM_COMMON.BDTAUPR = RegistersToUpdate;
2441  }
2442  break;
2444  {
2445  HRTIMx->HRTIM_COMMON.BDTBUPR = RegistersToUpdate;
2446  }
2447  break;
2449  {
2450  HRTIMx->HRTIM_COMMON.BDTCUPR = RegistersToUpdate;
2451  }
2452  break;
2454  {
2455  HRTIMx->HRTIM_COMMON.BDTDUPR = RegistersToUpdate;
2456  }
2457  break;
2459  {
2460  HRTIMx->HRTIM_COMMON.BDTEUPR = RegistersToUpdate;
2461  }
2462  break;
2464  {
2465  HRTIMx->HRTIM_COMMON.BDMUPDR = RegistersToUpdate;
2466  }
2467  break;
2468  default:
2469  break;
2470  }
2471 }
2472 
2479 void HRTIM_SynchronizationConfig(HRTIM_TypeDef *HRTIMx, HRTIM_SynchroCfgTypeDef * pSynchroCfg)
2480 {
2481  uint32_t HRTIM_mcr;
2482 
2483  /* Check parameters */
2487 
2488  HRTIM_mcr = HRTIMx->HRTIM_MASTER.MCR;
2489 
2490  /* Set the synchronization input source */
2491  HRTIM_mcr &= ~(HRTIM_MCR_SYNC_IN);
2492  HRTIM_mcr |= pSynchroCfg->SyncInputSource;
2493 
2494  /* Set the event to be sent on the synchronization output */
2495  HRTIM_mcr &= ~(HRTIM_MCR_SYNC_SRC);
2496  HRTIM_mcr |= pSynchroCfg->SyncOutputSource;
2497 
2498  /* Set the polarity of the synchronization output */
2499  HRTIM_mcr &= ~(HRTIM_MCR_SYNC_OUT);
2500  HRTIM_mcr |= pSynchroCfg->SyncOutputPolarity;
2501 
2502  /* Update the HRTIMx registers */
2503  HRTIMx->HRTIM_MASTER.MCR = HRTIM_mcr;
2504 }
2505 
2512 void HRTIM_BurstModeConfig(HRTIM_TypeDef * HRTIMx,
2513  HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
2514 {
2515  uint32_t HRTIM_bmcr;
2516 
2517  /* Check parameters */
2518  assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
2522 
2523  HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
2524 
2525  /* Set the burst mode operating mode */
2526  HRTIM_bmcr &= ~(HRTIM_BMCR_BMOM);
2527  HRTIM_bmcr |= pBurstModeCfg->Mode;
2528 
2529  /* Set the burst mode clock source */
2530  HRTIM_bmcr &= ~(HRTIM_BMCR_BMCLK);
2531  HRTIM_bmcr |= pBurstModeCfg->ClockSource;
2532 
2533  /* Set the burst mode prescaler */
2534  HRTIM_bmcr &= ~(HRTIM_BMCR_BMPSC);
2535  HRTIM_bmcr |= pBurstModeCfg->Prescaler;
2536 
2537  /* Enable/disable burst mode registers preload */
2538  HRTIM_bmcr &= ~(HRTIM_BMCR_BMPREN);
2539  HRTIM_bmcr |= pBurstModeCfg->PreloadEnable;
2540 
2541  /* Set the burst mode trigger */
2542  HRTIMx->HRTIM_COMMON.BMTRGR = pBurstModeCfg->Trigger;
2543 
2544  /* Set the burst mode compare value */
2545  HRTIMx->HRTIM_COMMON.BMCMPR = pBurstModeCfg->IdleDuration;
2546 
2547  /* Set the burst mode period */
2548  HRTIMx->HRTIM_COMMON.BMPER = pBurstModeCfg->Period;
2549 
2550  /* Update the HRTIMx registers */
2551  HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
2552 }
2553 
2572 void HRTIM_EventConfig(HRTIM_TypeDef * HRTIMx,
2573  uint32_t Event,
2574  HRTIM_EventCfgTypeDef* pEventCfg)
2575 {
2576  /* Check parameters */
2577  assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
2582 
2583  /* Configure the event channel */
2584  HRTIM_ExternalEventConfig(HRTIMx, Event, pEventCfg);
2585 
2586 }
2587 
2599 void HRTIM_EventPrescalerConfig(HRTIM_TypeDef * HRTIMx,
2600  uint32_t Prescaler)
2601 {
2602  uint32_t HRTIM_eecr3;
2603 
2604  /* Check parameters */
2606 
2607  /* Set the external event prescaler */
2608  HRTIM_eecr3 = HRTIMx->HRTIM_COMMON.EECR3;
2609  HRTIM_eecr3 &= ~(HRTIM_EECR3_EEVSD);
2610  HRTIM_eecr3 |= Prescaler;
2611 
2612  /* Update the HRTIMx registers */
2613  HRTIMx->HRTIM_COMMON.EECR3 = HRTIM_eecr3;
2614 }
2615 
2629 void HRTIM_FaultConfig(HRTIM_TypeDef * HRTIMx,
2630  HRTIM_FaultCfgTypeDef* pFaultCfg,
2631  uint32_t Fault)
2632 {
2633  uint32_t HRTIM_fltinr1;
2634  uint32_t HRTIM_fltinr2;
2635 
2636  /* Check parameters */
2637  assert_param(IS_HRTIM_FAULT(Fault));
2641  assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
2642 
2643  /* Configure fault channel */
2644  HRTIM_fltinr1 = HRTIMx->HRTIM_COMMON.FLTINxR1;
2645  HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2;
2646 
2647  switch (Fault)
2648  {
2649  case HRTIM_FAULT_1:
2650  {
2651  HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
2652  HRTIM_fltinr1 |= pFaultCfg->Polarity;
2653  HRTIM_fltinr1 |= pFaultCfg->Source;
2654  HRTIM_fltinr1 |= pFaultCfg->Filter;
2655  HRTIM_fltinr1 |= pFaultCfg->Lock;
2656  }
2657  break;
2658  case HRTIM_FAULT_2:
2659  {
2660  HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
2661  HRTIM_fltinr1 |= (pFaultCfg->Polarity << 8);
2662  HRTIM_fltinr1 |= (pFaultCfg->Source << 8);
2663  HRTIM_fltinr1 |= (pFaultCfg->Filter << 8);
2664  HRTIM_fltinr1 |= (pFaultCfg->Lock << 8);
2665  }
2666  break;
2667  case HRTIM_FAULT_3:
2668  {
2669  HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
2670  HRTIM_fltinr1 |= (pFaultCfg->Polarity << 16);
2671  HRTIM_fltinr1 |= (pFaultCfg->Source << 16);
2672  HRTIM_fltinr1 |= (pFaultCfg->Filter << 16);
2673  HRTIM_fltinr1 |= (pFaultCfg->Lock << 16);
2674  }
2675  break;
2676  case HRTIM_FAULT_4:
2677  {
2678  HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
2679  HRTIM_fltinr1 |= (pFaultCfg->Polarity << 24);
2680  HRTIM_fltinr1 |= (pFaultCfg->Source << 24);
2681  HRTIM_fltinr1 |= (pFaultCfg->Filter << 24);
2682  HRTIM_fltinr1 |= (pFaultCfg->Lock << 24);
2683  }
2684  break;
2685  case HRTIM_FAULT_5:
2686  {
2687  HRTIM_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
2688  HRTIM_fltinr2 |= pFaultCfg->Polarity;
2689  HRTIM_fltinr2 |= pFaultCfg->Source;
2690  HRTIM_fltinr2 |= pFaultCfg->Filter;
2691  HRTIM_fltinr2 |= pFaultCfg->Lock;
2692  }
2693  break;
2694  default:
2695  break;
2696  }
2697 
2698  /* Update the HRTIMx registers */
2699  HRTIMx->HRTIM_COMMON.FLTINxR1 = HRTIM_fltinr1;
2700  HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2;
2701 }
2702 
2714 void HRTIM_FaultPrescalerConfig(HRTIM_TypeDef * HRTIMx,
2715  uint32_t Prescaler)
2716 {
2717  uint32_t HRTIM_fltinr2;
2718 
2719  /* Check parameters */
2721 
2722  /* Set the external event prescaler */
2723  HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2;
2724  HRTIM_fltinr2 &= ~(HRTIM_FLTINR2_FLTSD);
2725  HRTIM_fltinr2 |= Prescaler;
2726 
2727  /* Update the HRTIMx registers */
2728  HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2;
2729 }
2730 
2747 void HRTIM_FaultModeCtl(HRTIM_TypeDef * HRTIMx, uint32_t Fault, uint32_t Enable)
2748 {
2749  uint32_t HRTIM_fltinr1;
2750  uint32_t HRTIM_fltinr2;
2751 
2752  /* Check parameters */
2753  assert_param(IS_HRTIM_FAULT(Fault));
2755 
2756  /* Configure fault channel */
2757  HRTIM_fltinr1 = HRTIMx->HRTIM_COMMON.FLTINxR1;
2758  HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2;
2759 
2760  switch (Fault)
2761  {
2762  case HRTIM_FAULT_1:
2763  {
2764  HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT1E;
2765  HRTIM_fltinr1 |= Enable;
2766  }
2767  break;
2768  case HRTIM_FAULT_2:
2769  {
2770  HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT2E;
2771  HRTIM_fltinr1 |= (Enable<< 8);
2772  }
2773  break;
2774  case HRTIM_FAULT_3:
2775  {
2776  HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT3E;
2777  HRTIM_fltinr1 |= (Enable << 16);
2778  }
2779  break;
2780  case HRTIM_FAULT_4:
2781  {
2782  HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT4E;
2783  HRTIM_fltinr1 |= (Enable << 24);
2784  }
2785  break;
2786  case HRTIM_FAULT_5:
2787  {
2788  HRTIM_fltinr2 &= ~HRTIM_FLTINR2_FLT5E;
2789  HRTIM_fltinr2 |= Enable;
2790  }
2791  break;
2792  default:
2793  break;
2794  }
2795 
2796  /* Update the HRTIMx registers */
2797  HRTIMx->HRTIM_COMMON.FLTINxR1 = HRTIM_fltinr1;
2798  HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2;
2799 }
2800 
2814 void HRTIM_ADCTriggerConfig(HRTIM_TypeDef * HRTIMx,
2815  uint32_t ADCTrigger,
2816  HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
2817 {
2818  uint32_t HRTIM_cr1;
2819 
2820  /* Check parameters */
2821  assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
2823 
2824  /* Set the ADC trigger update source */
2825  HRTIM_cr1 = HRTIMx->HRTIM_COMMON.CR1;
2826 
2827  switch (ADCTrigger)
2828  {
2829  case HRTIM_ADCTRIGGER_1:
2830  {
2831  HRTIM_cr1 &= ~(HRTIM_CR1_ADC1USRC);
2832  HRTIM_cr1 |= pADCTriggerCfg->UpdateSource;
2833 
2834  /* Set the ADC trigger 1 source */
2835  HRTIMx->HRTIM_COMMON.ADC1R = pADCTriggerCfg->Trigger;
2836  }
2837  break;
2838  case HRTIM_ADCTRIGGER_2:
2839  {
2840  HRTIM_cr1 &= ~(HRTIM_CR1_ADC2USRC);
2841  HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 3);
2842 
2843  /* Set the ADC trigger 2 source */
2844  HRTIMx->HRTIM_COMMON.ADC2R = pADCTriggerCfg->Trigger;
2845  }
2846  break;
2847  case HRTIM_ADCTRIGGER_3:
2848  {
2849  HRTIM_cr1 &= ~(HRTIM_CR1_ADC3USRC);
2850  HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 6);
2851 
2852  /* Set the ADC trigger 3 source */
2853  HRTIMx->HRTIM_COMMON.ADC3R = pADCTriggerCfg->Trigger;
2854  }
2855  case HRTIM_ADCTRIGGER_4:
2856  {
2857  HRTIM_cr1 &= ~(HRTIM_CR1_ADC4USRC);
2858  HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 9);
2859 
2860  /* Set the ADC trigger 4 source */
2861  HRTIMx->HRTIM_COMMON.ADC4R = pADCTriggerCfg->Trigger;
2862  }
2863  break;
2864  default:
2865  break;
2866  }
2867 
2868  /* Update the HRTIMx registers */
2869  HRTIMx->HRTIM_COMMON.CR1 = HRTIM_cr1;
2870 }
2871 
2872 
2882 void HRTIM_BurstModeCtl(HRTIM_TypeDef * HRTIMx, uint32_t Enable)
2883 {
2884  uint32_t HRTIM_bmcr;
2885 
2886  /* Check parameters */
2888 
2889  /* Enable/Disable the burst mode controller */
2890  HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
2891  HRTIM_bmcr &= ~(HRTIM_BMCR_BME);
2892  HRTIM_bmcr |= Enable;
2893 
2894  /* Update the HRTIMx registers */
2895  HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
2896 }
2897 
2912 void HRTIM_SoftwareCapture(HRTIM_TypeDef * HRTIMx,
2913  uint32_t TimerIdx,
2914  uint32_t CaptureUnit)
2915 {
2916  /* Check parameters */
2918  assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
2919 
2920  /* Force a software capture on concerned capture unit */
2921  switch (CaptureUnit)
2922  {
2923  case HRTIM_CAPTUREUNIT_1:
2924  {
2925  HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR |= HRTIM_CPT1CR_SWCPT;
2926  }
2927  break;
2928  case HRTIM_CAPTUREUNIT_2:
2929  {
2930  HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR |= HRTIM_CPT2CR_SWCPT;
2931  }
2932  break;
2933  default:
2934  break;
2935  }
2936 }
2937 
2953 void HRTIM_SoftwareUpdate(HRTIM_TypeDef * HRTIMx,
2954  uint32_t TimersToUpdate)
2955 {
2956  /* Check parameters */
2957  assert_param(IS_HRTIM_TIMERUPDATE(TimersToUpdate));
2958 
2959  /* Force timer(s) registers update */
2960  HRTIMx->HRTIM_COMMON.CR2 |= TimersToUpdate;
2961 
2962 }
2963 
2979 void HRTIM_SoftwareReset(HRTIM_TypeDef * HRTIMx,
2980  uint32_t TimersToReset)
2981 {
2982  /* Check parameters */
2983  assert_param(IS_HRTIM_TIMERRESET(TimersToReset));
2984 
2985  /* Force timer(s) registers update */
2986  HRTIMx->HRTIM_COMMON.CR2 |= TimersToReset;
2987 
2988 }
2989 
3016 void HRTIM_WaveformSetOutputLevel(HRTIM_TypeDef * HRTIMx,
3017  uint32_t TimerIdx,
3018  uint32_t Output,
3019  uint32_t OutputLevel)
3020 {
3021  /* Check parameters */
3022  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
3023  assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
3024 
3025  /* Force timer output level */
3026  switch (Output)
3027  {
3028  case HRTIM_OUTPUT_TA1:
3029  case HRTIM_OUTPUT_TB1:
3030  case HRTIM_OUTPUT_TC1:
3031  case HRTIM_OUTPUT_TD1:
3032  case HRTIM_OUTPUT_TE1:
3033  {
3034  if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
3035  {
3036  /* Force output to its active state */
3037  HRTIMx->HRTIM_TIMERx[TimerIdx].SETx1R |= HRTIM_SET1R_SST;
3038  }
3039  else
3040  {
3041  /* Force output to its inactive state */
3042  HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx1R |= HRTIM_RST1R_SRT;
3043  }
3044  }
3045  break;
3046  case HRTIM_OUTPUT_TA2:
3047  case HRTIM_OUTPUT_TB2:
3048  case HRTIM_OUTPUT_TC2:
3049  case HRTIM_OUTPUT_TD2:
3050  case HRTIM_OUTPUT_TE2:
3051  {
3052  if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
3053  {
3054  /* Force output to its active state */
3055  HRTIMx->HRTIM_TIMERx[TimerIdx].SETx2R |= HRTIM_SET2R_SST;
3056  }
3057  else
3058  {
3059  /* Force output to its inactive state */
3060  HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx2R |= HRTIM_RST2R_SRT;
3061  }
3062  }
3063  break;
3064  default:
3065  break;
3066  }
3067 }
3068 
3069 
3101 uint32_t HRTIM_GetCapturedValue(HRTIM_TypeDef * HRTIMx,
3102  uint32_t TimerIdx,
3103  uint32_t CaptureUnit)
3104 {
3105  uint32_t captured_value = 0;
3106 
3107  /* Check parameters */
3109  assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
3110 
3111  /* Read captured value */
3112  switch (CaptureUnit)
3113  {
3114  case HRTIM_CAPTUREUNIT_1:
3115  {
3116  captured_value = HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xR;
3117  }
3118  break;
3119  case HRTIM_CAPTUREUNIT_2:
3120  {
3121  captured_value = HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xR;
3122  }
3123  break;
3124  default:
3125  break;
3126  }
3127 
3128  return captured_value;
3129 }
3130 
3153 uint32_t HRTIM_WaveformGetOutputLevel(HRTIM_TypeDef * HRTIMx,
3154  uint32_t TimerIdx,
3155  uint32_t Output)
3156 {
3157  uint32_t output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
3158 
3159  /* Check parameters */
3160  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
3161 
3162  /* Read the output level */
3163  switch (Output)
3164  {
3165  case HRTIM_OUTPUT_TA1:
3166  case HRTIM_OUTPUT_TB1:
3167  case HRTIM_OUTPUT_TC1:
3168  case HRTIM_OUTPUT_TD1:
3169  case HRTIM_OUTPUT_TE1:
3170  {
3171  if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != RESET)
3172  {
3173  output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
3174  }
3175  else
3176  {
3177  output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
3178  }
3179  }
3180  break;
3181  case HRTIM_OUTPUT_TA2:
3182  case HRTIM_OUTPUT_TB2:
3183  case HRTIM_OUTPUT_TC2:
3184  case HRTIM_OUTPUT_TD2:
3185  case HRTIM_OUTPUT_TE2:
3186  {
3187  if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != RESET)
3188  {
3189  output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
3190  }
3191  else
3192  {
3193  output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
3194  }
3195  }
3196  break;
3197  default:
3198  break;
3199  }
3200 
3201  return output_level;
3202 }
3203 
3224 #ifdef __GNUC__
3225 # pragma GCC diagnostic push
3226 # pragma GCC diagnostic ignored "-Wunused-parameter"
3227 #endif
3228 uint32_t HRTIM_WaveformGetOutputState(HRTIM_TypeDef * HRTIMx,
3229  uint32_t TimerIdx,
3230  uint32_t Output)
3231 {
3232  uint32_t output_bit = 0;
3233  uint32_t output_state = HRTIM_OUTPUTSTATE_IDLE;
3234 
3235  /* Check parameters */
3236  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
3237 
3238  /* Set output state according to output control status and output disable status */
3239  switch (Output)
3240  {
3241  case HRTIM_OUTPUT_TA1:
3242  {
3243  output_bit = HRTIM_OENR_TA1OEN;
3244  }
3245  break;
3246  case HRTIM_OUTPUT_TA2:
3247  {
3248  output_bit = HRTIM_OENR_TA2OEN;
3249  }
3250  break;
3251  case HRTIM_OUTPUT_TB1:
3252  {
3253  output_bit = HRTIM_OENR_TB1OEN;
3254  }
3255  break;
3256  case HRTIM_OUTPUT_TB2:
3257  {
3258  output_bit = HRTIM_OENR_TB2OEN;
3259  }
3260  break;
3261  case HRTIM_OUTPUT_TC1:
3262  {
3263  output_bit = HRTIM_OENR_TC1OEN;
3264  }
3265  break;
3266  case HRTIM_OUTPUT_TC2:
3267  {
3268  output_bit = HRTIM_OENR_TC2OEN;
3269  }
3270  break;
3271  case HRTIM_OUTPUT_TD1:
3272  {
3273  output_bit = HRTIM_OENR_TD1OEN;
3274  }
3275  break;
3276  case HRTIM_OUTPUT_TD2:
3277  {
3278  output_bit = HRTIM_OENR_TD2OEN;
3279  }
3280  break;
3281  case HRTIM_OUTPUT_TE1:
3282  {
3283  output_bit = HRTIM_OENR_TE1OEN;
3284  }
3285  break;
3286  case HRTIM_OUTPUT_TE2:
3287  {
3288  output_bit = HRTIM_OENR_TE2OEN;
3289  }
3290  break;
3291  default:
3292  break;
3293  }
3294 
3295  if ((HRTIMx->HRTIM_COMMON.OENR & output_bit) != RESET)
3296  {
3297  /* Output is enabled: output in RUN state (whatever ouput disable status is)*/
3298  output_state = HRTIM_OUTPUTSTATE_RUN;
3299  }
3300  else
3301  {
3302  if ((HRTIMx->HRTIM_COMMON.ODSR & output_bit) != RESET)
3303  {
3304  /* Output is disabled: output in FAULT state */
3305  output_state = HRTIM_OUTPUTSTATE_FAULT;
3306  }
3307  else
3308  {
3309  /* Output is disabled: output in IDLE state */
3310  output_state = HRTIM_OUTPUTSTATE_IDLE;
3311  }
3312  }
3313 
3314  return(output_state);
3315 }
3316 #ifdef __GNUC__
3317 # pragma GCC diagnostic pop
3318 #endif
3319 
3341 uint32_t HRTIM_GetDelayedProtectionStatus(HRTIM_TypeDef * HRTIMx,
3342  uint32_t TimerIdx,
3343  uint32_t Output)
3344 {
3345  uint32_t delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
3346 
3347  /* Check parameters */
3348  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
3349 
3350  /* Read the delayed protection status */
3351  switch (Output)
3352  {
3353  case HRTIM_OUTPUT_TA1:
3354  case HRTIM_OUTPUT_TB1:
3355  case HRTIM_OUTPUT_TC1:
3356  case HRTIM_OUTPUT_TD1:
3357  case HRTIM_OUTPUT_TE1:
3358  {
3359  if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != RESET)
3360  {
3361  /* Output 1 was active when the delayed idle protection was triggered */
3362  delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
3363  }
3364  else
3365  {
3366  /* Output 1 was inactive when the delayed idle protection was triggered */
3367  delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
3368  }
3369  }
3370  break;
3371  case HRTIM_OUTPUT_TA2:
3372  case HRTIM_OUTPUT_TB2:
3373  case HRTIM_OUTPUT_TC2:
3374  case HRTIM_OUTPUT_TD2:
3375  case HRTIM_OUTPUT_TE2:
3376  {
3377  if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != RESET)
3378  {
3379  /* Output 2 was active when the delayed idle protection was triggered */
3380  delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
3381  }
3382  else
3383  {
3384  /* Output 2 was inactive when the delayed idle protection was triggered */
3385  delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
3386  }
3387  }
3388  break;
3389  default:
3390  break;
3391  }
3392 
3393  return delayed_protection_status;
3394 }
3395 
3401 uint32_t HRTIM_GetBurstStatus(HRTIM_TypeDef * HRTIMx)
3402 {
3403  uint32_t burst_mode_status;
3404 
3405  /* Read burst mode status */
3406  burst_mode_status = (HRTIMx->HRTIM_COMMON.BMCR & HRTIM_BMCR_BMSTAT);
3407 
3408  return burst_mode_status;
3409 }
3410 
3420 uint32_t HRTIM_GetCurrentPushPullStatus(HRTIM_TypeDef * HRTIMx,
3421  uint32_t TimerIdx)
3422 {
3423  uint32_t current_pushpull_status;
3424 
3425  /* Check the parameters */
3427 
3428  /* Read current push pull status */
3429  current_pushpull_status = (HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
3430 
3431  return current_pushpull_status;
3432 }
3433 
3434 
3444 uint32_t HRTIM_GetIdlePushPullStatus(HRTIM_TypeDef * HRTIMx,
3445  uint32_t TimerIdx)
3446 {
3447  uint32_t idle_pushpull_status;
3448 
3449  /* Check the parameters */
3451 
3452  /* Read current push pull status */
3453  idle_pushpull_status = (HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
3454 
3455  return idle_pushpull_status;
3456 }
3457 
3463 void HRTIM_MasterBase_Config(HRTIM_TypeDef * HRTIMx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
3464 {
3465  /* Set the prescaler ratio */
3466  HRTIMx->HRTIM_MASTER.MCR &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
3467  HRTIMx->HRTIM_MASTER.MCR |= (uint32_t)HRTIM_BaseInitStruct->PrescalerRatio;
3468 
3469  /* Set the operating mode */
3470  HRTIMx->HRTIM_MASTER.MCR &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
3471  HRTIMx->HRTIM_MASTER.MCR |= (uint32_t)HRTIM_BaseInitStruct->Mode;
3472 
3473  /* Update the HRTIMx registers */
3474  HRTIMx->HRTIM_MASTER.MPER = HRTIM_BaseInitStruct->Period;
3475  HRTIMx->HRTIM_MASTER.MREP = HRTIM_BaseInitStruct->RepetitionCounter;
3476 }
3477 
3484 void HRTIM_TimingUnitBase_Config(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
3485 {
3486  /* Set the prescaler ratio */
3487  HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
3488  HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR |= (uint32_t)HRTIM_BaseInitStruct->PrescalerRatio;
3489 
3490  /* Set the operating mode */
3491  HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
3492  HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR |= (uint32_t)HRTIM_BaseInitStruct->Mode;
3493 
3494  /* Update the HRTIMx registers */
3495  HRTIMx->HRTIM_TIMERx[TimerIdx].PERxR = HRTIM_BaseInitStruct->Period;
3496  HRTIMx->HRTIM_TIMERx[TimerIdx].REPxR = HRTIM_BaseInitStruct->RepetitionCounter;
3497 }
3498 
3506 void HRTIM_MasterWaveform_Config(HRTIM_TypeDef * HRTIMx,
3507  HRTIM_TimerInitTypeDef * pTimerInit)
3508 {
3509  uint32_t HRTIM_mcr;
3510  uint32_t HRTIM_bmcr;
3511 
3512  /* Configure master timer */
3513  HRTIM_mcr = HRTIMx->HRTIM_MASTER.MCR;
3514  HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
3515 
3516  /* Enable/Disable the half mode */
3517  HRTIM_mcr &= ~(HRTIM_MCR_HALF);
3518  HRTIM_mcr |= pTimerInit->HalfModeEnable;
3519 
3520  /* Enable/Disable the timer start upon synchronization event reception */
3521  HRTIM_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
3522  HRTIM_mcr |= pTimerInit->StartOnSync;
3523 
3524  /* Enable/Disable the timer reset upon synchronization event reception */
3525  HRTIM_mcr &= ~(HRTIM_MCR_SYNCRSTM);
3526  HRTIM_mcr |= pTimerInit->ResetOnSync;
3527 
3528  /* Enable/Disable the DAC synchronization event generation */
3529  HRTIM_mcr &= ~(HRTIM_MCR_DACSYNC);
3530  HRTIM_mcr |= pTimerInit->DACSynchro;
3531 
3532  /* Enable/Disable preload mechanism for timer registers */
3533  HRTIM_mcr &= ~(HRTIM_MCR_PREEN);
3534  HRTIM_mcr |= pTimerInit->PreloadEnable;
3535 
3536  /* Master timer registers update handling */
3537  HRTIM_mcr &= ~(HRTIM_MCR_BRSTDMA);
3538  HRTIM_mcr |= (pTimerInit->UpdateGating << 2);
3539 
3540  /* Enable/Disable registers update on repetition */
3541  HRTIM_mcr &= ~(HRTIM_MCR_MREPU);
3542  HRTIM_mcr |= pTimerInit->RepetitionUpdate;
3543 
3544  /* Set the timer burst mode */
3545  HRTIM_bmcr &= ~(HRTIM_BMCR_MTBM);
3546  HRTIM_bmcr |= pTimerInit->BurstMode;
3547 
3548  /* Update the HRTIMx registers */
3549  HRTIMx->HRTIM_MASTER.MCR = HRTIM_mcr;
3550  HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
3551 
3552 }
3553 
3561 void HRTIM_TimingUnitWaveform_Config(HRTIM_TypeDef * HRTIMx,
3562  uint32_t TimerIdx,
3563  HRTIM_TimerInitTypeDef * pTimerInit)
3564 {
3565  uint32_t HRTIM_timcr;
3566  uint32_t HRTIM_bmcr;
3567 
3568  /* Configure timing unit */
3569  HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
3570  HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
3571 
3572  /* Enable/Disable the half mode */
3573  HRTIM_timcr &= ~(HRTIM_TIMCR_HALF);
3574  HRTIM_timcr |= pTimerInit->HalfModeEnable;
3575 
3576  /* Enable/Disable the timer start upon synchronization event reception */
3577  HRTIM_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
3578  HRTIM_timcr |= pTimerInit->StartOnSync;
3579 
3580  /* Enable/Disable the timer reset upon synchronization event reception */
3581  HRTIM_timcr &= ~(HRTIM_TIMCR_SYNCRST);
3582  HRTIM_timcr |= pTimerInit->ResetOnSync;
3583 
3584  /* Enable/Disable the DAC synchronization event generation */
3585  HRTIM_timcr &= ~(HRTIM_TIMCR_DACSYNC);
3586  HRTIM_timcr |= pTimerInit->DACSynchro;
3587 
3588  /* Enable/Disable preload mechanism for timer registers */
3589  HRTIM_timcr &= ~(HRTIM_TIMCR_PREEN);
3590  HRTIM_timcr |= pTimerInit->PreloadEnable;
3591 
3592  /* Timing unit registers update handling */
3593  HRTIM_timcr &= ~(HRTIM_TIMCR_UPDGAT);
3594  HRTIM_timcr |= pTimerInit->UpdateGating;
3595 
3596  /* Enable/Disable registers update on repetition */
3597  HRTIM_timcr &= ~(HRTIM_TIMCR_TREPU);
3599  {
3600  HRTIM_timcr |= HRTIM_TIMCR_TREPU;
3601  }
3602 
3603  /* Set the timer burst mode */
3604  switch (TimerIdx)
3605  {
3607  {
3608  HRTIM_bmcr &= ~(HRTIM_BMCR_TABM);
3609  HRTIM_bmcr |= ( pTimerInit->BurstMode << 1);
3610  }
3611  break;
3613  {
3614  HRTIM_bmcr &= ~(HRTIM_BMCR_TBBM);
3615  HRTIM_bmcr |= ( pTimerInit->BurstMode << 2);
3616  }
3617  break;
3619  {
3620  HRTIM_bmcr &= ~(HRTIM_BMCR_TCBM);
3621  HRTIM_bmcr |= ( pTimerInit->BurstMode << 3);
3622  }
3623  break;
3625  {
3626  HRTIM_bmcr &= ~(HRTIM_BMCR_TDBM);
3627  HRTIM_bmcr |= ( pTimerInit->BurstMode << 4);
3628  }
3629  break;
3631  {
3632  HRTIM_bmcr &= ~(HRTIM_BMCR_TEBM);
3633  HRTIM_bmcr |= ( pTimerInit->BurstMode << 5);
3634  }
3635  break;
3636  default:
3637  break;
3638  }
3639 
3640  /* Update the HRTIMx registers */
3641  HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
3642  HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
3643 }
3644 
3653 void HRTIM_CompareUnitConfig(HRTIM_TypeDef * HRTIMx,
3654  uint32_t TimerIdx,
3655  uint32_t CompareUnit,
3656  HRTIM_CompareCfgTypeDef * pCompareCfg)
3657 {
3658  if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
3659  {
3660  /* Configure the compare unit of the master timer */
3661  switch (CompareUnit)
3662  {
3663  case HRTIM_COMPAREUNIT_1:
3664  {
3665  HRTIMx->HRTIM_MASTER.MCMP1R = pCompareCfg->CompareValue;
3666  }
3667  break;
3668  case HRTIM_COMPAREUNIT_2:
3669  {
3670  HRTIMx->HRTIM_MASTER.MCMP2R = pCompareCfg->CompareValue;
3671  }
3672  break;
3673  case HRTIM_COMPAREUNIT_3:
3674  {
3675  HRTIMx->HRTIM_MASTER.MCMP3R = pCompareCfg->CompareValue;
3676  }
3677  break;
3678  case HRTIM_COMPAREUNIT_4:
3679  {
3680  HRTIMx->HRTIM_MASTER.MCMP4R = pCompareCfg->CompareValue;
3681  }
3682  break;
3683  default:
3684  break;
3685  }
3686  }
3687  else
3688  {
3689  /* Configure the compare unit of the timing unit */
3690  switch (CompareUnit)
3691  {
3692  case HRTIM_COMPAREUNIT_1:
3693  {
3694  HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
3695  }
3696  break;
3697  case HRTIM_COMPAREUNIT_2:
3698  {
3699  HRTIMx->HRTIM_TIMERx[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
3700  }
3701  break;
3702  case HRTIM_COMPAREUNIT_3:
3703  {
3704  HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
3705  }
3706  break;
3707  case HRTIM_COMPAREUNIT_4:
3708  {
3709  HRTIMx->HRTIM_TIMERx[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
3710  }
3711  break;
3712  default:
3713  break;
3714  }
3715  }
3716 }
3717 
3726 void HRTIM_CaptureUnitConfig(HRTIM_TypeDef * HRTIMx,
3727  uint32_t TimerIdx,
3728  uint32_t CaptureUnit,
3729  uint32_t Event)
3730 {
3731  uint32_t CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
3732 
3733  switch (Event)
3734  {
3735  case HRTIM_EVENT_1:
3736  {
3737  CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
3738  }
3739  break;
3740  case HRTIM_EVENT_2:
3741  {
3742  CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
3743  }
3744  break;
3745  case HRTIM_EVENT_3:
3746  {
3747  CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
3748  }
3749  break;
3750  case HRTIM_EVENT_4:
3751  {
3752  CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
3753  }
3754  break;
3755  case HRTIM_EVENT_5:
3756  {
3757  CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
3758  }
3759  break;
3760  case HRTIM_EVENT_6:
3761  {
3762  CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
3763  }
3764  break;
3765  case HRTIM_EVENT_7:
3766  {
3767  CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
3768  }
3769  break;
3770  case HRTIM_EVENT_8:
3771  {
3772  CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
3773  }
3774  break;
3775  case HRTIM_EVENT_9:
3776  {
3777  CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
3778  }
3779  break;
3780  case HRTIM_EVENT_10:
3781  {
3782  CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
3783  }
3784  break;
3785  default:
3786  break;
3787 
3788  }
3789  switch (CaptureUnit)
3790  {
3791  case HRTIM_CAPTUREUNIT_1:
3792  {
3793  HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = CaptureTrigger;
3794  }
3795  break;
3796  case HRTIM_CAPTUREUNIT_2:
3797  {
3798  HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = CaptureTrigger;
3799  }
3800  break;
3801  default:
3802  break;
3803  }
3804 }
3805 
3814 void HRTIM_OutputConfig(HRTIM_TypeDef * HRTIMx,
3815  uint32_t TimerIdx,
3816  uint32_t Output,
3817  HRTIM_OutputCfgTypeDef * pOutputCfg)
3818 {
3819  uint32_t HRTIM_outr;
3820  uint32_t shift = 0;
3821 
3822  HRTIM_outr = HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR;
3823 
3824  switch (Output)
3825  {
3826  case HRTIM_OUTPUT_TA1:
3827  case HRTIM_OUTPUT_TB1:
3828  case HRTIM_OUTPUT_TC1:
3829  case HRTIM_OUTPUT_TD1:
3830  case HRTIM_OUTPUT_TE1:
3831  {
3832  /* Set the output set/reset crossbar */
3833  HRTIMx->HRTIM_TIMERx[TimerIdx].SETx1R = pOutputCfg->SetSource;
3834  HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
3835 
3836  shift = 0;
3837  }
3838  break;
3839  case HRTIM_OUTPUT_TA2:
3840  case HRTIM_OUTPUT_TB2:
3841  case HRTIM_OUTPUT_TC2:
3842  case HRTIM_OUTPUT_TD2:
3843  case HRTIM_OUTPUT_TE2:
3844  {
3845  /* Set the output set/reset crossbar */
3846  HRTIMx->HRTIM_TIMERx[TimerIdx].SETx2R = pOutputCfg->SetSource;
3847  HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
3848 
3849  shift = 16;
3850  }
3851  break;
3852  default:
3853  break;
3854  }
3855 
3856  /* Clear output config */
3857  HRTIM_outr &= ~((HRTIM_OUTR_POL1 |
3858  HRTIM_OUTR_IDLM1 |
3859  HRTIM_OUTR_IDLES1|
3860  HRTIM_OUTR_FAULT1|
3861  HRTIM_OUTR_CHP1 |
3862  HRTIM_OUTR_DIDL1) << shift);
3863 
3864  /* Set the polarity */
3865  HRTIM_outr |= (pOutputCfg->Polarity << shift);
3866 
3867  /* Set the IDLE mode */
3868  HRTIM_outr |= (pOutputCfg->IdleMode << shift);
3869 
3870  /* Set the IDLE state */
3871  HRTIM_outr |= (pOutputCfg->IdleState << shift);
3872 
3873  /* Set the FAULT state */
3874  HRTIM_outr |= (pOutputCfg->FaultState << shift);
3875 
3876  /* Set the chopper mode */
3877  HRTIM_outr |= (pOutputCfg->ChopperModeEnable << shift);
3878 
3879  /* Set the burst mode entry mode */
3880  HRTIM_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
3881 
3882  /* Update HRTIMx register */
3883  HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR = HRTIM_outr;
3884 }
3885 
3893 static void HRTIM_ExternalEventConfig(HRTIM_TypeDef * HRTIMx,
3894  uint32_t Event,
3895  HRTIM_EventCfgTypeDef *pEventCfg)
3896 {
3897  uint32_t hrtim_eecr1;
3898  uint32_t hrtim_eecr2;
3899  uint32_t hrtim_eecr3;
3900 
3901  /* Configure external event channel */
3902  hrtim_eecr1 = HRTIMx->HRTIM_COMMON.EECR1;
3903  hrtim_eecr2 = HRTIMx->HRTIM_COMMON.EECR2;
3904  hrtim_eecr3 = HRTIMx->HRTIM_COMMON.EECR3;
3905 
3906  switch (Event)
3907  {
3908  case HRTIM_EVENT_1:
3909  {
3910  hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
3911  hrtim_eecr1 |= pEventCfg->Source;
3912  hrtim_eecr1 |= pEventCfg->Polarity;
3913  hrtim_eecr1 |= pEventCfg->Sensitivity;
3914  /* Update the HRTIM registers (all bit fields but EE1FAST bit) */
3915  HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
3916  /* Update the HRTIM registers (EE1FAST bit) */
3917  hrtim_eecr1 |= pEventCfg->FastMode;
3918  HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
3919  }
3920  break;
3921  case HRTIM_EVENT_2:
3922  {
3923  hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
3924  hrtim_eecr1 |= (pEventCfg->Source << 6);
3925  hrtim_eecr1 |= (pEventCfg->Polarity << 6);
3926  hrtim_eecr1 |= (pEventCfg->Sensitivity << 6);
3927  /* Update the HRTIM registers (all bit fields but EE2FAST bit) */
3928  HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
3929  /* Update the HRTIM registers (EE2FAST bit) */
3930  hrtim_eecr1 |= (pEventCfg->FastMode << 6);
3931  HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
3932  }
3933  break;
3934  case HRTIM_EVENT_3:
3935  {
3936  hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
3937  hrtim_eecr1 |= (pEventCfg->Source << 12);
3938  hrtim_eecr1 |= (pEventCfg->Polarity << 12);
3939  hrtim_eecr1 |= (pEventCfg->Sensitivity << 12);
3940  /* Update the HRTIM registers (all bit fields but EE3FAST bit) */
3941  HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
3942  /* Update the HRTIM registers (EE3FAST bit) */
3943  hrtim_eecr1 |= (pEventCfg->FastMode << 12);
3944  HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
3945  }
3946  break;
3947  case HRTIM_EVENT_4:
3948  {
3949  hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
3950  hrtim_eecr1 |= (pEventCfg->Source << 18);
3951  hrtim_eecr1 |= (pEventCfg->Polarity << 18);
3952  hrtim_eecr1 |= (pEventCfg->Sensitivity << 18);
3953  /* Update the HRTIM registers (all bit fields but EE4FAST bit) */
3954  HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
3955  /* Update the HRTIM registers (EE4FAST bit) */
3956  hrtim_eecr1 |= (pEventCfg->FastMode << 18);
3957  HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
3958  }
3959  break;
3960  case HRTIM_EVENT_5:
3961  {
3962  hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
3963  hrtim_eecr1 |= (pEventCfg->Source << 24);
3964  hrtim_eecr1 |= (pEventCfg->Polarity << 24);
3965  hrtim_eecr1 |= (pEventCfg->Sensitivity << 24);
3966  /* Update the HRTIM registers (all bit fields but EE5FAST bit) */
3967  HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
3968  /* Update the HRTIM registers (EE5FAST bit) */
3969  hrtim_eecr1 |= (pEventCfg->FastMode << 24);
3970  HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
3971  }
3972  break;
3973  case HRTIM_EVENT_6:
3974  {
3975  hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
3976  hrtim_eecr2 |= pEventCfg->Source;
3977  hrtim_eecr2 |= pEventCfg->Polarity;
3978  hrtim_eecr2 |= pEventCfg->Sensitivity;
3979  hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
3980  hrtim_eecr3 |= pEventCfg->Filter;
3981  /* Update the HRTIM registers */
3982  HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
3983  HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
3984  }
3985  break;
3986  case HRTIM_EVENT_7:
3987  {
3988  hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
3989  hrtim_eecr2 |= (pEventCfg->Source << 6);
3990  hrtim_eecr2 |= (pEventCfg->Polarity << 6);
3991  hrtim_eecr2 |= (pEventCfg->Sensitivity << 6);
3992  hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
3993  hrtim_eecr3 |= (pEventCfg->Filter << 6);
3994  /* Update the HRTIM registers */
3995  HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
3996  HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
3997  }
3998  break;
3999  case HRTIM_EVENT_8:
4000  {
4001  hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
4002  hrtim_eecr2 |= (pEventCfg->Source << 12);
4003  hrtim_eecr2 |= (pEventCfg->Polarity << 12);
4004  hrtim_eecr2 |= (pEventCfg->Sensitivity << 12);
4005  hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
4006  hrtim_eecr3 |= (pEventCfg->Filter << 12);
4007  /* Update the HRTIM registers */
4008  HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
4009  HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
4010  }
4011  break;
4012  case HRTIM_EVENT_9:
4013  {
4014  hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
4015  hrtim_eecr2 |= (pEventCfg->Source << 18);
4016  hrtim_eecr2 |= (pEventCfg->Polarity << 18);
4017  hrtim_eecr2 |= (pEventCfg->Sensitivity << 18);
4018  hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
4019  hrtim_eecr3 |= (pEventCfg->Filter << 18);
4020  /* Update the HRTIM registers */
4021  HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
4022  HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
4023  }
4024  break;
4025  case HRTIM_EVENT_10:
4026  {
4027  hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
4028  hrtim_eecr2 |= (pEventCfg->Source << 24);
4029  hrtim_eecr2 |= (pEventCfg->Polarity << 24);
4030  hrtim_eecr2 |= (pEventCfg->Sensitivity << 24);
4031  hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
4032  hrtim_eecr3 |= (pEventCfg->Filter << 24);
4033  /* Update the HRTIM registers */
4034  HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
4035  HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
4036  }
4037  break;
4038  default:
4039  break;
4040  }
4041 }
4042 
4050 void HRTIM_TIM_ResetConfig(HRTIM_TypeDef * HRTIMx,
4051  uint32_t TimerIdx,
4052  uint32_t Event)
4053 {
4054  switch (Event)
4055  {
4056  case HRTIM_EVENT_1:
4057  {
4058  HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
4059  }
4060  break;
4061  case HRTIM_EVENT_2:
4062  {
4063  HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
4064  }
4065  break;
4066  case HRTIM_EVENT_3:
4067  {
4068  HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
4069  }
4070  break;
4071  case HRTIM_EVENT_4:
4072  {
4073  HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
4074  }
4075  break;
4076  case HRTIM_EVENT_5:
4077  {
4078  HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
4079  }
4080  break;
4081  case HRTIM_EVENT_6:
4082  {
4083  HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
4084  }
4085  break;
4086  case HRTIM_EVENT_7:
4087  {
4088  HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
4089  }
4090  break;
4091  case HRTIM_EVENT_8:
4092  {
4093  HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
4094  }
4095  break;
4096  case HRTIM_EVENT_9:
4097  {
4098  HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
4099  }
4100  break;
4101  case HRTIM_EVENT_10:
4102  {
4103  HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
4104  }
4105  break;
4106  default:
4107  break;
4108  }
4109 }
4121 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
4122 
4123 
4124 
void HRTIM_ITCommonConfig(HRTIM_TypeDef *HRTIMx, uint32_t HRTIM_CommonIT, FunctionalState NewState)
Enables or disables the common interrupt request.
void HRTIM_FaultPrescalerConfig(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
Configures the fault conditioning block prescaler.
static void HRTIM_TimingUnitBase_Config(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef *HRTIM_BaseInitStruct)
Configures timing unit (timer A to timer E) time base.
#define HRTIM_TIMERID_TIMER_E
#define IS_HRTIM_TIMERUPDATE(TIMERUPDATE)
#define HRTIM_CAPTURETRIGGER_EEV_2
FlagStatus
Definition: stm32f4xx.h:706
#define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE)
void HRTIM_Waveform_Init(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef *HRTIM_BaseInitStruct, HRTIM_TimerInitTypeDef *HRTIM_TimerInitStruct)
Initializes a timer operating in waveform mode.
#define HRTIM_OUTPUTSTATE_FAULT
void HRTIM_BurstModeCtl(HRTIM_TypeDef *HRTIMx, uint32_t Enable)
Enables or disables the HRTIMx burst mode controller.
#define HRTIM_FAULT_2
#define HRTIM_BASICOCMODE_INACTIVE
#define HRTIM_OUTPUTSTATE_RUN
#define HRTIM_FAULT_1
#define IS_HRTIM_MODE(MODE)
void HRTIM_DMACmd(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_DMA, FunctionalState NewState)
Enables or disables the HRTIMx&#39;s DMA Requests.
void HRTIM_ChopperModeConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_ChopperModeCfgTypeDef *pChopperModeCfg)
Configures the chopper mode feature for a timer.
void HRTIM_SimpleOC_Init(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef *HRTIM_BaseInitStruct)
Initializes the HRTIMx timer in basic output compare mode.
#define HRTIM_COMPAREUNIT_2
void HRTIM_ClearFlag(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG)
Clears the Master and slaves interrupt flags.
#define IS_HRTIM_TIMDEADTIMEINSERTION(TIMDEADTIMEINSERTION)
#define __HRTIM_DISABLE(__HANDLE__, __TIMERS__)
Dead time feature configuration definition.
#define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)
#define HRTIM_ADCTRIGGER_1
FlagStatus HRTIM_GetFlagStatus(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG)
Checks whether the specified HRTIM flag is set or not.
#define HRTIM_TIMRESETTRIGGER_EEV_2
void HRTIM_SimpleOnePulseChannelConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t OnePulseChannel, HRTIM_BasicOnePulseChannelCfgTypeDef *pBasicOnePulseChannelCfg)
Configures an output basic one pulse mode.
#define HRTIM_OUTPUTCHOPPERMODE_DISABLED
#define HRTIM_COMPAREUNIT_3
FunctionalState
Definition: stm32f4xx.h:708
#define HRTIM_OUTPUTSET_TIMCMP1
#define HRTIM_EVENT_5
#define HRTIM_ADCTRIGGER_2
void HRTIM_SimplePWMChannelConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t PWMChannel, HRTIM_BasicPWMChannelCfgTypeDef *pBasicPWMChannelCfg)
Configures an output in basic PWM mode.
Output
#define HRTIM_OUTPUT_TC1
#define HRTIM_CAPTURETRIGGER_EEV_7
#define HRTIM_OUTPUT_TA1
#define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)
#define HRTIM_FAULT_5
#define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)
Capture unit configuration definition.
Waveform mode initialization parameters definition.
#define HRTIM_CAPTURETRIGGER_EEV_4
Timer configuration definition.
void HRTIM_SimpleOCChannelConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t OCChannel, HRTIM_BasicOCChannelCfgTypeDef *pBasicOCChannelCfg)
Configures an output in basic output compare mode.
void HRTIM_SimpleOCStop(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t OCChannel)
Stops the output compare signal generation on the designed timer output.
#define HRTIM_TIMERID_TIMER_C
#define HRTIM_OUTPUT_TE1
#define HRTIM_CAPTURETRIGGER_EEV_5
#define HRTIM_BASICOCMODE_TOGGLE
void HRTIM_SimplePWMStop(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t PWMChannel)
Stops the PWM output signal generation on the designed timer output.
void HRTIM_DeInit(HRTIM_TypeDef *HRTIMx)
De-initializes a timer operating in all mode.
#define HRTIM_OUTPUTSTATE_IDLE
#define HRTIM_OUTPUTLEVEL_INACTIVE
HRTIM Configuration Structure definition - Time base related parameters.
#define HRTIM_CAPTURETRIGGER_EEV_1
#define HRTIM_EVENT_3
void HRTIM_EventConfig(HRTIM_TypeDef *HRTIMx, uint32_t Event, HRTIM_EventCfgTypeDef *pEventCfg)
Configures the conditioning of an external event.
#define IS_HRTIM_TIMDELAYEDPROTECTION(TIMDELAYEDPROTECTION)
#define HRTIM_TIMCR_TIMUPDATETRIGGER
void HRTIM_DeadTimeConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg)
Configures the dead time insertion feature for a timer.
Master synchronization configuration definition.
#define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)
#define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)
void HRTIM_EventPrescalerConfig(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
Configures the external event conditioning block prescaler.
void HRTIM_WaveformCompareConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CompareUnit, HRTIM_CompareCfgTypeDef *pCompareCfg)
Configures the compare unit of a timer operating in waveform mode.
#define HRTIM_EVENT_2
Chopper mode configuration definition.
#define HRTIM_TIMERINDEX_TIMER_A
#define HRTIM_TIMRESETTRIGGER_EEV_9
static void HRTIM_OutputConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t Output, HRTIM_OutputCfgTypeDef *OutputCfg)
Configures the output of a timing unit.
void HRTIM_FaultModeCtl(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Enable)
Enables or disables the HRTIMx Fault mode.
#define IS_HRTIM_BURSTMODE(BURSTMODE)
#define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)
void assert_param(int val)
#define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)
void HRTIM_SimpleCaptureChannelConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CaptureChannel, HRTIM_BasicCaptureChannelCfgTypeDef *pBasicCaptureChannelCfg)
Configures a basic capture.
#define HRTIM_CAPTURETRIGGER_EEV_10
#define HRTIM_FLTR_FLTxEN
#define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)
void HRTIM_SimpleCaptureStart(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CaptureChannel)
Enables a basic capture on the designed capture unit.
#define HRTIM_OUTPUT_TE2
#define IS_HRTIM_FAULTCTL(FAULTCTL)
#define HRTIM_OUTPUTLEVEL_ACTIVE
#define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)
#define HRTIM_OUTPUT_TD2
#define HRTIM_OUTPUTRESET_TIMCMP2
#define IS_HRTIM_TIMERRESET(TIMERRESET)
#define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)
#define IS_HRTIM_DACSYNC(DACSYNC)
uint32_t HRTIM_GetBurstStatus(HRTIM_TypeDef *HRTIMx)
Returns the actual status (active or inactive) of the burst mode controller.
uint32_t HRTIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx)
Indicates on which output the signal was applied, in push-pull mode balanced fault mode or delayed id...
void HRTIM_SimpleBaseStop(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx)
Stops the counter of a timer operating in basic time base mode.
#define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)
static void HRTIM_TIM_ResetConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t Event)
Configures the timer counter reset.
#define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)
#define HRTIM_TIMRESETTRIGGER_EEV_6
#define IS_HRTIM_EVENTSRC(EVENTSRC)
#define IS_HRTIM_BASICOCMODE(BASICOCMODE)
#define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)
void HRTIM_WaveformCounterStart(HRTIM_TypeDef *HRTIMx, uint32_t TimersToStart)
Starts the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed...
#define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION)
External event channel configuration definition.
#define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE)
uint32_t HRTIM_GetDelayedProtectionStatus(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t Output)
Returns the level (active or inactive) of the designated output when the delayed protection was trigg...
void HRTIM_WaveformSetOutputLevel(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t Output, uint32_t OutputLevel)
Forces the timer output to its active or inactive state.
#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA)
#define HRTIM_COMPAREUNIT_4
#define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)
void HRTIM_SimpleCaptureStop(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CaptureChannel)
Disables a basic capture on the designed capture unit.
static void HRTIM_MasterWaveform_Config(HRTIM_TypeDef *HRTIMx, HRTIM_TimerInitTypeDef *TimerInit)
Configures the master timer in waveform mode.
Definition: stm32f4xx.h:706
void HRTIM_WaveformCaptureConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CaptureUnit, HRTIM_CaptureCfgTypeDef *pCaptureCfg)
Configures the capture unit of a timer operating in waveform mode.
void HRTIM_FaultConfig(HRTIM_TypeDef *HRTIMx, HRTIM_FaultCfgTypeDef *pFaultCfg, uint32_t Fault)
Configures the conditioning of fault input.
#define HRTIM_EVENT_8
#define HRTIM_TIMERINDEX_TIMER_C
#define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)
enum FlagStatus ITStatus
#define HRTIM_OUTPUT_TA2
#define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)
void HRTIM_WaveformCounterStop(HRTIM_TypeDef *HRTIMx, uint32_t TimersToStop)
Stops the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed)...
#define HRTIM_TIMEVENTFILTER_NONE
static void HRTIM_MasterBase_Config(HRTIM_TypeDef *HRTIMx, HRTIM_BaseInitTypeDef *HRTIM_BaseInitStruc)
Configures the master timer time base.
#define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)
Output configuration definition.
#define IS_HRTIM_TIMERBURSTMODE(TIMERBURSTMODE)
#define HRTIM_EVENT_4
#define HRTIM_TIMERID_TIMER_D
#define HRTIM_TIMERINDEX_TIMER_B
#define IS_HRTIM_HALFMODE(HALFMODE)
Compare unit configuration definition.
#define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)
#define HRTIM_OUTPUTSET_TIMPER
#define HRTIM_OUTPUTRESET_TIMCMP1
#define HRTIM_TIMERID_TIMER_B
#define HRTIM_TIMERINDEX_TIMER_D
#define IS_HRTIM_OUTPUTIDLESTATE(OUTPUTIDLESTATE)
#define HRTIM_CAPTUREUNIT_1
void HRTIM_SimpleOnePulseStop(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t OnePulseChannel)
Disables the basic one pulse signal generation on the designed output.
#define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)
static void HRTIM_ExternalEventConfig(HRTIM_TypeDef *HRTIMx, uint32_t Event, HRTIM_EventCfgTypeDef *EventCfg)
Configures an external event channel.
This file contains all the functions prototypes for the HRTIM firmware library.
void HRTIM_SimplePWM_Init(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef *HRTIM_BaseInitStruct)
Initializes the HRTIMx timer in basic PWM mode.
void HRTIM_ITConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT, FunctionalState NewState)
Enables or disables the Master and slaves interrupt request.
ADC trigger configuration definition.
void HRTIM_MasterSetCompare(HRTIM_TypeDef *HRTIMx, uint32_t CompareUnit, uint32_t Compare)
Sets the HRTIMx Master Comparex Register value.
#define HRTIM_TIMRESETTRIGGER_EEV_3
#define HRTIM_CAPTURETRIGGER_EEV_3
void HRTIM_SimpleOnePulseStart(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t OnePulseChannel)
Enables the basic one pulse signal generation on the designed output.
#define HRTIM_AUTODELAYEDMODE_REGULAR
void HRTIM_WaveformTimerConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_TimerCfgTypeDef *pTimerCfg)
Configures the general behavior of a timer operating in waveform mode.
void HRTIM_ClearCommonITPendingBit(HRTIM_TypeDef *HRTIMx, uint32_t HRTIM_CommonIT)
Clears the common interrupt pending bits.
void HRTIM_SimpleBaseStart(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx)
Starts the counter of a timer operating in basic time base mode.
#define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)
#define HRTIM_TIMERID_MASTER
#define IS_HRTIM_EVENT(EVENT)
void HRTIM_WaveformOutputStop(HRTIM_TypeDef *HRTIMx, uint32_t OutputsToStop)
Disables the generation of the waveform signal on the designated output(s) Outputs can be combined (O...
Burst mode configuration definition.
#define HRTIM_ADCTRIGGER_4
#define HRTIM_EVENT_7
#define HRTIM_CAPTURETRIGGER_EEV_9
Basic output compare mode configuration definition.
#define IS_HRTIM_FAULTFILTER(FAULTFILTER)
void HRTIM_WaveformOutputConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t Output, HRTIM_OutputCfgTypeDef *pOutputCfg)
Configures the output of a timer operating in waveform mode.
#define HRTIM_TIMRESETTRIGGER_EEV_8
#define HRTIM_CAPTURETRIGGER_EEV_6
#define HRTIM_OUTPUT_TC2
Basic PWM output mode configuration definition.
#define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)
External event filtering in timing units configuration definition.
void HRTIM_SimpleBase_Init(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef *HRTIM_BaseInitStruct)
Initializes the HRTIMx timer in basic time base mode.
void HRTIM_TimerEventFilteringConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t Event, HRTIM_TimerEventFilteringCfgTypeDef *pTimerEventFilteringCfg)
Configures the event filtering capabilities of a timer (blanking, windowing)
#define IS_HRTIM_EVENTPOLARITY(EVENTPOLARITY)
uint32_t HRTIM_WaveformGetOutputLevel(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t Output)
Returns actual level (active or inactive) of the designated output.
void HRTIM_ADCTriggerConfig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrigger, HRTIM_ADCTriggerCfgTypeDef *pADCTriggerCfg)
Configures both the ADC trigger register update source and the ADC trigger source.
uint32_t HRTIM_WaveformGetOutputState(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t Output)
Returns actual state (RUN, IDLE, FAULT) of the designated output.
#define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)
void HRTIM_SynchronizationConfig(HRTIM_TypeDef *HRTIMx, HRTIM_SynchroCfgTypeDef *pSynchroCfg)
Configures the external input/output synchronization of the HRTIMx.
#define IS_HRTIM_OUTPUTFAULTSTATE(OUTPUTFAULTSTATE)
#define HRTIM_TIMRESETTRIGGER_EEV_4
#define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)
#define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)
#define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)
#define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)
#define HRTIM_BASICOCMODE_ACTIVE
#define RCC_APB2Periph_HRTIM1
#define HRTIM_OUTPUT_TB1
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
#define HRTIM_TIMRESETTRIGGER_EEV_10
#define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)
void HRTIM_SimplePWMStart(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t PWMChannel)
Starts the PWM output signal generation on the designed timer output.
#define HRTIM_CAPTURETRIGGER_EEV_8
#define IS_HRTIM_SYNCRESET(SYNCRESET)
#define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)
void HRTIM_BurstDMAConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t RegistersToUpdate)
Configures the burst DMA controller for a timer.
Basic One Pulse mode configuration definition.
#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1
void HRTIM_SoftwareUpdate(HRTIM_TypeDef *HRTIMx, uint32_t TimersToUpdate)
Triggers the update of the registers of one or several timers.
#define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)
void HRTIM_SlaveSetCompare(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CompareUnit, uint32_t Compare)
Sets the HRTIMx Slave Comparex Register value.
#define HRTIM_TIMERINDEX_TIMER_E
#define HRTIM_EVENT_6
#define HRTIM_CAPTUREUNIT_2
void HRTIM_SoftwareCapture(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CaptureUnit)
Triggers a software capture on the designed capture unit.
#define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)
#define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER)
#define HRTIM_TIMERID_TIMER_A
#define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)
#define HRTIM_TIMRESETTRIGGER_EEV_1
static void HRTIM_CaptureUnitConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CaptureUnit, uint32_t Event)
Configures a capture unit.
#define HRTIM_OUTPUT_TD1
#define IS_HRTIM_FAULT(FAULT)
#define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET)
#define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)
#define HRTIM_EVENTFASTMODE_DISABLE
#define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR
#define IS_HRTIM_PRELOAD(PRELOAD)
#define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)
#define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)
void HRTIM_SimpleOnePulse_Init(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef *HRTIM_BaseInitStruct)
Initializes the HRTIMx timer in basic one pulse mode.
#define HRTIM_ADCTRIGGER_3
#define HRTIM_OUTPUTSET_NONE
#define __HRTIM_ENABLE(__HANDLE__, __TIMERS__)
Enables or disables the timer counter(s)
#define HRTIM_EVENTSRC_1
#define HRTIM_TIMERINDEX_MASTER
#define IS_HRTIM_FAULTLOCK(FAULTLOCK)
ITStatus HRTIM_GetITStatus(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT)
Checks whether the specified HRTIM interrupt has occurred or not.
#define IS_HRTIM_SYNCSTART(SYNCSTART)
Fault channel configuration definition.
#define HRTIM_EVENT_1
void HRTIM_SoftwareReset(HRTIM_TypeDef *HRTIMx, uint32_t TimersToReset)
Triggers the reset of one or several timers.
ITStatus HRTIM_GetCommonITStatus(HRTIM_TypeDef *HRTIMx, uint32_t HRTIM_CommonIT)
Checks whether the specified HRTIM common interrupt has occurred or not.
#define HRTIM_UPDATEONREPETITION_ENABLED
#define HRTIM_EVENT_9
#define HRTIM_OUTPUTRESET_NONE
#define IS_HRTIM_EVENTFILTER(EVENTFILTER)
FlagStatus HRTIM_GetCommonFlagStatus(HRTIM_TypeDef *HRTIMx, uint32_t HRTIM_CommonFLAG)
Checks whether the specified HRTIM common flag is set or not.
void HRTIM_ClearCommonFlag(HRTIM_TypeDef *HRTIMx, uint32_t HRTIM_CommonFLAG)
Clears the common interrupt flags.
#define HRTIM_OUTPUTIDLEMODE_NONE
#define HRTIM_COMPAREUNIT_1
Basic capture mode configuration definition.
void HRTIM_DLLCalibrationStart(HRTIM_TypeDef *HRTIMx, uint32_t CalibrationRate)
Starts the DLL calibration.
static void HRTIM_TimingUnitWaveform_Config(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_TimerInitTypeDef *TimerInit)
Configures timing unit (timer A to timer E) in waveform mode.
void HRTIM_WaveformOutputStart(HRTIM_TypeDef *HRTIMx, uint32_t OutputsToStart)
Enables the generation of the waveform signal on the designated output(s) Outputs can be combined (OR...
#define HRTIM_FAULT_4
void HRTIM_BurstModeConfig(HRTIM_TypeDef *HRTIMx, HRTIM_BurstModeCfgTypeDef *pBurstModeCfg)
Configures the burst mode feature of the HRTIMx.
#define IS_HRTIM_TIMERINDEX(TIMERINDEX)
static void HRTIM_CompareUnitConfig(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CompareUnit, HRTIM_CompareCfgTypeDef *CompareCfg)
Configures a compare unit.
void HRTIM_SimpleOCStart(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t OCChannel)
Starts the output compare signal generation on the designed timer output.
#define HRTIM_EVENT_10
#define HRTIM_FAULT_3
uint32_t HRTIM_GetCapturedValue(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CaptureUnit)
Returns actual value of the capture register of the designated capture unit.
#define IS_HRTIM_EVENTFASTMODE(EVENTFASTMODE)
static uint32_t TimerIdxToTimerId[]
#define IS_HRTIM_TIMING_UNIT(TIMERINDEX)
#define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER)
void HRTIM_ClearITPendingBit(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT)
Clears the Master and slaves interrupt request pending bits.
#define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)
#define HRTIM_OUTPUT_TB2
#define HRTIM_SINGLE_CALIBRATION
#define HRTIM_TIMRESETTRIGGER_EEV_5
uint32_t HRTIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx)
Indicates on which output the signal is currently active (when the push pull mode is enabled) ...
#define HRTIM_OUTPUTSET_TIMCMP2
#define HRTIM_OUTPUTFAULTSTATE_NONE
#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3
#define HRTIM_CAPTURETRIGGER_NONE
#define HRTIM_TIMRESETTRIGGER_EEV_7
void HRTIM_SimpleCapture_Init(HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef *HRTIM_BaseInitStruct)
Initializes a timer operating in basic capture mode.


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19