stm32f30x_can.c
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1 
70 /* Includes ------------------------------------------------------------------*/
71 #include "stm32f30x_can.h"
72 #include "stm32f30x_rcc.h"
73 
82 /* Private typedef -----------------------------------------------------------*/
83 /* Private define ------------------------------------------------------------*/
84 
85 /* CAN Master Control Register bits */
86 #define MCR_DBF ((uint32_t)0x00010000) /* software master reset */
87 
88 /* CAN Mailbox Transmit Request */
89 #define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */
90 
91 /* CAN Filter Master Register bits */
92 #define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */
93 
94 /* Time out for INAK bit */
95 #define INAK_TIMEOUT ((uint32_t)0x00FFFFFF)
96 /* Time out for SLAK bit */
97 #define SLAK_TIMEOUT ((uint32_t)0x00FFFFFF)
98 
99 /* Flags in TSR register */
100 #define CAN_FLAGS_TSR ((uint32_t)0x08000000)
101 /* Flags in RF1R register */
102 #define CAN_FLAGS_RF1R ((uint32_t)0x04000000)
103 /* Flags in RF0R register */
104 #define CAN_FLAGS_RF0R ((uint32_t)0x02000000)
105 /* Flags in MSR register */
106 #define CAN_FLAGS_MSR ((uint32_t)0x01000000)
107 /* Flags in ESR register */
108 #define CAN_FLAGS_ESR ((uint32_t)0x00F00000)
109 
110 /* Mailboxes definition */
111 #define CAN_TXMAILBOX_0 ((uint8_t)0x00)
112 #define CAN_TXMAILBOX_1 ((uint8_t)0x01)
113 #define CAN_TXMAILBOX_2 ((uint8_t)0x02)
114 
115 #define CAN_MODE_MASK ((uint32_t) 0x00000003)
116 
117 /* Private macro -------------------------------------------------------------*/
118 /* Private variables ---------------------------------------------------------*/
119 /* Private function prototypes -----------------------------------------------*/
120 /* Private functions ---------------------------------------------------------*/
121 static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
122 
153 {
154  /* Check the parameters */
156 
157  /* Enable CAN1 reset state */
159  /* Release CAN1 from reset state */
161 }
162 
172 uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
173 {
174  uint8_t InitStatus = CAN_InitStatus_Failed;
175  __IO uint32_t wait_ack = 0x00000000;
176  /* Check the parameters */
178  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
179  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
180  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
181  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
182  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
183  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
184  assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
185  assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
186  assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
187  assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
188  assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
189 
190  /* Exit from sleep mode */
191  CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
192 
193  /* Request initialisation */
194  CANx->MCR |= CAN_MCR_INRQ ;
195 
196  /* Wait the acknowledge */
197  while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
198  {
199  wait_ack++;
200  }
201 
202  /* Check acknowledge */
203  if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
204  {
205  InitStatus = CAN_InitStatus_Failed;
206  }
207  else
208  {
209  /* Set the time triggered communication mode */
210  if (CAN_InitStruct->CAN_TTCM == ENABLE)
211  {
212  CANx->MCR |= CAN_MCR_TTCM;
213  }
214  else
215  {
216  CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;
217  }
218 
219  /* Set the automatic bus-off management */
220  if (CAN_InitStruct->CAN_ABOM == ENABLE)
221  {
222  CANx->MCR |= CAN_MCR_ABOM;
223  }
224  else
225  {
226  CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;
227  }
228 
229  /* Set the automatic wake-up mode */
230  if (CAN_InitStruct->CAN_AWUM == ENABLE)
231  {
232  CANx->MCR |= CAN_MCR_AWUM;
233  }
234  else
235  {
236  CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;
237  }
238 
239  /* Set the no automatic retransmission */
240  if (CAN_InitStruct->CAN_NART == ENABLE)
241  {
242  CANx->MCR |= CAN_MCR_NART;
243  }
244  else
245  {
246  CANx->MCR &= ~(uint32_t)CAN_MCR_NART;
247  }
248 
249  /* Set the receive FIFO locked mode */
250  if (CAN_InitStruct->CAN_RFLM == ENABLE)
251  {
252  CANx->MCR |= CAN_MCR_RFLM;
253  }
254  else
255  {
256  CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;
257  }
258 
259  /* Set the transmit FIFO priority */
260  if (CAN_InitStruct->CAN_TXFP == ENABLE)
261  {
262  CANx->MCR |= CAN_MCR_TXFP;
263  }
264  else
265  {
266  CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;
267  }
268 
269  /* Set the bit timing register */
270  CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
271  ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
272  ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
273  ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
274  ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
275 
276  /* Request leave initialisation */
277  CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
278 
279  /* Wait the acknowledge */
280  wait_ack = 0;
281 
282  while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
283  {
284  wait_ack++;
285  }
286 
287  /* ...and check acknowledged */
288  if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
289  {
290  InitStatus = CAN_InitStatus_Failed;
291  }
292  else
293  {
294  InitStatus = CAN_InitStatus_Success ;
295  }
296  }
297 
298  /* At this step, return the status of initialization */
299  return InitStatus;
300 }
301 
309 void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
310 {
311  uint32_t filter_number_bit_pos = 0;
312  /* Check the parameters */
313  assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
314  assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
315  assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
317  assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
318 
319  filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
320 
321  /* Initialisation mode for the filter */
322  CAN1->FMR |= FMR_FINIT;
323 
324  /* Filter Deactivation */
325  CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;
326 
327  /* Filter Scale */
328  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
329  {
330  /* 16-bit scale for the filter */
331  CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;
332 
333  /* First 16-bit identifier and First 16-bit mask */
334  /* Or First 16-bit identifier and Second 16-bit identifier */
335  CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
336  ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
337  (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
338 
339  /* Second 16-bit identifier and Second 16-bit mask */
340  /* Or Third 16-bit identifier and Fourth 16-bit identifier */
341  CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
342  ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
343  (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
344  }
345 
346  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
347  {
348  /* 32-bit scale for the filter */
349  CAN1->FS1R |= filter_number_bit_pos;
350  /* 32-bit identifier or First 32-bit identifier */
351  CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
352  ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
353  (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
354  /* 32-bit mask or Second 32-bit identifier */
355  CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
356  ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
357  (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
358  }
359 
360  /* Filter Mode */
361  if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
362  {
363  /*Id/Mask mode for the filter*/
364  CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;
365  }
366  else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
367  {
368  /*Identifier list mode for the filter*/
369  CAN1->FM1R |= (uint32_t)filter_number_bit_pos;
370  }
371 
372  /* Filter FIFO assignment */
373  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
374  {
375  /* FIFO 0 assignation for the filter */
376  CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;
377  }
378 
379  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
380  {
381  /* FIFO 1 assignation for the filter */
382  CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;
383  }
384 
385  /* Filter activation */
386  if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
387  {
388  CAN1->FA1R |= filter_number_bit_pos;
389  }
390 
391  /* Leave the initialisation mode for the filter */
392  CAN1->FMR &= ~FMR_FINIT;
393 }
394 
400 void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
401 {
402  /* Reset CAN init structure parameters values */
403 
404  /* Initialize the time triggered communication mode */
405  CAN_InitStruct->CAN_TTCM = DISABLE;
406 
407  /* Initialize the automatic bus-off management */
408  CAN_InitStruct->CAN_ABOM = DISABLE;
409 
410  /* Initialize the automatic wake-up mode */
411  CAN_InitStruct->CAN_AWUM = DISABLE;
412 
413  /* Initialize the no automatic retransmission */
414  CAN_InitStruct->CAN_NART = DISABLE;
415 
416  /* Initialize the receive FIFO locked mode */
417  CAN_InitStruct->CAN_RFLM = DISABLE;
418 
419  /* Initialize the transmit FIFO priority */
420  CAN_InitStruct->CAN_TXFP = DISABLE;
421 
422  /* Initialize the CAN_Mode member */
423  CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
424 
425  /* Initialize the CAN_SJW member */
426  CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
427 
428  /* Initialize the CAN_BS1 member */
429  CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
430 
431  /* Initialize the CAN_BS2 member */
432  CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
433 
434  /* Initialize the CAN_Prescaler member */
435  CAN_InitStruct->CAN_Prescaler = 1;
436 }
437 
443 void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
444 {
445  /* Check the parameters */
446  assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
447 
448  /* Enter Initialisation mode for the filter */
449  CAN1->FMR |= FMR_FINIT;
450 
451  /* Select the start slave bank */
452  CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;
453  CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;
454 
455  /* Leave Initialisation mode for the filter */
456  CAN1->FMR &= ~FMR_FINIT;
457 }
458 
469 {
470  /* Check the parameters */
473 
474  if (NewState != DISABLE)
475  {
476  /* Enable Debug Freeze */
477  CANx->MCR |= MCR_DBF;
478  }
479  else
480  {
481  /* Disable Debug Freeze */
482  CANx->MCR &= ~MCR_DBF;
483  }
484 }
485 
498 {
499  /* Check the parameters */
502  if (NewState != DISABLE)
503  {
504  /* Enable the TTCM mode */
505  CANx->MCR |= CAN_MCR_TTCM;
506 
507  /* Set TGT bits */
508  CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT);
509  CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT);
510  CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT);
511  }
512  else
513  {
514  /* Disable the TTCM mode */
515  CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM);
516 
517  /* Reset TGT bits */
518  CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT);
519  CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT);
520  CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT);
521  }
522 }
551 uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
552 {
553  uint8_t transmit_mailbox = 0;
554  /* Check the parameters */
556  assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
557  assert_param(IS_CAN_RTR(TxMessage->RTR));
558  assert_param(IS_CAN_DLC(TxMessage->DLC));
559 
560  /* Select one empty transmit mailbox */
561  if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
562  {
563  transmit_mailbox = 0;
564  }
565  else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
566  {
567  transmit_mailbox = 1;
568  }
569  else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
570  {
571  transmit_mailbox = 2;
572  }
573  else
574  {
575  transmit_mailbox = CAN_TxStatus_NoMailBox;
576  }
577 
578  if (transmit_mailbox != CAN_TxStatus_NoMailBox)
579  {
580  /* Set up the Id */
581  CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
582  if (TxMessage->IDE == CAN_Id_Standard)
583  {
584  assert_param(IS_CAN_STDID(TxMessage->StdId));
585  CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \
586  TxMessage->RTR);
587  }
588  else
589  {
590  assert_param(IS_CAN_EXTID(TxMessage->ExtId));
591  CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \
592  TxMessage->IDE | \
593  TxMessage->RTR);
594  }
595 
596  /* Set up the DLC */
597  TxMessage->DLC &= (uint8_t)0x0000000F;
598  CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
599  CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;
600 
601  /* Set up the data field */
602  CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) |
603  ((uint32_t)TxMessage->Data[2] << 16) |
604  ((uint32_t)TxMessage->Data[1] << 8) |
605  ((uint32_t)TxMessage->Data[0]));
606  CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) |
607  ((uint32_t)TxMessage->Data[6] << 16) |
608  ((uint32_t)TxMessage->Data[5] << 8) |
609  ((uint32_t)TxMessage->Data[4]));
610  /* Request transmission */
611  CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;
612  }
613  return transmit_mailbox;
614 }
615 
623 uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
624 {
625  uint32_t state = 0;
626 
627  /* Check the parameters */
629  assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
630 
631  switch (TransmitMailbox)
632  {
633  case (CAN_TXMAILBOX_0):
634  state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0);
635  break;
636  case (CAN_TXMAILBOX_1):
637  state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1);
638  break;
639  case (CAN_TXMAILBOX_2):
640  state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2);
641  break;
642  default:
643  state = CAN_TxStatus_Failed;
644  break;
645  }
646  switch (state)
647  {
648  /* transmit pending */
649  case (0x0): state = CAN_TxStatus_Pending;
650  break;
651  /* transmit failed */
653  break;
655  break;
657  break;
658  /* transmit succeeded */
660  break;
662  break;
664  break;
665  default: state = CAN_TxStatus_Failed;
666  break;
667  }
668  return (uint8_t) state;
669 }
670 
677 void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
678 {
679  /* Check the parameters */
682  /* abort transmission */
683  switch (Mailbox)
684  {
685  case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0;
686  break;
687  case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1;
688  break;
689  case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2;
690  break;
691  default:
692  break;
693  }
694 }
724 void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
725 {
726  /* Check the parameters */
728  assert_param(IS_CAN_FIFO(FIFONumber));
729  /* Get the Id */
730  RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
731  if (RxMessage->IDE == CAN_Id_Standard)
732  {
733  RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
734  }
735  else
736  {
737  RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
738  }
739 
740  RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
741  /* Get the DLC */
742  RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
743  /* Get the FMI */
744  RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
745  /* Get the data field */
746  RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
747  RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
748  RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
749  RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
750  RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
751  RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
752  RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
753  RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
754  /* Release the FIFO */
755  /* Release FIFO0 */
756  if (FIFONumber == CAN_FIFO0)
757  {
758  CANx->RF0R |= CAN_RF0R_RFOM0;
759  }
760  /* Release FIFO1 */
761  else /* FIFONumber == CAN_FIFO1 */
762  {
763  CANx->RF1R |= CAN_RF1R_RFOM1;
764  }
765 }
766 
773 void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
774 {
775  /* Check the parameters */
777  assert_param(IS_CAN_FIFO(FIFONumber));
778  /* Release FIFO0 */
779  if (FIFONumber == CAN_FIFO0)
780  {
781  CANx->RF0R |= CAN_RF0R_RFOM0;
782  }
783  /* Release FIFO1 */
784  else /* FIFONumber == CAN_FIFO1 */
785  {
786  CANx->RF1R |= CAN_RF1R_RFOM1;
787  }
788 }
789 
796 uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
797 {
798  uint8_t message_pending=0;
799  /* Check the parameters */
801  assert_param(IS_CAN_FIFO(FIFONumber));
802  if (FIFONumber == CAN_FIFO0)
803  {
804  message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
805  }
806  else if (FIFONumber == CAN_FIFO1)
807  {
808  message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
809  }
810  else
811  {
812  message_pending = 0;
813  }
814  return message_pending;
815 }
846 uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)
847 {
848  uint8_t status = CAN_ModeStatus_Failed;
849 
850  /* Timeout for INAK or also for SLAK bits*/
851  uint32_t timeout = INAK_TIMEOUT;
852 
853  /* Check the parameters */
855  assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
856 
857  if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
858  {
859  /* Request initialisation */
860  CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ);
861 
862  /* Wait the acknowledge */
863  while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))
864  {
865  timeout--;
866  }
867  if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
868  {
869  status = CAN_ModeStatus_Failed;
870  }
871  else
872  {
873  status = CAN_ModeStatus_Success;
874  }
875  }
876  else if (CAN_OperatingMode == CAN_OperatingMode_Normal)
877  {
878  /* Request leave initialisation and sleep mode and enter Normal mode */
879  CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));
880 
881  /* Wait the acknowledge */
882  while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))
883  {
884  timeout--;
885  }
886  if ((CANx->MSR & CAN_MODE_MASK) != 0)
887  {
888  status = CAN_ModeStatus_Failed;
889  }
890  else
891  {
892  status = CAN_ModeStatus_Success;
893  }
894  }
895  else if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
896  {
897  /* Request Sleep mode */
898  CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
899 
900  /* Wait the acknowledge */
901  while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))
902  {
903  timeout--;
904  }
905  if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
906  {
907  status = CAN_ModeStatus_Failed;
908  }
909  else
910  {
911  status = CAN_ModeStatus_Success;
912  }
913  }
914  else
915  {
916  status = CAN_ModeStatus_Failed;
917  }
918 
919  return (uint8_t) status;
920 }
921 
927 uint8_t CAN_Sleep(CAN_TypeDef* CANx)
928 {
929  uint8_t sleepstatus = CAN_Sleep_Failed;
930 
931  /* Check the parameters */
933 
934  /* Request Sleep mode */
935  CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
936 
937  /* Sleep mode status */
938  if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
939  {
940  /* Sleep mode not entered */
941  sleepstatus = CAN_Sleep_Ok;
942  }
943  /* return sleep mode status */
944  return (uint8_t)sleepstatus;
945 }
946 
952 uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
953 {
954  uint32_t wait_slak = SLAK_TIMEOUT;
955  uint8_t wakeupstatus = CAN_WakeUp_Failed;
956 
957  /* Check the parameters */
959 
960  /* Wake up request */
961  CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
962 
963  /* Sleep mode status */
964  while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
965  {
966  wait_slak--;
967  }
968  if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
969  {
970  /* wake up done : Sleep mode exited */
971  wakeupstatus = CAN_WakeUp_Ok;
972  }
973  /* return wakeup status */
974  return (uint8_t)wakeupstatus;
975 }
1015 {
1016  uint8_t errorcode=0;
1017 
1018  /* Check the parameters */
1020 
1021  /* Get the error code*/
1022  errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC);
1023 
1024  /* Return the error code*/
1025  return errorcode;
1026 }
1027 
1040 {
1041  uint8_t counter=0;
1042 
1043  /* Check the parameters */
1045 
1046  /* Get the Receive Error Counter*/
1047  counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24);
1048 
1049  /* Return the Receive Error Counter*/
1050  return counter;
1051 }
1052 
1053 
1060 {
1061  uint8_t counter=0;
1062 
1063  /* Check the parameters */
1065 
1066  /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
1067  counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16);
1068 
1069  /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
1070  return counter;
1071 }
1218 void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
1219 {
1220  /* Check the parameters */
1222  assert_param(IS_CAN_IT(CAN_IT));
1223  assert_param(IS_FUNCTIONAL_STATE(NewState));
1224 
1225  if (NewState != DISABLE)
1226  {
1227  /* Enable the selected CANx interrupt */
1228  CANx->IER |= CAN_IT;
1229  }
1230  else
1231  {
1232  /* Disable the selected CANx interrupt */
1233  CANx->IER &= ~CAN_IT;
1234  }
1235 }
1258 FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
1259 {
1260  FlagStatus bitstatus = RESET;
1261 
1262  /* Check the parameters */
1264  assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
1265 
1266 
1267  if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)
1268  {
1269  /* Check the status of the specified CAN flag */
1270  if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
1271  {
1272  /* CAN_FLAG is set */
1273  bitstatus = SET;
1274  }
1275  else
1276  {
1277  /* CAN_FLAG is reset */
1278  bitstatus = RESET;
1279  }
1280  }
1281  else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)
1282  {
1283  /* Check the status of the specified CAN flag */
1284  if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
1285  {
1286  /* CAN_FLAG is set */
1287  bitstatus = SET;
1288  }
1289  else
1290  {
1291  /* CAN_FLAG is reset */
1292  bitstatus = RESET;
1293  }
1294  }
1295  else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)
1296  {
1297  /* Check the status of the specified CAN flag */
1298  if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
1299  {
1300  /* CAN_FLAG is set */
1301  bitstatus = SET;
1302  }
1303  else
1304  {
1305  /* CAN_FLAG is reset */
1306  bitstatus = RESET;
1307  }
1308  }
1309  else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)
1310  {
1311  /* Check the status of the specified CAN flag */
1312  if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
1313  {
1314  /* CAN_FLAG is set */
1315  bitstatus = SET;
1316  }
1317  else
1318  {
1319  /* CAN_FLAG is reset */
1320  bitstatus = RESET;
1321  }
1322  }
1323  else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */
1324  {
1325  /* Check the status of the specified CAN flag */
1326  if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
1327  {
1328  /* CAN_FLAG is set */
1329  bitstatus = SET;
1330  }
1331  else
1332  {
1333  /* CAN_FLAG is reset */
1334  bitstatus = RESET;
1335  }
1336  }
1337  /* Return the CAN_FLAG status */
1338  return bitstatus;
1339 }
1340 
1358 void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
1359 {
1360  uint32_t flagtmp=0;
1361  /* Check the parameters */
1363  assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
1364 
1365  if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */
1366  {
1367  /* Clear the selected CAN flags */
1368  CANx->ESR = (uint32_t)RESET;
1369  }
1370  else /* MSR or TSR or RF0R or RF1R */
1371  {
1372  flagtmp = CAN_FLAG & 0x000FFFFF;
1373 
1374  if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)
1375  {
1376  /* Receive Flags */
1377  CANx->RF0R = (uint32_t)(flagtmp);
1378  }
1379  else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)
1380  {
1381  /* Receive Flags */
1382  CANx->RF1R = (uint32_t)(flagtmp);
1383  }
1384  else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)
1385  {
1386  /* Transmit Flags */
1387  CANx->TSR = (uint32_t)(flagtmp);
1388  }
1389  else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */
1390  {
1391  /* Operating mode Flags */
1392  CANx->MSR = (uint32_t)(flagtmp);
1393  }
1394  }
1395 }
1396 
1418 ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
1419 {
1420  ITStatus itstatus = RESET;
1421  /* Check the parameters */
1423  assert_param(IS_CAN_IT(CAN_IT));
1424 
1425  /* check the interrupt enable bit */
1426  if((CANx->IER & CAN_IT) != RESET)
1427  {
1428  /* in case the Interrupt is enabled, .... */
1429  switch (CAN_IT)
1430  {
1431  case CAN_IT_TME:
1432  /* Check CAN_TSR_RQCPx bits */
1434  break;
1435  case CAN_IT_FMP0:
1436  /* Check CAN_RF0R_FMP0 bit */
1437  itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);
1438  break;
1439  case CAN_IT_FF0:
1440  /* Check CAN_RF0R_FULL0 bit */
1441  itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);
1442  break;
1443  case CAN_IT_FOV0:
1444  /* Check CAN_RF0R_FOVR0 bit */
1445  itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);
1446  break;
1447  case CAN_IT_FMP1:
1448  /* Check CAN_RF1R_FMP1 bit */
1449  itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);
1450  break;
1451  case CAN_IT_FF1:
1452  /* Check CAN_RF1R_FULL1 bit */
1453  itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);
1454  break;
1455  case CAN_IT_FOV1:
1456  /* Check CAN_RF1R_FOVR1 bit */
1457  itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);
1458  break;
1459  case CAN_IT_WKU:
1460  /* Check CAN_MSR_WKUI bit */
1461  itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);
1462  break;
1463  case CAN_IT_SLK:
1464  /* Check CAN_MSR_SLAKI bit */
1465  itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);
1466  break;
1467  case CAN_IT_EWG:
1468  /* Check CAN_ESR_EWGF bit */
1469  itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);
1470  break;
1471  case CAN_IT_EPV:
1472  /* Check CAN_ESR_EPVF bit */
1473  itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);
1474  break;
1475  case CAN_IT_BOF:
1476  /* Check CAN_ESR_BOFF bit */
1477  itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);
1478  break;
1479  case CAN_IT_LEC:
1480  /* Check CAN_ESR_LEC bit */
1481  itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);
1482  break;
1483  case CAN_IT_ERR:
1484  /* Check CAN_MSR_ERRI bit */
1485  itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI);
1486  break;
1487  default:
1488  /* in case of error, return RESET */
1489  itstatus = RESET;
1490  break;
1491  }
1492  }
1493  else
1494  {
1495  /* in case the Interrupt is not enabled, return RESET */
1496  itstatus = RESET;
1497  }
1498 
1499  /* Return the CAN_IT status */
1500  return itstatus;
1501 }
1502 
1522 void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
1523 {
1524  /* Check the parameters */
1526  assert_param(IS_CAN_CLEAR_IT(CAN_IT));
1527 
1528  switch (CAN_IT)
1529  {
1530  case CAN_IT_TME:
1531  /* Clear CAN_TSR_RQCPx (rc_w1)*/
1533  break;
1534  case CAN_IT_FF0:
1535  /* Clear CAN_RF0R_FULL0 (rc_w1)*/
1536  CANx->RF0R = CAN_RF0R_FULL0;
1537  break;
1538  case CAN_IT_FOV0:
1539  /* Clear CAN_RF0R_FOVR0 (rc_w1)*/
1540  CANx->RF0R = CAN_RF0R_FOVR0;
1541  break;
1542  case CAN_IT_FF1:
1543  /* Clear CAN_RF1R_FULL1 (rc_w1)*/
1544  CANx->RF1R = CAN_RF1R_FULL1;
1545  break;
1546  case CAN_IT_FOV1:
1547  /* Clear CAN_RF1R_FOVR1 (rc_w1)*/
1548  CANx->RF1R = CAN_RF1R_FOVR1;
1549  break;
1550  case CAN_IT_WKU:
1551  /* Clear CAN_MSR_WKUI (rc_w1)*/
1552  CANx->MSR = CAN_MSR_WKUI;
1553  break;
1554  case CAN_IT_SLK:
1555  /* Clear CAN_MSR_SLAKI (rc_w1)*/
1556  CANx->MSR = CAN_MSR_SLAKI;
1557  break;
1558  case CAN_IT_EWG:
1559  /* Clear CAN_MSR_ERRI (rc_w1) */
1560  CANx->MSR = CAN_MSR_ERRI;
1561  /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
1562  break;
1563  case CAN_IT_EPV:
1564  /* Clear CAN_MSR_ERRI (rc_w1) */
1565  CANx->MSR = CAN_MSR_ERRI;
1566  /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
1567  break;
1568  case CAN_IT_BOF:
1569  /* Clear CAN_MSR_ERRI (rc_w1) */
1570  CANx->MSR = CAN_MSR_ERRI;
1571  /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
1572  break;
1573  case CAN_IT_LEC:
1574  /* Clear LEC bits */
1575  CANx->ESR = RESET;
1576  /* Clear CAN_MSR_ERRI (rc_w1) */
1577  CANx->MSR = CAN_MSR_ERRI;
1578  break;
1579  case CAN_IT_ERR:
1580  /*Clear LEC bits */
1581  CANx->ESR = RESET;
1582  /* Clear CAN_MSR_ERRI (rc_w1) */
1583  CANx->MSR = CAN_MSR_ERRI;
1584  /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/
1585  break;
1586  default:
1587  break;
1588  }
1589 }
1600 static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
1601 {
1602  ITStatus pendingbitstatus = RESET;
1603 
1604  if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
1605  {
1606  /* CAN_IT is set */
1607  pendingbitstatus = SET;
1608  }
1609  else
1610  {
1611  /* CAN_IT is reset */
1612  pendingbitstatus = RESET;
1613  }
1614  return pendingbitstatus;
1615 }
1616 
1629 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
#define CAN_RF1R_FULL1
Definition: stm32f4xx.h:2610
#define CAN_TSR_RQCP2
Definition: stm32f4xx.h:2585
#define IS_CAN_BANKNUMBER(BANKNUMBER)
void CAN_ClearITPendingBit(CAN_TypeDef *CANx, uint32_t CAN_IT)
Clears the CANx&#39;s interrupt pending bits.
#define CAN_TXMAILBOX_0
FlagStatus
Definition: stm32f4xx.h:706
#define IS_CAN_FILTER_FIFO(FIFO)
#define CAN_TSR_RQCP0
Definition: stm32f4xx.h:2575
#define MCR_DBF
Definition: stm32f30x_can.c:86
#define CAN_MSR_WKUI
Definition: stm32f4xx.h:2567
uint8_t IDE
#define CAN_TSR_TXOK1
Definition: stm32f4xx.h:2581
#define CAN_RF1R_FOVR1
Definition: stm32f4xx.h:2611
#define CAN_BS2_3tq
#define CAN_InitStatus_Failed
#define CAN_IT_FOV1
#define CAN_MCR_SLEEP
Definition: stm32f4xx.h:2554
CAN init structure definition.
Definition: stm32f4xx_can.h:56
uint8_t RTR
FunctionalState
Definition: stm32f4xx.h:708
#define CAN_RF0R_FOVR0
Definition: stm32f4xx.h:2605
uint8_t CAN_Init(CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct)
Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.
#define CAN_IT_FMP1
#define IS_CAN_OPERATING_MODE(MODE)
ITStatus CAN_GetITStatus(CAN_TypeDef *CANx, uint32_t CAN_IT)
Checks whether the specified CANx interrupt has occurred or not.
#define CAN_IT_EPV
#define CAN_IT_BOF
FunctionalState CAN_FilterActivation
This file contains all the functions prototypes for the CAN firmware library.
__IO uint32_t RDTR
Definition: stm32f4xx.h:777
void CAN_DeInit(CAN_TypeDef *CANx)
Deinitializes the CAN peripheral registers to their default reset values.
#define CAN_FLAGS_MSR
#define CAN_Sleep_Failed
#define CAN_FIFO0
#define CAN_RF0R_FULL0
Definition: stm32f4xx.h:2604
FunctionalState CAN_TTCM
Definition: stm32f4xx_can.h:76
__IO uint32_t RDLR
Definition: stm32f4xx.h:778
FunctionalState CAN_AWUM
Definition: stm32f4xx_can.h:82
uint8_t FMI
#define CAN_IT_FMP0
#define CAN_Filter_FIFO0
uint8_t Data[8]
#define CAN_RF0R_FMP0
Definition: stm32f4xx.h:2603
#define CAN_WakeUp_Ok
#define CAN_FLAGS_RF1R
FunctionalState CAN_TXFP
Definition: stm32f4xx_can.h:91
#define CAN_RF1R_RFOM1
Definition: stm32f4xx.h:2612
#define CAN_ESR_BOFF
Definition: stm32f4xx.h:2633
void assert_param(int val)
FunctionalState CAN_NART
Definition: stm32f4xx_can.h:85
static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
Checks whether the CAN interrupt has occurred or not.
#define IS_CAN_BS2(BS2)
#define CAN_OperatingMode_Normal
#define CAN_MCR_ABOM
Definition: stm32f4xx.h:2559
__IO uint32_t TDLR
Definition: stm32f4xx.h:766
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
#define IS_CAN_IT(IT)
#define INAK_TIMEOUT
Definition: stm32f30x_can.c:95
#define CAN_TXMAILBOX_2
static volatile uint8_t * status
Definition: drv_i2c.c:102
#define IS_CAN_DLC(DLC)
uint8_t CAN_OperatingModeRequest(CAN_TypeDef *CANx, uint8_t CAN_OperatingMode)
Selects the CAN Operation mode.
#define IS_CAN_ALL_PERIPH(PERIPH)
Definition: stm32f4xx_can.h:50
#define CAN_IT_FF1
#define IS_CAN_GET_FLAG(FLAG)
#define CAN_ESR_EWGF
Definition: stm32f4xx.h:2631
Definition: stm32f4xx.h:706
FlagStatus CAN_GetFlagStatus(CAN_TypeDef *CANx, uint32_t CAN_FLAG)
Checks whether the specified CAN flag is set or not.
#define SLAK_TIMEOUT
Definition: stm32f30x_can.c:97
__IO uint32_t IER
Definition: stm32f4xx.h:803
uint8_t DLC
uint8_t CAN_MessagePending(CAN_TypeDef *CANx, uint8_t FIFONumber)
Returns the number of pending received messages.
#define CAN_FIFO1
__IO uint32_t TDHR
Definition: stm32f4xx.h:767
enum FlagStatus ITStatus
#define CAN_TSR_TME1
Definition: stm32f4xx.h:2594
#define CAN_MSR_INAK
Definition: stm32f4xx.h:2564
void CAN_DBGFreeze(CAN_TypeDef *CANx, FunctionalState NewState)
Enables or disables the DBG Freeze for CAN.
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
This file contains all the functions prototypes for the RCC firmware library.
#define CAN_TDT0R_TGT
Definition: stm32f4xx.h:2661
uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef *CANx)
Returns the CANx Receive Error Counter (REC).
#define CAN_BS1_4tq
__IO uint32_t RF0R
Definition: stm32f4xx.h:801
#define __IO
Definition: core_cm0.h:198
#define IS_CAN_MODE(MODE)
#define IS_CAN_CLEAR_FLAG(FLAG)
#define CAN_Sleep_Ok
#define CAN_IT_FOV0
#define IS_CAN_IDTYPE(IDTYPE)
#define CAN_IT_SLK
#define CAN_Filter_FIFO1
#define CAN_MSR_SLAK
Definition: stm32f4xx.h:2565
void CAN_FIFORelease(CAN_TypeDef *CANx, uint8_t FIFONumber)
Releases the specified receive FIFO.
uint8_t CAN_TransmitStatus(CAN_TypeDef *CANx, uint8_t TransmitMailbox)
Checks the transmission status of a CAN Frame.
#define CAN_MCR_NART
Definition: stm32f4xx.h:2557
#define CAN_OperatingMode_Sleep
#define CAN_ESR_EPVF
Definition: stm32f4xx.h:2632
#define CAN_TSR_ABRQ0
Definition: stm32f4xx.h:2579
#define CAN1
Definition: stm32f4xx.h:2069
void CAN_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage)
Receives a correct CAN frame.
#define IS_CAN_STDID(STDID)
#define CAN_TSR_RQCP1
Definition: stm32f4xx.h:2580
#define CAN_IT_FF0
#define CAN_TxStatus_NoMailBox
#define IS_CAN_CLEAR_IT(IT)
#define CAN_ESR_TEC
Definition: stm32f4xx.h:2640
uint8_t CAN_WakeUp(CAN_TypeDef *CANx)
Wakes up the CAN peripheral from sleep mode .
#define IS_CAN_FILTER_NUMBER(NUMBER)
uint8_t DLC
#define CAN_IT_EWG
#define CAN_TSR_ABRQ1
Definition: stm32f4xx.h:2584
#define TMIDxR_TXRQ
Definition: stm32f30x_can.c:89
FunctionalState CAN_RFLM
Definition: stm32f4xx_can.h:88
#define IS_CAN_EXTID(EXTID)
#define CAN_TxStatus_Pending
__IO uint32_t RDHR
Definition: stm32f4xx.h:779
__IO uint32_t TIR
Definition: stm32f4xx.h:764
#define FMR_FINIT
Definition: stm32f30x_can.c:92
#define CAN_IT_ERR
#define CAN_MCR_AWUM
Definition: stm32f4xx.h:2558
#define IS_CAN_PRESCALER(PRESCALER)
#define CAN_SJW_1tq
#define CAN_MSR_SLAKI
Definition: stm32f4xx.h:2568
#define CAN_MCR_TXFP
Definition: stm32f4xx.h:2555
#define CAN_MCR_TTCM
Definition: stm32f4xx.h:2560
__IO uint32_t RIR
Definition: stm32f4xx.h:776
void CAN_CancelTransmit(CAN_TypeDef *CANx, uint8_t Mailbox)
Cancels a transmit request.
void CAN_ClearFlag(CAN_TypeDef *CANx, uint32_t CAN_FLAG)
Clears the CAN&#39;s pending flags.
#define CAN_TDT2R_TGT
Definition: stm32f4xx.h:2709
__IO uint32_t TSR
Definition: stm32f4xx.h:800
#define IS_CAN_FILTER_SCALE(SCALE)
__IO uint32_t BTR
Definition: stm32f4xx.h:805
#define CAN_MCR_RFLM
Definition: stm32f4xx.h:2556
uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef *CANx)
Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
__IO uint32_t MCR
Definition: stm32f4xx.h:798
uint8_t RTR
void CAN_TTComModeCmd(CAN_TypeDef *CANx, FunctionalState NewState)
Enables or disables the CAN Time TriggerOperation communication mode.
#define CAN_IT_WKU
#define CAN_TxStatus_Failed
uint16_t CAN_FilterFIFOAssignment
#define CAN_FilterScale_32bit
uint32_t ExtId
#define CAN_ESR_LEC
Definition: stm32f4xx.h:2635
#define CAN_TSR_TME2
Definition: stm32f4xx.h:2595
void CAN_ITConfig(CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState)
Enables or disables the specified CANx interrupts.
void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
Select the start bank filter for slave CAN.
#define IS_CAN_FILTER_MODE(MODE)
#define CAN_RF0R_RFOM0
Definition: stm32f4xx.h:2606
#define CAN_TSR_TME0
Definition: stm32f4xx.h:2593
uint8_t CAN_GetLastErrorCode(CAN_TypeDef *CANx)
Returns the CANx&#39;s last error code (LEC).
#define CAN_TDT1R_TGT
Definition: stm32f4xx.h:2685
#define IS_CAN_SJW(SJW)
CAN filter init structure definition.
Definition: stm32f4xx_can.h:98
#define CAN_MODE_MASK
Controller Area Network.
Definition: stm32f4xx.h:796
uint16_t CAN_Prescaler
Definition: stm32f4xx_can.h:58
#define CAN_FLAGS_ESR
CAN Tx message structure definition.
#define CAN_MCR_INRQ
Definition: stm32f4xx.h:2553
uint32_t StdId
#define CAN_FLAGS_RF0R
uint8_t IDE
#define CAN_ModeStatus_Failed
__IO uint32_t MSR
Definition: stm32f4xx.h:799
uint8_t CAN_Sleep(CAN_TypeDef *CANx)
Enters the Sleep (low power) mode.
#define CAN_TXMAILBOX_1
#define CAN_WakeUp_Failed
uint32_t StdId
__IO uint32_t TDTR
Definition: stm32f4xx.h:765
#define CAN_Mode_Normal
CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]
Definition: stm32f4xx.h:808
#define CAN_FilterMode_IdMask
#define IS_CAN_FIFO(FIFO)
#define CAN_TSR_TXOK0
Definition: stm32f4xx.h:2576
#define CAN_TSR_ABRQ2
Definition: stm32f4xx.h:2589
#define CAN_Id_Standard
void CAN_FilterInit(CAN_FilterInitTypeDef *CAN_FilterInitStruct)
Configures the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct...
void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct)
Fills each CAN_InitStruct member with its default value.
#define CAN_TSR_TXOK2
Definition: stm32f4xx.h:2586
#define IS_CAN_BS1(BS1)
#define CAN_OperatingMode_Initialization
__IO uint32_t RF1R
Definition: stm32f4xx.h:802
FunctionalState CAN_ABOM
Definition: stm32f4xx_can.h:79
#define CAN_ModeStatus_Success
#define CAN_FLAG_LEC
#define CAN_ESR_REC
Definition: stm32f4xx.h:2641
#define CAN_InitStatus_Success
#define CAN_MSR_ERRI
Definition: stm32f4xx.h:2566
#define IS_CAN_RTR(RTR)
CAN_TxMailBox_TypeDef sTxMailBox[3]
Definition: stm32f4xx.h:807
#define CAN_TxStatus_Ok
__IO uint32_t ESR
Definition: stm32f4xx.h:804
#define CAN_FLAGS_TSR
uint32_t ExtId
uint8_t CAN_Transmit(CAN_TypeDef *CANx, CanTxMsg *TxMessage)
Initiates and transmits a CAN frame message.
#define CAN_IT_TME
#define CAN_RF1R_FMP1
Definition: stm32f4xx.h:2609
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX)
uint8_t Data[8]
CAN Rx message structure definition.
#define CAN_IT_LEC
#define CAN_FilterScale_16bit


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19