stm32f30x_adc.c
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1 
75 /* Includes ------------------------------------------------------------------*/
76 #include "stm32f30x_adc.h"
77 #include "stm32f30x_rcc.h"
78 
88 /* Private typedef -----------------------------------------------------------*/
89 /* Private define ------------------------------------------------------------*/
90 
91 /* CFGR register Mask */
92 #define CFGR_CLEAR_Mask ((uint32_t)0xFDFFC007)
93 
94 /* JSQR register Mask */
95 #define JSQR_CLEAR_Mask ((uint32_t)0x00000000)
96 
97 /* ADC ADON mask */
98 #define CCR_CLEAR_MASK ((uint32_t)0xFFFC10E0)
99 
100 /* ADC JDRx registers offset */
101 #define JDR_Offset ((uint8_t)0x80)
102 
103 /* Private macro -------------------------------------------------------------*/
104 /* Private variables ---------------------------------------------------------*/
105 /* Private function prototypes -----------------------------------------------*/
106 /* Private functions ---------------------------------------------------------*/
107 
140 {
141  /* Check the parameters */
143 
144 
145  if((ADCx == ADC1) || (ADCx == ADC2))
146  {
147  /* Enable ADC1/ADC2 reset state */
149  /* Release ADC1/ADC2 from reset state */
151  }
152  else if((ADCx == ADC3) || (ADCx == ADC4))
153  {
154  /* Enable ADC3/ADC4 reset state */
156  /* Release ADC3/ADC4 from reset state */
158  }
159 }
168 void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
169 {
170  uint32_t tmpreg1 = 0;
171  /* Check the parameters */
177  assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
181 
182  /*---------------------------- ADCx CFGR Configuration -----------------*/
183  /* Get the ADCx CFGR value */
184  tmpreg1 = ADCx->CFGR;
185  /* Clear SCAN bit */
186  tmpreg1 &= CFGR_CLEAR_Mask;
187  /* Configure ADCx: scan conversion mode */
188  /* Set SCAN bit according to ADC_ScanConvMode value */
189  tmpreg1 |= (uint32_t)ADC_InitStruct->ADC_ContinuousConvMode |
190  ADC_InitStruct->ADC_Resolution|
191  ADC_InitStruct->ADC_ExternalTrigConvEvent|
192  ADC_InitStruct->ADC_ExternalTrigEventEdge|
193  ADC_InitStruct->ADC_DataAlign|
194  ADC_InitStruct->ADC_OverrunMode|
195  ADC_InitStruct->ADC_AutoInjMode;
196 
197  /* Write to ADCx CFGR */
198  ADCx->CFGR = tmpreg1;
199 
200  /*---------------------------- ADCx SQR1 Configuration -----------------*/
201  /* Get the ADCx SQR1 value */
202  tmpreg1 = ADCx->SQR1;
203  /* Clear L bits */
204  tmpreg1 &= ~(uint32_t)(ADC_SQR1_L);
205  /* Configure ADCx: regular channel sequence length */
206  /* Set L bits according to ADC_NbrOfRegChannel value */
207  tmpreg1 |= (uint32_t) (ADC_InitStruct->ADC_NbrOfRegChannel - 1);
208  /* Write to ADCx SQR1 */
209  ADCx->SQR1 = tmpreg1;
210 
211 }
212 
218 void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
219 {
220  /* Reset ADC init structure parameters values */
221  ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
222  ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
225  ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
226  ADC_InitStruct->ADC_OverrunMode = DISABLE;
227  ADC_InitStruct->ADC_AutoInjMode = DISABLE;
228  ADC_InitStruct->ADC_NbrOfRegChannel = 1;
229 }
230 
239 void ADC_InjectedInit(ADC_TypeDef* ADCx, ADC_InjectedInitTypeDef* ADC_InjectedInitStruct)
240 {
241  uint32_t tmpreg1 = 0;
242  /* Check the parameters */
247  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedInitStruct->ADC_InjecSequence1));
248  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedInitStruct->ADC_InjecSequence2));
249  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedInitStruct->ADC_InjecSequence3));
250  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedInitStruct->ADC_InjecSequence4));
251 
252  /*---------------------------- ADCx JSQR Configuration -----------------*/
253  /* Get the ADCx JSQR value */
254  tmpreg1 = ADCx->JSQR;
255  /* Clear L bits */
256  tmpreg1 &= JSQR_CLEAR_Mask;
257  /* Configure ADCx: Injected channel sequence length, external trigger,
258  external trigger edge and sequences
259  */
260  tmpreg1 = (uint32_t) ((ADC_InjectedInitStruct->ADC_NbrOfInjecChannel - (uint8_t)1) |
261  ADC_InjectedInitStruct->ADC_ExternalTrigInjecConvEvent |
262  ADC_InjectedInitStruct->ADC_ExternalTrigInjecEventEdge |
263  (uint32_t)((ADC_InjectedInitStruct->ADC_InjecSequence1) << 8) |
264  (uint32_t)((ADC_InjectedInitStruct->ADC_InjecSequence2) << 14) |
265  (uint32_t)((ADC_InjectedInitStruct->ADC_InjecSequence3) << 20) |
266  (uint32_t)((ADC_InjectedInitStruct->ADC_InjecSequence4) << 26));
267  /* Write to ADCx SQR1 */
268  ADCx->JSQR = tmpreg1;
269 }
270 
276 void ADC_InjectedStructInit(ADC_InjectedInitTypeDef* ADC_InjectedInitStruct)
277 {
280  ADC_InjectedInitStruct->ADC_NbrOfInjecChannel = 1;
281  ADC_InjectedInitStruct->ADC_InjecSequence1 = ADC_InjectedChannel_1;
282  ADC_InjectedInitStruct->ADC_InjecSequence2 = ADC_InjectedChannel_1;
283  ADC_InjectedInitStruct->ADC_InjecSequence3 = ADC_InjectedChannel_1;
284  ADC_InjectedInitStruct->ADC_InjecSequence4 = ADC_InjectedChannel_1;
285 }
286 
295 void ADC_CommonInit(ADC_TypeDef* ADCx, ADC_CommonInitTypeDef* ADC_CommonInitStruct)
296 {
297  uint32_t tmpreg1 = 0;
298  /* Check the parameters */
299  assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode));
300  assert_param(IS_ADC_CLOCKMODE(ADC_CommonInitStruct->ADC_Clock));
301  assert_param(IS_ADC_DMA_MODE(ADC_CommonInitStruct->ADC_DMAMode));
302  assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode));
304 
305  if((ADCx == ADC1) || (ADCx == ADC2))
306  {
307  /* Get the ADC CCR value */
308  tmpreg1 = ADC1_2->CCR;
309 
310  /* Clear MULTI, DELAY, DMA and ADCPRE bits */
311  tmpreg1 &= CCR_CLEAR_MASK;
312  }
313  else
314  {
315  /* Get the ADC CCR value */
316  tmpreg1 = ADC3_4->CCR;
317 
318  /* Clear MULTI, DELAY, DMA and ADCPRE bits */
319  tmpreg1 &= CCR_CLEAR_MASK;
320  }
321  /*---------------------------- ADC CCR Configuration -----------------*/
322  /* Configure ADCx: Multi mode, Delay between two sampling time, ADC clock, DMA mode
323  and DMA access mode for dual mode */
324  /* Set MULTI bits according to ADC_Mode value */
325  /* Set CKMODE bits according to ADC_Clock value */
326  /* Set MDMA bits according to ADC_DMAAccessMode value */
327  /* Set DMACFG bits according to ADC_DMAMode value */
328  /* Set DELAY bits according to ADC_TwoSamplingDelay value */
329  tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode |
330  ADC_CommonInitStruct->ADC_Clock |
331  ADC_CommonInitStruct->ADC_DMAAccessMode |
332  (uint32_t)(ADC_CommonInitStruct->ADC_DMAMode << 12) |
333  (uint32_t)((uint32_t)ADC_CommonInitStruct->ADC_TwoSamplingDelay << 8));
334 
335  if((ADCx == ADC1) || (ADCx == ADC2))
336  {
337  /* Write to ADC CCR */
338  ADC1_2->CCR = tmpreg1;
339  }
340  else
341  {
342  /* Write to ADC CCR */
343  ADC3_4->CCR = tmpreg1;
344  }
345 }
346 
353 void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
354 {
355  /* Initialize the ADC_Mode member */
356  ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent;
357 
358  /* initialize the ADC_Clock member */
359  ADC_CommonInitStruct->ADC_Clock = ADC_Clock_AsynClkMode;
360 
361  /* Initialize the ADC_DMAAccessMode member */
362  ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
363 
364  /* Initialize the ADC_DMAMode member */
365  ADC_CommonInitStruct->ADC_DMAMode = ADC_DMAMode_OneShot;
366 
367  /* Initialize the ADC_TwoSamplingDelay member */
368  ADC_CommonInitStruct->ADC_TwoSamplingDelay = 0;
369 
370 }
371 
379 void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
380 {
381  /* Check the parameters */
384 
385  if (NewState != DISABLE)
386  {
387  /* Set the ADEN bit */
388  ADCx->CR |= ADC_CR_ADEN;
389  }
390  else
391  {
392  /* Disable the selected ADC peripheral: Set the ADDIS bit */
393  ADCx->CR |= ADC_CR_ADDIS;
394  }
395 }
396 
403 {
404  /* Check the parameters */
406 
407  /* Set the ADCAL bit */
408  ADCx->CR |= ADC_CR_ADCAL;
409 }
410 
417 {
418  /* Check the parameters */
420 
421  /* Return the selected ADC calibration value */
422  return (uint32_t)ADCx->CALFACT;
423 }
424 
430 void ADC_SetCalibrationValue(ADC_TypeDef* ADCx, uint32_t ADC_Calibration)
431 {
432  /* Check the parameters */
434 
435  /* Set the ADC calibration register value */
436  ADCx->CALFACT = ADC_Calibration;
437 }
438 
448 void ADC_SelectCalibrationMode(ADC_TypeDef* ADCx, uint32_t ADC_CalibrationMode)
449 {
450  /* Check the parameters */
452  assert_param(IS_ADC_CALIBRATION_MODE(ADC_CalibrationMode));
453  /* Set or Reset the ADCALDIF bit */
454  ADCx->CR &= (~ADC_CR_ADCALDIF);
455  ADCx->CR |= ADC_CalibrationMode;
456 
457 }
458 
465 {
466  FlagStatus bitstatus = RESET;
467  /* Check the parameters */
469  /* Check the status of CAL bit */
470  if ((ADCx->CR & ADC_CR_ADCAL) != (uint32_t)RESET)
471  {
472  /* CAL bit is set: calibration on going */
473  bitstatus = SET;
474  }
475  else
476  {
477  /* CAL bit is reset: end of calibration */
478  bitstatus = RESET;
479  }
480  /* Return the CAL bit status */
481  return bitstatus;
482 }
483 
490 {
491  /* Check the parameters */
493 
494  /* Set the ADDIS bit */
495  ADCx->CR |= ADC_CR_ADDIS;
496 }
497 
498 
505 {
506  FlagStatus bitstatus = RESET;
507  /* Check the parameters */
509 
510  /* Check the status of ADDIS bit */
511  if ((ADCx->CR & ADC_CR_ADDIS) != (uint32_t)RESET)
512  {
513  /* ADDIS bit is set */
514  bitstatus = SET;
515  }
516  else
517  {
518  /* ADDIS bit is reset */
519  bitstatus = RESET;
520  }
521  /* Return the ADDIS bit status */
522  return bitstatus;
523 }
524 
533 {
534  /* Check the parameters */
537 
538  /* set the intermediate state before moving the ADC voltage regulator
539  from enable state to disable state or from disable state to enable state */
540  ADCx->CR &= ~(ADC_CR_ADVREGEN);
541 
542  if (NewState != DISABLE)
543  {
544  /* Set the ADVREGEN bit 0 */
545  ADCx->CR |= ADC_CR_ADVREGEN_0;
546  }
547  else
548  {
549  /* Set the ADVREGEN bit 1 */
550  ADCx->CR |=ADC_CR_ADVREGEN_1;
551  }
552 }
553 
576 void ADC_SelectDifferentialMode(ADC_TypeDef* ADCx, uint8_t ADC_Channel, FunctionalState NewState)
577 {
578  /* Check the parameters */
580  assert_param(IS_ADC_DIFFCHANNEL(ADC_Channel));
582 
583  if (NewState != DISABLE)
584  {
585  /* Set the DIFSEL bit */
586  ADCx->DIFSEL |= (uint32_t)(1 << ADC_Channel );
587  }
588  else
589  {
590  /* Reset the DIFSEL bit */
591  ADCx->DIFSEL &= ~(uint32_t)(1 << ADC_Channel);
592  }
593 }
594 
603 {
604  /* Check the parameters */
607 
608  if (NewState != DISABLE)
609  {
610  /* Set the JQM bit */
611  ADCx->CFGR |= (uint32_t)(ADC_CFGR_JQM );
612  }
613  else
614  {
615  /* Reset the JQM bit */
616  ADCx->CFGR &= ~(uint32_t)(ADC_CFGR_JQM);
617  }
618 }
619 
628 {
629  /* Check the parameters */
632 
633  if (NewState != DISABLE)
634  {
635  /* Set the AUTDLY bit */
636  ADCx->CFGR |= (uint32_t)(ADC_CFGR_AUTDLY );
637  }
638  else
639  {
640  /* Reset the AUTDLY bit */
641  ADCx->CFGR &= ~(uint32_t)(ADC_CFGR_AUTDLY);
642  }
643 }
644 
694 void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
695 {
696  uint32_t tmpreg = 0;
697  /* Check the parameters */
699  assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
700  /* Get the old register value */
701  tmpreg = ADCx->CFGR;
702  /* Clear AWDEN, AWDENJ and AWDSGL bits */
703  tmpreg &= ~(uint32_t)(ADC_CFGR_AWD1SGL|ADC_CFGR_AWD1EN|ADC_CFGR_JAWD1EN);
704  /* Set the analog watchdog enable mode */
705  tmpreg |= ADC_AnalogWatchdog;
706  /* Store the new register value */
707  ADCx->CFGR = tmpreg;
708 }
709 
719 void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
720  uint16_t LowThreshold)
721 {
722  /* Check the parameters */
724  assert_param(IS_ADC_THRESHOLD(HighThreshold));
725  assert_param(IS_ADC_THRESHOLD(LowThreshold));
726  /* Set the ADCx high threshold */
727  ADCx->TR1 &= ~(uint32_t)ADC_TR1_HT1;
728  ADCx->TR1 |= (uint32_t)((uint32_t)HighThreshold << 16);
729 
730  /* Set the ADCx low threshold */
731  ADCx->TR1 &= ~(uint32_t)ADC_TR1_LT1;
732  ADCx->TR1 |= LowThreshold;
733 }
734 
744 void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold,
745  uint8_t LowThreshold)
746 {
747  /* Check the parameters */
749 
750  /* Set the ADCx high threshold */
751  ADCx->TR2 &= ~(uint32_t)ADC_TR2_HT2;
752  ADCx->TR2 |= (uint32_t)((uint32_t)HighThreshold << 16);
753 
754  /* Set the ADCx low threshold */
755  ADCx->TR2 &= ~(uint32_t)ADC_TR2_LT2;
756  ADCx->TR2 |= LowThreshold;
757 }
758 
768 void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold,
769  uint8_t LowThreshold)
770 {
771  /* Check the parameters */
773 
774  /* Set the ADCx high threshold */
775  ADCx->TR3 &= ~(uint32_t)ADC_TR3_HT3;
776  ADCx->TR3 |= (uint32_t)((uint32_t)HighThreshold << 16);
777 
778  /* Set the ADCx low threshold */
779  ADCx->TR3 &= ~(uint32_t)ADC_TR3_LT3;
780  ADCx->TR3 |= LowThreshold;
781 }
782 
808 void ADC_AnalogWatchdog1SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
809 {
810  uint32_t tmpreg = 0;
811  /* Check the parameters */
813  assert_param(IS_ADC_CHANNEL(ADC_Channel));
814  /* Get the old register value */
815  tmpreg = ADCx->CFGR;
816  /* Clear the Analog watchdog channel select bits */
817  tmpreg &= ~(uint32_t)ADC_CFGR_AWD1CH;
818  /* Set the Analog watchdog channel */
819  tmpreg |= (uint32_t)((uint32_t)ADC_Channel << 26);
820  /* Store the new register value */
821  ADCx->CFGR = tmpreg;
822 }
823 
849 void ADC_AnalogWatchdog2SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
850 {
851  uint32_t tmpreg = 0;
852  /* Check the parameters */
854  assert_param(IS_ADC_CHANNEL(ADC_Channel));
855  /* Get the old register value */
856  tmpreg = ADCx->AWD2CR;
857  /* Clear the Analog watchdog channel select bits */
858  tmpreg &= ~(uint32_t)ADC_AWD2CR_AWD2CH;
859  /* Set the Analog watchdog channel */
860  tmpreg |= (uint32_t)1 << (ADC_Channel);
861  /* Store the new register value */
862  ADCx->AWD2CR |= tmpreg;
863 }
864 
890 void ADC_AnalogWatchdog3SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
891 {
892  uint32_t tmpreg = 0;
893  /* Check the parameters */
895  assert_param(IS_ADC_CHANNEL(ADC_Channel));
896  /* Get the old register value */
897  tmpreg = ADCx->AWD3CR;
898  /* Clear the Analog watchdog channel select bits */
899  tmpreg &= ~(uint32_t)ADC_AWD3CR_AWD3CH;
900  /* Set the Analog watchdog channel */
901  tmpreg |= (uint32_t)1 << (ADC_Channel);
902  /* Store the new register value */
903  ADCx->AWD3CR |= tmpreg;
904 }
905 
948 #ifdef __GNUC__
949 # pragma GCC diagnostic push
950 # pragma GCC diagnostic ignored "-Wunused-parameter"
951 #endif
953 {
954  /* Check the parameters */
956 
957  if (NewState != DISABLE)
958  {
959  /* Enable the temperature sensor channel*/
960  ADC1_2->CCR |= ADC12_CCR_TSEN;
961  }
962  else
963  {
964  /* Disable the temperature sensor channel*/
965  ADC1_2->CCR &= ~(uint32_t)ADC12_CCR_TSEN;
966  }
967 }
968 #ifdef __GNUC__
969 # pragma GCC diagnostic pop
970 #endif
971 
980 {
981  /* Check the parameters */
984 
985  if((ADCx == ADC1) || (ADCx == ADC2))
986  {
987  if (NewState != DISABLE)
988  {
989  /* Enable the Vrefint channel*/
990  ADC1_2->CCR |= ADC12_CCR_VREFEN;
991  }
992  else
993  {
994  /* Disable the Vrefint channel*/
995  ADC1_2->CCR &= ~(uint32_t)ADC12_CCR_VREFEN;
996  }
997  }
998  else
999  {
1000  if (NewState != DISABLE)
1001  {
1002  /* Enable the Vrefint channel*/
1003  ADC3_4->CCR |= ADC34_CCR_VREFEN;
1004  }
1005  else
1006  {
1007  /* Disable the Vrefint channel*/
1008  ADC3_4->CCR &= ~(uint32_t)ADC34_CCR_VREFEN;
1009  }
1010  }
1011 }
1012 
1020 #ifdef __GNUC__
1021 # pragma GCC diagnostic push
1022 # pragma GCC diagnostic ignored "-Wunused-parameter"
1023 #endif
1025 {
1026  /* Check the parameters */
1027  assert_param(IS_FUNCTIONAL_STATE(NewState));
1028 
1029  if (NewState != DISABLE)
1030  {
1031  /* Enable the Vbat channel*/
1032  ADC1_2->CCR |= ADC12_CCR_VBATEN;
1033  }
1034  else
1035  {
1036  /* Disable the Vbat channel*/
1037  ADC1_2->CCR &= ~(uint32_t)ADC12_CCR_VBATEN;
1038  }
1039 }
1040 #ifdef __GNUC__
1041 # pragma GCC diagnostic pop
1042 #endif
1043 
1141 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
1142 {
1143  uint32_t tmpreg1 = 0, tmpreg2 = 0;
1144  /* Check the parameters */
1146  assert_param(IS_ADC_CHANNEL(ADC_Channel));
1147  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
1148 
1149  /* Regular sequence configuration */
1150  /* For Rank 1 to 4 */
1151  if (Rank < 5)
1152  {
1153  /* Get the old register value */
1154  tmpreg1 = ADCx->SQR1;
1155  /* Calculate the mask to clear */
1156  tmpreg2 = 0x1F << (6 * (Rank ));
1157  /* Clear the old SQx bits for the selected rank */
1158  tmpreg1 &= ~tmpreg2;
1159  /* Calculate the mask to set */
1160  tmpreg2 = (uint32_t)(ADC_Channel) << (6 * (Rank));
1161  /* Set the SQx bits for the selected rank */
1162  tmpreg1 |= tmpreg2;
1163  /* Store the new register value */
1164  ADCx->SQR1 = tmpreg1;
1165  }
1166  /* For Rank 5 to 9 */
1167  else if (Rank < 10)
1168  {
1169  /* Get the old register value */
1170  tmpreg1 = ADCx->SQR2;
1171  /* Calculate the mask to clear */
1172  tmpreg2 = ADC_SQR2_SQ5 << (6 * (Rank - 5));
1173  /* Clear the old SQx bits for the selected rank */
1174  tmpreg1 &= ~tmpreg2;
1175  /* Calculate the mask to set */
1176  tmpreg2 = (uint32_t)(ADC_Channel) << (6 * (Rank - 5));
1177  /* Set the SQx bits for the selected rank */
1178  tmpreg1 |= tmpreg2;
1179  /* Store the new register value */
1180  ADCx->SQR2 = tmpreg1;
1181  }
1182  /* For Rank 10 to 14 */
1183  else if (Rank < 15)
1184  {
1185  /* Get the old register value */
1186  tmpreg1 = ADCx->SQR3;
1187  /* Calculate the mask to clear */
1188  tmpreg2 = ADC_SQR3_SQ10 << (6 * (Rank - 10));
1189  /* Clear the old SQx bits for the selected rank */
1190  tmpreg1 &= ~tmpreg2;
1191  /* Calculate the mask to set */
1192  tmpreg2 = (uint32_t)(ADC_Channel) << (6 * (Rank - 10));
1193  /* Set the SQx bits for the selected rank */
1194  tmpreg1 |= tmpreg2;
1195  /* Store the new register value */
1196  ADCx->SQR3 = tmpreg1;
1197  }
1198  else
1199  {
1200  /* Get the old register value */
1201  tmpreg1 = ADCx->SQR4;
1202  /* Calculate the mask to clear */
1203  tmpreg2 = ADC_SQR3_SQ15 << (6 * (Rank - 15));
1204  /* Clear the old SQx bits for the selected rank */
1205  tmpreg1 &= ~tmpreg2;
1206  /* Calculate the mask to set */
1207  tmpreg2 = (uint32_t)(ADC_Channel) << (6 * (Rank - 15));
1208  /* Set the SQx bits for the selected rank */
1209  tmpreg1 |= tmpreg2;
1210  /* Store the new register value */
1211  ADCx->SQR4 = tmpreg1;
1212  }
1213 
1214  /* Channel sampling configuration */
1215  /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
1216  if (ADC_Channel > ADC_Channel_9)
1217  {
1218  /* Get the old register value */
1219  tmpreg1 = ADCx->SMPR2;
1220  /* Calculate the mask to clear */
1221  tmpreg2 = ADC_SMPR2_SMP10 << (3 * (ADC_Channel - 10));
1222  /* Clear the old channel sample time */
1223  ADCx->SMPR2 &= ~tmpreg2;
1224  /* Calculate the mask to set */
1225  ADCx->SMPR2 |= (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
1226 
1227  }
1228  else /* ADC_Channel include in ADC_Channel_[0..9] */
1229  {
1230  /* Get the old register value */
1231  tmpreg1 = ADCx->SMPR1;
1232  /* Calculate the mask to clear */
1233  tmpreg2 = ADC_SMPR1_SMP1 << (3 * (ADC_Channel - 1));
1234  /* Clear the old channel sample time */
1235  ADCx->SMPR1 &= ~tmpreg2;
1236  /* Calculate the mask to set */
1237  ADCx->SMPR1 |= (uint32_t)ADC_SampleTime << (3 * (ADC_Channel));
1238  }
1239 }
1240 
1248 void ADC_RegularChannelSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t SequencerLength)
1249 {
1250  /* Check the parameters */
1252 
1253  /* Configure the ADC sequence lenght */
1254  ADCx->SQR1 &= ~(uint32_t)ADC_SQR1_L;
1255  ADCx->SQR1 |= (uint32_t)(SequencerLength - 1);
1256 }
1257 
1288 void ADC_ExternalTriggerConfig(ADC_TypeDef* ADCx, uint16_t ADC_ExternalTrigConvEvent, uint16_t ADC_ExternalTrigEventEdge)
1289 {
1290  /* Check the parameters */
1292  assert_param(IS_ADC_EXT_TRIG(ADC_ExternalTrigConvEvent));
1293  assert_param(IS_EXTERNALTRIG_EDGE(ADC_ExternalTrigEventEdge));
1294 
1295  /* Disable the selected ADC conversion on external event */
1296  ADCx->CFGR &= ~(ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL);
1297  ADCx->CFGR |= (uint32_t)(ADC_ExternalTrigEventEdge | ADC_ExternalTrigConvEvent);
1298 }
1299 
1306 {
1307  /* Check the parameters */
1309 
1310  /* Set the ADSTART bit */
1311  ADCx->CR |= ADC_CR_ADSTART;
1312 }
1313 
1320 {
1321  FlagStatus bitstatus = RESET;
1322  /* Check the parameters */
1324  /* Check the status of ADSTART bit */
1325  if ((ADCx->CR & ADC_CR_ADSTART) != (uint32_t)RESET)
1326  {
1327  /* ADSTART bit is set */
1328  bitstatus = SET;
1329  }
1330  else
1331  {
1332  /* ADSTART bit is reset */
1333  bitstatus = RESET;
1334  }
1335  /* Return the ADSTART bit status */
1336  return bitstatus;
1337 }
1338 
1345 {
1346  /* Check the parameters */
1348 
1349  /* Set the ADSTP bit */
1350  ADCx->CR |= ADC_CR_ADSTP;
1351 }
1352 
1353 
1362 void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
1363 {
1364  uint32_t tmpreg1 = 0;
1365  uint32_t tmpreg2 = 0;
1366  /* Check the parameters */
1369  /* Get the old register value */
1370  tmpreg1 = ADCx->CFGR;
1371  /* Clear the old discontinuous mode channel count */
1372  tmpreg1 &= ~(uint32_t)(ADC_CFGR_DISCNUM);
1373  /* Set the discontinuous mode channel count */
1374  tmpreg2 = Number - 1;
1375  tmpreg1 |= tmpreg2 << 17;
1376  /* Store the new register value */
1377  ADCx->CFGR = tmpreg1;
1378 }
1379 
1390 {
1391  /* Check the parameters */
1393  assert_param(IS_FUNCTIONAL_STATE(NewState));
1394  if (NewState != DISABLE)
1395  {
1396  /* Enable the selected ADC regular discontinuous mode */
1397  ADCx->CFGR |= ADC_CFGR_DISCEN;
1398  }
1399  else
1400  {
1401  /* Disable the selected ADC regular discontinuous mode */
1402  ADCx->CFGR &= ~(uint32_t)(ADC_CFGR_DISCEN);
1403  }
1404 }
1405 
1412 {
1413  /* Check the parameters */
1415  /* Return the selected ADC conversion value */
1416  return (uint16_t) ADCx->DR;
1417 }
1418 
1429 {
1430  uint32_t tmpreg1 = 0;
1431 
1432  /* Check the parameters */
1434 
1435  if((ADCx == ADC1) || (ADCx== ADC2))
1436  {
1437  /* Get the dual mode conversion value */
1438  tmpreg1 = ADC1_2->CDR;
1439  }
1440  else
1441  {
1442  /* Get the dual mode conversion value */
1443  tmpreg1 = ADC3_4->CDR;
1444  }
1445  /* Return the dual mode conversion value */
1446  return (uint32_t) tmpreg1;
1447 }
1448 
1476 void ADC_SetChannelOffset1(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset)
1477 {
1478  /* Check the parameters */
1480  assert_param(IS_ADC_CHANNEL(ADC_Channel));
1481  assert_param(IS_ADC_OFFSET(Offset));
1482 
1483  /* Select the Channel */
1484  ADCx->OFR1 &= ~ (uint32_t) ADC_OFR1_OFFSET1_CH;
1485  ADCx->OFR1 |= (uint32_t)((uint32_t)ADC_Channel << 26);
1486 
1487  /* Set the data offset */
1488  ADCx->OFR1 &= ~ (uint32_t) ADC_OFR1_OFFSET1;
1489  ADCx->OFR1 |= (uint32_t)Offset;
1490 }
1491 
1519 void ADC_SetChannelOffset2(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset)
1520 {
1521  /* Check the parameters */
1523  assert_param(IS_ADC_CHANNEL(ADC_Channel));
1524  assert_param(IS_ADC_OFFSET(Offset));
1525 
1526  /* Select the Channel */
1527  ADCx->OFR2 &= ~ (uint32_t) ADC_OFR2_OFFSET2_CH;
1528  ADCx->OFR2 |= (uint32_t)((uint32_t)ADC_Channel << 26);
1529 
1530  /* Set the data offset */
1531  ADCx->OFR2 &= ~ (uint32_t) ADC_OFR2_OFFSET2;
1532  ADCx->OFR2 |= (uint32_t)Offset;
1533 }
1534 
1562 void ADC_SetChannelOffset3(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset)
1563 {
1564  /* Check the parameters */
1566  assert_param(IS_ADC_CHANNEL(ADC_Channel));
1567  assert_param(IS_ADC_OFFSET(Offset));
1568 
1569  /* Select the Channel */
1570  ADCx->OFR3 &= ~ (uint32_t) ADC_OFR3_OFFSET3_CH;
1571  ADCx->OFR3 |= (uint32_t)((uint32_t)ADC_Channel << 26);
1572 
1573  /* Set the data offset */
1574  ADCx->OFR3 &= ~ (uint32_t) ADC_OFR3_OFFSET3;
1575  ADCx->OFR3 |= (uint32_t)Offset;
1576 }
1577 
1605 void ADC_SetChannelOffset4(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset)
1606 {
1607  /* Check the parameters */
1609  assert_param(IS_ADC_CHANNEL(ADC_Channel));
1610  assert_param(IS_ADC_OFFSET(Offset));
1611 
1612  /* Select the Channel */
1613  ADCx->OFR4 &= ~ (uint32_t) ADC_OFR4_OFFSET4_CH;
1614  ADCx->OFR4 |= (uint32_t)((uint32_t)ADC_Channel << 26);
1615 
1616  /* Set the data offset */
1617  ADCx->OFR4 &= ~ (uint32_t) ADC_OFR4_OFFSET4;
1618  ADCx->OFR4 |= (uint32_t)Offset;
1619 }
1620 
1629 {
1630  /* Check the parameters */
1632  assert_param(IS_FUNCTIONAL_STATE(NewState));
1633 
1634  if (NewState != DISABLE)
1635  {
1636  /* Set the OFFSET1_EN bit */
1637  ADCx->OFR1 |= ADC_OFR1_OFFSET1_EN;
1638  }
1639  else
1640  {
1641  /* Reset the OFFSET1_EN bit */
1642  ADCx->OFR1 &= ~(ADC_OFR1_OFFSET1_EN);
1643  }
1644 }
1645 
1654 {
1655  /* Check the parameters */
1657  assert_param(IS_FUNCTIONAL_STATE(NewState));
1658 
1659  if (NewState != DISABLE)
1660  {
1661  /* Set the OFFSET1_EN bit */
1662  ADCx->OFR2 |= ADC_OFR2_OFFSET2_EN;
1663  }
1664  else
1665  {
1666  /* Reset the OFFSET1_EN bit */
1667  ADCx->OFR2 &= ~(ADC_OFR2_OFFSET2_EN);
1668  }
1669 }
1670 
1679 {
1680  /* Check the parameters */
1682  assert_param(IS_FUNCTIONAL_STATE(NewState));
1683 
1684  if (NewState != DISABLE)
1685  {
1686  /* Set the OFFSET1_EN bit */
1687  ADCx->OFR3 |= ADC_OFR3_OFFSET3_EN;
1688  }
1689  else
1690  {
1691  /* Reset the OFFSET1_EN bit */
1692  ADCx->OFR3 &= ~(ADC_OFR3_OFFSET3_EN);
1693  }
1694 }
1695 
1704 {
1705  /* Check the parameters */
1707  assert_param(IS_FUNCTIONAL_STATE(NewState));
1708 
1709  if (NewState != DISABLE)
1710  {
1711  /* Set the OFFSET1_EN bit */
1712  ADCx->OFR4 |= ADC_OFR4_OFFSET4_EN;
1713  }
1714  else
1715  {
1716  /* Reset the OFFSET1_EN bit */
1717  ADCx->OFR4 &= ~(ADC_OFR4_OFFSET4_EN);
1718  }
1719 }
1720 
1755 {
1756  /* Check the parameters */
1758  assert_param(IS_FUNCTIONAL_STATE(NewState));
1759  if (NewState != DISABLE)
1760  {
1761  /* Enable the selected ADC DMA request */
1762  ADCx->CFGR |= ADC_CFGR_DMAEN;
1763  }
1764  else
1765  {
1766  /* Disable the selected ADC DMA request */
1767  ADCx->CFGR &= ~(uint32_t)ADC_CFGR_DMAEN;
1768  }
1769 }
1770 
1780 void ADC_DMAConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMAMode)
1781 {
1782  /* Check the parameters */
1784  assert_param(IS_ADC_DMA_MODE(ADC_DMAMode));
1785 
1786  /* Set or reset the DMACFG bit */
1787  ADCx->CFGR &= ~(uint32_t)ADC_CFGR_DMACFG;
1788  ADCx->CFGR |= ADC_DMAMode;
1789 }
1790 
1853 void ADC_InjectedChannelSampleTimeConfig(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint8_t ADC_SampleTime)
1854 {
1855  uint32_t tmpreg1 = 0;
1856  /* Check the parameters */
1858  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
1859  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
1860 
1861  /* Channel sampling configuration */
1862  /* if ADC_InjectedChannel_10 ... ADC_InjectedChannel_18 is selected */
1863  if (ADC_InjectedChannel > ADC_InjectedChannel_9)
1864  {
1865  /* Calculate the mask to clear */
1866  tmpreg1 = ADC_SMPR2_SMP10 << (3 * (ADC_InjectedChannel - 10));
1867  /* Clear the old channel sample time */
1868  ADCx->SMPR2 &= ~tmpreg1;
1869  /* Calculate the mask to set */
1870  ADCx->SMPR2 |= (uint32_t)ADC_SampleTime << (3 * (ADC_InjectedChannel - 10));
1871 
1872  }
1873  else /* ADC_InjectedChannel include in ADC_InjectedChannel_[0..9] */
1874  {
1875  /* Calculate the mask to clear */
1876  tmpreg1 = ADC_SMPR1_SMP1 << (3 * (ADC_InjectedChannel - 1));
1877  /* Clear the old channel sample time */
1878  ADCx->SMPR1 &= ~tmpreg1;
1879  /* Calculate the mask to set */
1880  ADCx->SMPR1 |= (uint32_t)ADC_SampleTime << (3 * (ADC_InjectedChannel));
1881  }
1882 }
1883 
1893 {
1894  /* Check the parameters */
1896 
1897  /* Enable the selected ADC conversion for injected group on external event and start the selected
1898  ADC injected conversion */
1899  ADCx->CR |= ADC_CR_JADSTART;
1900 }
1901 
1908 {
1909  /* Check the parameters */
1911 
1912  /* Set the JADSTP bit */
1913  ADCx->CR |= ADC_CR_JADSTP;
1914 }
1915 
1922 {
1923  FlagStatus bitstatus = RESET;
1924  /* Check the parameters */
1926 
1927  /* Check the status of JADSTART bit */
1928  if ((ADCx->CR & ADC_CR_JADSTART) != (uint32_t)RESET)
1929  {
1930  /* JADSTART bit is set */
1931  bitstatus = SET;
1932  }
1933  else
1934  {
1935  /* JADSTART bit is reset */
1936  bitstatus = RESET;
1937  }
1938  /* Return the JADSTART bit status */
1939  return bitstatus;
1940 }
1941 
1951 {
1952  /* Check the parameters */
1954  assert_param(IS_FUNCTIONAL_STATE(NewState));
1955  if (NewState != DISABLE)
1956  {
1957  /* Enable the selected ADC automatic injected group conversion */
1958  ADCx->CFGR |= ADC_CFGR_JAUTO;
1959  }
1960  else
1961  {
1962  /* Disable the selected ADC automatic injected group conversion */
1963  ADCx->CFGR &= ~ADC_CFGR_JAUTO;
1964  }
1965 }
1966 
1977 {
1978  /* Check the parameters */
1980  assert_param(IS_FUNCTIONAL_STATE(NewState));
1981  if (NewState != DISABLE)
1982  {
1983  /* Enable the selected ADC injected discontinuous mode */
1984  ADCx->CFGR |= ADC_CFGR_JDISCEN;
1985  }
1986  else
1987  {
1988  /* Disable the selected ADC injected discontinuous mode */
1989  ADCx->CFGR &= ~ADC_CFGR_JDISCEN;
1990  }
1991 }
1992 
2004 uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedSequence)
2005 {
2006  __IO uint32_t tmp = 0;
2007 
2008  /* Check the parameters */
2010  assert_param(IS_ADC_INJECTED_SEQUENCE(ADC_InjectedSequence));
2011 
2012  tmp = (uint32_t)ADCx;
2013  tmp += ((ADC_InjectedSequence - 1 )<< 2) + JDR_Offset;
2014 
2015  /* Returns the selected injected channel conversion data value */
2016  return (uint16_t) (*(__IO uint32_t*) tmp);
2017 }
2018 
2137 void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState)
2138 {
2139  /* Check the parameters */
2141  assert_param(IS_FUNCTIONAL_STATE(NewState));
2142  assert_param(IS_ADC_IT(ADC_IT));
2143 
2144  if (NewState != DISABLE)
2145  {
2146  /* Enable the selected ADC interrupts */
2147  ADCx->IER |= ADC_IT;
2148  }
2149  else
2150  {
2151  /* Disable the selected ADC interrupts */
2152  ADCx->IER &= (~(uint32_t)ADC_IT);
2153  }
2154 }
2155 
2174 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
2175 {
2176  FlagStatus bitstatus = RESET;
2177  /* Check the parameters */
2179  assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
2180 
2181  /* Check the status of the specified ADC flag */
2182  if ((ADCx->ISR & ADC_FLAG) != (uint32_t)RESET)
2183  {
2184  /* ADC_FLAG is set */
2185  bitstatus = SET;
2186  }
2187  else
2188  {
2189  /* ADC_FLAG is reset */
2190  bitstatus = RESET;
2191  }
2192  /* Return the ADC_FLAG status */
2193  return bitstatus;
2194 }
2195 
2214 void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
2215 {
2216  /* Check the parameters */
2218  assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
2219  /* Clear the selected ADC flags */
2220  ADCx->ISR = (uint32_t)ADC_FLAG;
2221 }
2222 
2253 {
2254  uint32_t tmpreg1 = 0;
2255  FlagStatus bitstatus = RESET;
2256 
2257  /* Check the parameters */
2260 
2261  if((ADCx == ADC1) || (ADCx == ADC2))
2262  {
2263  tmpreg1 = ADC1_2->CSR;
2264  }
2265  else
2266  {
2267  tmpreg1 = ADC3_4->CSR;
2268  }
2269  /* Check the status of the specified ADC flag */
2270  if ((tmpreg1 & ADC_FLAG) != (uint32_t)RESET)
2271  {
2272  /* ADC_FLAG is set */
2273  bitstatus = SET;
2274  }
2275  else
2276  {
2277  /* ADC_FLAG is reset */
2278  bitstatus = RESET;
2279  }
2280  /* Return the ADC_FLAG status */
2281  return bitstatus;
2282 }
2283 
2313 void ADC_ClearCommonFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
2314 {
2315  /* Check the parameters */
2318 
2319  if((ADCx == ADC1) || (ADCx == ADC2))
2320  {
2321  /* Clear the selected ADC flags */
2322  ADC1_2->CSR |= (uint32_t)ADC_FLAG;
2323  }
2324  else
2325  {
2326  /* Clear the selected ADC flags */
2327  ADC3_4->CSR |= (uint32_t)ADC_FLAG;
2328  }
2329 }
2330 
2349 ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT)
2350 {
2351  ITStatus bitstatus = RESET;
2352  uint16_t itstatus = 0x0, itenable = 0x0;
2353  /* Check the parameters */
2355  assert_param(IS_ADC_GET_IT(ADC_IT));
2356 
2357  itstatus = ADCx->ISR & ADC_IT;
2358 
2359  itenable = ADCx->IER & ADC_IT;
2360  if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
2361  {
2362  bitstatus = SET;
2363  }
2364  else
2365  {
2366  bitstatus = RESET;
2367  }
2368  return bitstatus;
2369 }
2370 
2389 void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT)
2390 {
2391  /* Check the parameters */
2393  assert_param(IS_ADC_IT(ADC_IT));
2394  /* Clear the selected ADC interrupt pending bit */
2395  ADCx->ISR = (uint32_t)ADC_IT;
2396 }
2397 
2414 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
#define IS_ADC_CLEAR_COMMONFLAG(FLAG)
#define ADC3
Definition: stm32f4xx.h:2085
uint32_t ADC_OverrunMode
Definition: stm32f30x_adc.h:69
#define IS_ADC_MODE(MODE)
#define IS_EXTERNALTRIGINJ_EDGE(EDGE)
FlagStatus
Definition: stm32f4xx.h:706
#define IS_ADC_INJECTED_CHANNEL(CHANNEL)
void ADC_SetChannelOffset2(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint16_t Offset)
Set the ADC channels conversion value offset2.
void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the selected ADC automatic injected group conversion after regular one...
#define IS_ADC_OVRUNMODE(MODE)
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG)
#define RCC_AHBPeriph_ADC12
void ADC_VbatCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the Vbat channel.
ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint32_t ADC_IT)
Checks whether the specified ADC interrupt has occurred or not.
FlagStatus ADC_GetDisableCmdStatus(ADC_TypeDef *ADCx)
Gets the selected ADC disable command Status.
FunctionalState
Definition: stm32f4xx.h:708
void ADC_VrefintCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the Vrefint channel.
#define ADC_InjectedChannel_9
#define ADC_ExternalTrigInjecEventEdge_None
ADC Init structure definition.
Definition: stm32f4xx_adc.h:53
#define ADC_ExternalTrigConvEvent_0
void ADC_SetChannelOffset3(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint16_t Offset)
Set the ADC channels conversion value offset3.
Analog to Digital Converter.
Definition: stm32f4xx.h:725
#define ADC_Mode_Independent
void ADC_DMAConfig(ADC_TypeDef *ADCx, uint32_t ADC_DMAMode)
Configure ADC DMA mode.
void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC peripheral.
#define RCC_AHBPeriph_ADC34
#define ADC_DMAAccessMode_Disabled
__IO uint32_t SMPR2
Definition: stm32f4xx.h:731
void ADC_SetChannelOffset1(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint16_t Offset)
Set the ADC channels conversion value offset1.
__IO uint32_t SMPR1
Definition: stm32f4xx.h:730
FunctionalState ADC_ContinuousConvMode
Definition: stm32f4xx_adc.h:61
#define IS_EXTERNALTRIG_EDGE(EDGE)
void ADC_ChannelOffset1Cmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the Offset1.
#define IS_ADC_DMA_ACCESS_MODE(MODE)
#define ADC_ExternalTrigInjecConvEvent_0
void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct)
Fills each ADC_InitStruct member with its default value.
#define IS_ADC_CHANNEL(CHANNEL)
#define IS_ADC_GET_FLAG(FLAG)
void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC DMA request.
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER)
#define IS_ADC_GET_COMMONFLAG(FLAG)
FlagStatus ADC_GetStartConversionStatus(ADC_TypeDef *ADCx)
Gets the selected ADC start conversion Status.
void ADC_AnalogWatchdog1SingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel)
Configures the analog watchdog 2 guarded single channel.
void assert_param(int val)
__IO uint32_t SQR3
Definition: stm32f4xx.h:740
#define IS_ADC_RESOLUTION(RESOLUTION)
#define IS_ADC_CLOCKMODE(CLOCK)
__IO uint32_t SQR2
Definition: stm32f4xx.h:739
uint8_t ADC_NbrOfRegChannel
Definition: stm32f30x_adc.h:74
#define ADC2
Definition: stm32f4xx.h:2084
#define IS_ADC_THRESHOLD(THRESHOLD)
void ADC_CommonInit(ADC_TypeDef *ADCx, ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Initializes the ADCs peripherals according to the specified parameters in the ADC_CommonInitStruct.
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
void ADC_StopInjectedConversion(ADC_TypeDef *ADCx)
Stops the selected ADC ongoing injected conversion.
#define CCR_CLEAR_MASK
Definition: stm32f30x_adc.c:98
uint32_t ADC_GetCalibrationValue(ADC_TypeDef *ADCx)
Returns the ADCx calibration value.
#define JSQR_CLEAR_Mask
Definition: stm32f30x_adc.c:95
Definition: stm32f4xx.h:706
ADC Common Init structure definition.
Definition: stm32f4xx_adc.h:84
uint32_t ADC_ExternalTrigInjecConvEvent
Definition: stm32f30x_adc.h:88
#define ADC_Channel_9
__IO uint32_t JSQR
Definition: stm32f4xx.h:741
#define ADC_InjectedChannel_1
enum FlagStatus ITStatus
void ADC_ChannelOffset4Cmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the Offset4.
#define IS_ADC_CONVMODE(MODE)
uint32_t ADC_DataAlign
Definition: stm32f4xx_adc.h:72
This file contains all the functions prototypes for the RCC firmware library.
#define IS_ADC_CALIBRATION_MODE(MODE)
void ADC_VoltageRegulatorCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC Voltage Regulator.
#define __IO
Definition: core_cm0.h:198
void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef *ADCx, uint8_t HighThreshold, uint8_t LowThreshold)
Configures the high and low thresholds of the analog watchdog2.
void ADC_AutoDelayCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Selects the ADC Delayed Conversion Mode.
#define IS_ADC_DMA_PERIPH(PERIPH)
Definition: stm32f10x_adc.h:87
void ADC_TempSensorCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the temperature sensor channel.
void ADC_ChannelOffset2Cmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the Offset2.
void ADC_StartInjectedConversion(ADC_TypeDef *ADCx)
Enables or disables the selected ADC start of the injected channels conversion.
#define JDR_Offset
#define IS_ADC_CLEAR_FLAG(FLAG)
void ADC_StartCalibration(ADC_TypeDef *ADCx)
Starts the selected ADC calibration process.
void ADC_DeInit(ADC_TypeDef *ADCx)
Deinitializes the ADCx peripheral registers to their default reset values.
void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog)
Enables or disables the analog watchdog on single/all regular or injected channels.
#define IS_ADC_SAMPLE_TIME(TIME)
void ADC_ExternalTriggerConfig(ADC_TypeDef *ADCx, uint16_t ADC_ExternalTrigConvEvent, uint16_t ADC_ExternalTrigEventEdge)
External Trigger Enable and Polarity Selection for regular channels.
void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode for injected group channel for the specified ADC...
void ADC_SelectCalibrationMode(ADC_TypeDef *ADCx, uint32_t ADC_CalibrationMode)
Select the ADC calibration mode.
#define IS_ADC_INJECTED_SEQUENCE(SEQUENCE)
void ADC_InjectedStructInit(ADC_InjectedInitTypeDef *ADC_InjectedInitStruct)
Fills each ADC_InjectedInitStruct member with its default value.
void ADC_DisableCmd(ADC_TypeDef *ADCx)
ADC Disable Command.
uint32_t ADC_TwoSamplingDelay
Definition: stm32f4xx_adc.h:96
__IO uint32_t DR
Definition: stm32f4xx.h:746
#define IS_ADC_IT(IT)
This file contains all the functions prototypes for the ADC firmware library.
void ADC_SetCalibrationValue(ADC_TypeDef *ADCx, uint32_t ADC_Calibration)
Sets the ADCx calibration register.
void ADC_SelectDifferentialMode(ADC_TypeDef *ADCx, uint8_t ADC_Channel, FunctionalState NewState)
Selectes the differential mode for a specific channel.
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG)
__IO uint32_t SQR1
Definition: stm32f4xx.h:738
uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx)
Returns the last ADCx conversion result data for regular channel.
FlagStatus ADC_GetStartInjectedConversionStatus(ADC_TypeDef *ADCx)
Gets the selected ADC Software start injected conversion Status.
uint32_t ADC_ExternalTrigInjecEventEdge
Definition: stm32f30x_adc.h:91
void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint32_t ADC_IT)
Clears the ADCx&#39;s interrupt pending bits.
uint32_t ADC_GetDualModeConversionValue(ADC_TypeDef *ADCx)
Returns the last ADC1, ADC2, ADC3 and ADC4 regular conversions results data in the selected dual mode...
#define IS_ADC_OFFSET(OFFSET)
void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number)
Configures the discontinuous mode for the selected ADC regular group channel.
void ADC_ChannelOffset3Cmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the Offset3.
#define IS_ADC_AUTOINJECMODE(MODE)
#define ADC_Resolution_12b
#define IS_ADC_GET_IT(IT)
#define IS_ADC_DMA_MODE(MODE)
#define ADC_ExternalTrigEventEdge_None
#define IS_ADC_INJECTED_LENGTH(LENGTH)
void ADC_ClearCommonFlag(ADC_TypeDef *ADCx, uint32_t ADC_FLAG)
Clears the ADCx&#39;s pending flags.
#define ADC_DMAMode_OneShot
uint32_t ADC_Resolution
Definition: stm32f4xx_adc.h:55
#define ADC_Clock_AsynClkMode
void ADC_RegularChannelSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t SequencerLength)
Sets the ADC regular channel sequence lenght.
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel)
Returns the ADC injected channel conversion result.
void ADC_StopConversion(ADC_TypeDef *ADCx)
Stops the selected ADC ongoing conversion.
FlagStatus ADC_GetCommonFlagStatus(ADC_TypeDef *ADCx, uint32_t ADC_FLAG)
Checks whether the specified ADC flag is set or not.
FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint32_t ADC_FLAG)
Checks whether the specified ADC flag is set or not.
#define ADC_SQR1_L
Definition: stm32f4xx.h:2373
#define CFGR_CLEAR_Mask
Definition: stm32f30x_adc.c:92
void ADC_ITConfig(ADC_TypeDef *ADCx, uint32_t ADC_IT, FunctionalState NewState)
Enables or disables the specified ADC interrupts.
#define IS_ADC_DIFFCHANNEL(CHANNEL)
void ADC_ClearFlag(ADC_TypeDef *ADCx, uint32_t ADC_FLAG)
Clears the ADCx&#39;s pending flags.
void ADC_InjectedInit(ADC_TypeDef *ADCx, ADC_InjectedInitTypeDef *ADC_InjectedInitStruct)
Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct.
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx)
Gets the selected ADC calibration status.
void ADC_StartConversion(ADC_TypeDef *ADCx)
Enables or disables the selected ADC start conversion .
#define IS_ADC_DATA_ALIGN(ALIGN)
void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef *ADCx, uint8_t HighThreshold, uint8_t LowThreshold)
Configures the high and low thresholds of the analog watchdog3.
void ADC_AnalogWatchdog2SingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel)
Configures the analog watchdog 2 guarded single channel.
#define IS_ADC_ALL_PERIPH(PERIPH)
uint32_t ADC_ExternalTrigConvEvent
Definition: stm32f30x_adc.h:61
void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sampl...
void ADC_InjectedChannelSampleTimeConfig(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint8_t ADC_SampleTime)
Configures for the selected ADC injected channel its corresponding sample time.
#define ADC_DataAlign_Right
void ADC_CommonStructInit(ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Fills each ADC_CommonInitStruct member with its default value.
uint32_t ADC_AutoInjMode
Definition: stm32f30x_adc.h:71
void ADC_SelectQueueOfContextMode(ADC_TypeDef *ADCx, FunctionalState NewState)
Selects the Queue Of Context Mode for injected channels.
#define IS_ADC_REGULAR_LENGTH(LENGTH)
void ADC_SetChannelOffset4(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint16_t Offset)
Set the ADC channels conversion value offset4.
void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
Configures the high and low thresholds of the analog watchdog1.
#define ADC1
Definition: stm32f4xx.h:2083
#define IS_ADC_TWOSAMPLING_DELAY(DELAY)
void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode on regular group channel for the specified ADC...
void ADC_AnalogWatchdog3SingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel)
Configures the analog watchdog 3 guarded single channel.
ADC Init structure definition.
Definition: stm32f30x_adc.h:85
#define IS_ADC_EXT_TRIG(REGTRIG)
void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct)
Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct.
uint32_t ADC_ExternalTrigEventEdge
Definition: stm32f30x_adc.h:64
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
Forces or releases AHB peripheral reset.


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19