stm32f10x_tim.c
Go to the documentation of this file.
1 
22 /* Includes ------------------------------------------------------------------*/
23 #include "stm32f10x_tim.h"
24 #include "stm32f10x_rcc.h"
25 
47 /* ---------------------- TIM registers bit mask ------------------------ */
48 #define SMCR_ETR_Mask ((uint16_t)0x00FF)
49 #define CCMR_Offset ((uint16_t)0x0018)
50 #define CCER_CCE_Set ((uint16_t)0x0001)
51 #define CCER_CCNE_Set ((uint16_t)0x0004)
52 
77 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
78  uint16_t TIM_ICFilter);
79 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
80  uint16_t TIM_ICFilter);
81 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
82  uint16_t TIM_ICFilter);
83 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
84  uint16_t TIM_ICFilter);
123 {
124  /* Check the parameters */
126 
127  if (TIMx == TIM1)
128  {
131  }
132  else if (TIMx == TIM2)
133  {
136  }
137  else if (TIMx == TIM3)
138  {
141  }
142  else if (TIMx == TIM4)
143  {
146  }
147  else if (TIMx == TIM5)
148  {
151  }
152  else if (TIMx == TIM6)
153  {
156  }
157  else if (TIMx == TIM7)
158  {
161  }
162  else if (TIMx == TIM8)
163  {
166  }
167  else if (TIMx == TIM9)
168  {
171  }
172  else if (TIMx == TIM10)
173  {
176  }
177  else if (TIMx == TIM11)
178  {
181  }
182  else if (TIMx == TIM12)
183  {
186  }
187  else if (TIMx == TIM13)
188  {
191  }
192  else if (TIMx == TIM14)
193  {
196  }
197  else if (TIMx == TIM15)
198  {
201  }
202  else if (TIMx == TIM16)
203  {
206  }
207  else
208  {
209  if (TIMx == TIM17)
210  {
213  }
214  }
215 }
216 
226 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
227 {
228  uint16_t tmpcr1 = 0;
229 
230  /* Check the parameters */
232  assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
233  assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
234 
235  tmpcr1 = TIMx->CR1;
236 
237  if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)||
238  (TIMx == TIM4) || (TIMx == TIM5))
239  {
240  /* Select the Counter Mode */
241  tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
242  tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
243  }
244 
245  if((TIMx != TIM6) && (TIMx != TIM7))
246  {
247  /* Set the clock division */
248  tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
249  tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
250  }
251 
252  TIMx->CR1 = tmpcr1;
253 
254  /* Set the Autoreload value */
255  TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
256 
257  /* Set the Prescaler value */
258  TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
259 
260  if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17))
261  {
262  /* Set the Repetition Counter value */
263  TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
264  }
265 
266  /* Generate an update event to reload the Prescaler and the Repetition counter
267  values immediately */
269 }
270 
279 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
280 {
281  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
282 
283  /* Check the parameters */
285  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
287  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
288  /* Disable the Channel 1: Reset the CC1E Bit */
289  TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
290  /* Get the TIMx CCER register value */
291  tmpccer = TIMx->CCER;
292  /* Get the TIMx CR2 register value */
293  tmpcr2 = TIMx->CR2;
294 
295  /* Get the TIMx CCMR1 register value */
296  tmpccmrx = TIMx->CCMR1;
297 
298  /* Reset the Output Compare Mode Bits */
299  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
300  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
301 
302  /* Select the Output Compare Mode */
303  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
304 
305  /* Reset the Output Polarity level */
306  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
307  /* Set the Output Compare Polarity */
308  tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
309 
310  /* Set the Output State */
311  tmpccer |= TIM_OCInitStruct->TIM_OutputState;
312 
313  if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)||
314  (TIMx == TIM16)|| (TIMx == TIM17))
315  {
320 
321  /* Reset the Output N Polarity level */
322  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
323  /* Set the Output N Polarity */
324  tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
325 
326  /* Reset the Output N State */
327  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));
328  /* Set the Output N State */
329  tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
330 
331  /* Reset the Output Compare and Output Compare N IDLE State */
332  tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
333  tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
334 
335  /* Set the Output Idle state */
336  tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
337  /* Set the Output N Idle state */
338  tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
339  }
340  /* Write to TIMx CR2 */
341  TIMx->CR2 = tmpcr2;
342 
343  /* Write to TIMx CCMR1 */
344  TIMx->CCMR1 = tmpccmrx;
345 
346  /* Set the Capture Compare Register value */
347  TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
348 
349  /* Write to TIMx CCER */
350  TIMx->CCER = tmpccer;
351 }
352 
362 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
363 {
364  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
365 
366  /* Check the parameters */
368  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
370  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
371  /* Disable the Channel 2: Reset the CC2E Bit */
372  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
373 
374  /* Get the TIMx CCER register value */
375  tmpccer = TIMx->CCER;
376  /* Get the TIMx CR2 register value */
377  tmpcr2 = TIMx->CR2;
378 
379  /* Get the TIMx CCMR1 register value */
380  tmpccmrx = TIMx->CCMR1;
381 
382  /* Reset the Output Compare mode and Capture/Compare selection Bits */
383  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
384  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));
385 
386  /* Select the Output Compare Mode */
387  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
388 
389  /* Reset the Output Polarity level */
390  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
391  /* Set the Output Compare Polarity */
392  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
393 
394  /* Set the Output State */
395  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
396 
397  if((TIMx == TIM1) || (TIMx == TIM8))
398  {
403 
404  /* Reset the Output N Polarity level */
405  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
406  /* Set the Output N Polarity */
407  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
408 
409  /* Reset the Output N State */
410  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));
411  /* Set the Output N State */
412  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
413 
414  /* Reset the Output Compare and Output Compare N IDLE State */
415  tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
416  tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
417 
418  /* Set the Output Idle state */
419  tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
420  /* Set the Output N Idle state */
421  tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
422  }
423  /* Write to TIMx CR2 */
424  TIMx->CR2 = tmpcr2;
425 
426  /* Write to TIMx CCMR1 */
427  TIMx->CCMR1 = tmpccmrx;
428 
429  /* Set the Capture Compare Register value */
430  TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
431 
432  /* Write to TIMx CCER */
433  TIMx->CCER = tmpccer;
434 }
435 
444 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
445 {
446  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
447 
448  /* Check the parameters */
450  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
452  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
453  /* Disable the Channel 2: Reset the CC2E Bit */
454  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
455 
456  /* Get the TIMx CCER register value */
457  tmpccer = TIMx->CCER;
458  /* Get the TIMx CR2 register value */
459  tmpcr2 = TIMx->CR2;
460 
461  /* Get the TIMx CCMR2 register value */
462  tmpccmrx = TIMx->CCMR2;
463 
464  /* Reset the Output Compare mode and Capture/Compare selection Bits */
465  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
466  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));
467  /* Select the Output Compare Mode */
468  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
469 
470  /* Reset the Output Polarity level */
471  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
472  /* Set the Output Compare Polarity */
473  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
474 
475  /* Set the Output State */
476  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
477 
478  if((TIMx == TIM1) || (TIMx == TIM8))
479  {
484 
485  /* Reset the Output N Polarity level */
486  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
487  /* Set the Output N Polarity */
488  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
489  /* Reset the Output N State */
490  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
491 
492  /* Set the Output N State */
493  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
494  /* Reset the Output Compare and Output Compare N IDLE State */
495  tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
496  tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
497  /* Set the Output Idle state */
498  tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
499  /* Set the Output N Idle state */
500  tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
501  }
502  /* Write to TIMx CR2 */
503  TIMx->CR2 = tmpcr2;
504 
505  /* Write to TIMx CCMR2 */
506  TIMx->CCMR2 = tmpccmrx;
507 
508  /* Set the Capture Compare Register value */
509  TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
510 
511  /* Write to TIMx CCER */
512  TIMx->CCER = tmpccer;
513 }
514 
523 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
524 {
525  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
526 
527  /* Check the parameters */
529  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
531  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
532  /* Disable the Channel 2: Reset the CC4E Bit */
533  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
534 
535  /* Get the TIMx CCER register value */
536  tmpccer = TIMx->CCER;
537  /* Get the TIMx CR2 register value */
538  tmpcr2 = TIMx->CR2;
539 
540  /* Get the TIMx CCMR2 register value */
541  tmpccmrx = TIMx->CCMR2;
542 
543  /* Reset the Output Compare mode and Capture/Compare selection Bits */
544  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
545  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));
546 
547  /* Select the Output Compare Mode */
548  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
549 
550  /* Reset the Output Polarity level */
551  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
552  /* Set the Output Compare Polarity */
553  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
554 
555  /* Set the Output State */
556  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
557 
558  if((TIMx == TIM1) || (TIMx == TIM8))
559  {
561  /* Reset the Output Compare IDLE State */
562  tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
563  /* Set the Output Idle state */
564  tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
565  }
566  /* Write to TIMx CR2 */
567  TIMx->CR2 = tmpcr2;
568 
569  /* Write to TIMx CCMR2 */
570  TIMx->CCMR2 = tmpccmrx;
571 
572  /* Set the Capture Compare Register value */
573  TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
574 
575  /* Write to TIMx CCER */
576  TIMx->CCER = tmpccer;
577 }
578 
587 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
588 {
589  /* Check the parameters */
590  assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
593  assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
594 
595  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
596  (TIMx == TIM4) ||(TIMx == TIM5))
597  {
598  assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
599  }
600  else
601  {
603  }
604  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
605  {
607  /* TI1 Configuration */
608  TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
609  TIM_ICInitStruct->TIM_ICSelection,
610  TIM_ICInitStruct->TIM_ICFilter);
611  /* Set the Input Capture Prescaler value */
612  TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
613  }
614  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
615  {
617  /* TI2 Configuration */
618  TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
619  TIM_ICInitStruct->TIM_ICSelection,
620  TIM_ICInitStruct->TIM_ICFilter);
621  /* Set the Input Capture Prescaler value */
622  TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
623  }
624  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
625  {
627  /* TI3 Configuration */
628  TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
629  TIM_ICInitStruct->TIM_ICSelection,
630  TIM_ICInitStruct->TIM_ICFilter);
631  /* Set the Input Capture Prescaler value */
632  TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
633  }
634  else
635  {
637  /* TI4 Configuration */
638  TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
639  TIM_ICInitStruct->TIM_ICSelection,
640  TIM_ICInitStruct->TIM_ICFilter);
641  /* Set the Input Capture Prescaler value */
642  TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
643  }
644 }
645 
654 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
655 {
656  uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
657  uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
658  /* Check the parameters */
660  /* Select the Opposite Input Polarity */
661  if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
662  {
663  icoppositepolarity = TIM_ICPolarity_Falling;
664  }
665  else
666  {
667  icoppositepolarity = TIM_ICPolarity_Rising;
668  }
669  /* Select the Opposite Input */
670  if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
671  {
672  icoppositeselection = TIM_ICSelection_IndirectTI;
673  }
674  else
675  {
676  icoppositeselection = TIM_ICSelection_DirectTI;
677  }
678  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
679  {
680  /* TI1 Configuration */
681  TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
682  TIM_ICInitStruct->TIM_ICFilter);
683  /* Set the Input Capture Prescaler value */
684  TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
685  /* TI2 Configuration */
686  TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
687  /* Set the Input Capture Prescaler value */
688  TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
689  }
690  else
691  {
692  /* TI2 Configuration */
693  TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
694  TIM_ICInitStruct->TIM_ICFilter);
695  /* Set the Input Capture Prescaler value */
696  TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
697  /* TI1 Configuration */
698  TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
699  /* Set the Input Capture Prescaler value */
700  TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
701  }
702 }
703 
712 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
713 {
714  /* Check the parameters */
716  assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
717  assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
718  assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
719  assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
722  /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
723  the OSSI State, the dead time value and the Automatic Output Enable Bit */
724  TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
725  TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
726  TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
727  TIM_BDTRInitStruct->TIM_AutomaticOutput;
728 }
729 
736 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
737 {
738  /* Set the default configuration */
739  TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
740  TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
741  TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
742  TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
743  TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
744 }
745 
752 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
753 {
754  /* Set the default configuration */
755  TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
756  TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
757  TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
758  TIM_OCInitStruct->TIM_Pulse = 0x0000;
759  TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
760  TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
761  TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
762  TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
763 }
764 
771 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
772 {
773  /* Set the default configuration */
774  TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
775  TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
776  TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
777  TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
778  TIM_ICInitStruct->TIM_ICFilter = 0x00;
779 }
780 
787 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
788 {
789  /* Set the default configuration */
790  TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
791  TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
792  TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
793  TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
794  TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
795  TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
796  TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
797 }
798 
806 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
807 {
808  /* Check the parameters */
811 
812  if (NewState != DISABLE)
813  {
814  /* Enable the TIM Counter */
815  TIMx->CR1 |= TIM_CR1_CEN;
816  }
817  else
818  {
819  /* Disable the TIM Counter */
820  TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
821  }
822 }
823 
832 {
833  /* Check the parameters */
836  if (NewState != DISABLE)
837  {
838  /* Enable the TIM Main Output */
839  TIMx->BDTR |= TIM_BDTR_MOE;
840  }
841  else
842  {
843  /* Disable the TIM Main Output */
844  TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));
845  }
846 }
847 
872 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
873 {
874  /* Check the parameters */
876  assert_param(IS_TIM_IT(TIM_IT));
878 
879  if (NewState != DISABLE)
880  {
881  /* Enable the Interrupt sources */
882  TIMx->DIER |= TIM_IT;
883  }
884  else
885  {
886  /* Disable the Interrupt sources */
887  TIMx->DIER &= (uint16_t)~TIM_IT;
888  }
889 }
890 
909 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
910 {
911  /* Check the parameters */
913  assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
914 
915  /* Set the event sources */
916  TIMx->EGR = TIM_EventSource;
917 }
918 
937 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
938 {
939  /* Check the parameters */
941  assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
942  assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
943  /* Set the DMA Base and the DMA Burst Length */
944  TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
945 }
946 
964 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
965 {
966  /* Check the parameters */
968  assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
970 
971  if (NewState != DISABLE)
972  {
973  /* Enable the DMA sources */
974  TIMx->DIER |= TIM_DMASource;
975  }
976  else
977  {
978  /* Disable the DMA sources */
979  TIMx->DIER &= (uint16_t)~TIM_DMASource;
980  }
981 }
982 
990 {
991  /* Check the parameters */
993  /* Disable slave mode to clock the prescaler directly with the internal clock */
994  TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
995 }
996 
1008 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
1009 {
1010  /* Check the parameters */
1012  assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
1013  /* Select the Internal Trigger */
1014  TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
1015  /* Select the External clock mode1 */
1016  TIMx->SMCR |= TIM_SlaveMode_External1;
1017 }
1018 
1035 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
1036  uint16_t TIM_ICPolarity, uint16_t ICFilter)
1037 {
1038  /* Check the parameters */
1040  assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
1041  assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
1042  assert_param(IS_TIM_IC_FILTER(ICFilter));
1043  /* Configure the Timer Input Clock Source */
1044  if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
1045  {
1046  TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
1047  }
1048  else
1049  {
1050  TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
1051  }
1052  /* Select the Trigger source */
1053  TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
1054  /* Select the External clock mode1 */
1055  TIMx->SMCR |= TIM_SlaveMode_External1;
1056 }
1057 
1075 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
1076  uint16_t ExtTRGFilter)
1077 {
1078  uint16_t tmpsmcr = 0;
1079  /* Check the parameters */
1081  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
1082  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
1083  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
1084  /* Configure the ETR Clock source */
1085  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
1086 
1087  /* Get the TIMx SMCR register value */
1088  tmpsmcr = TIMx->SMCR;
1089  /* Reset the SMS Bits */
1090  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
1091  /* Select the External clock mode1 */
1092  tmpsmcr |= TIM_SlaveMode_External1;
1093  /* Select the Trigger selection : ETRF */
1094  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
1095  tmpsmcr |= TIM_TS_ETRF;
1096  /* Write to TIMx SMCR */
1097  TIMx->SMCR = tmpsmcr;
1098 }
1099 
1117 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
1118  uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
1119 {
1120  /* Check the parameters */
1122  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
1123  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
1124  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
1125  /* Configure the ETR Clock source */
1126  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
1127  /* Enable the External clock mode2 */
1128  TIMx->SMCR |= TIM_SMCR_ECE;
1129 }
1130 
1148 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
1149  uint16_t ExtTRGFilter)
1150 {
1151  uint16_t tmpsmcr = 0;
1152  /* Check the parameters */
1154  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
1155  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
1156  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
1157  tmpsmcr = TIMx->SMCR;
1158  /* Reset the ETR Bits */
1159  tmpsmcr &= SMCR_ETR_Mask;
1160  /* Set the Prescaler, the Filter value and the Polarity */
1161  tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
1162  /* Write to TIMx SMCR */
1163  TIMx->SMCR = tmpsmcr;
1164 }
1165 
1176 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
1177 {
1178  /* Check the parameters */
1180  assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
1181  /* Set the Prescaler value */
1182  TIMx->PSC = Prescaler;
1183  /* Set or reset the UG Bit */
1184  TIMx->EGR = TIM_PSCReloadMode;
1185 }
1186 
1199 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
1200 {
1201  uint16_t tmpcr1 = 0;
1202  /* Check the parameters */
1204  assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
1205  tmpcr1 = TIMx->CR1;
1206  /* Reset the CMS and DIR Bits */
1207  tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
1208  /* Set the Counter Mode */
1209  tmpcr1 |= TIM_CounterMode;
1210  /* Write to TIMx CR1 register */
1211  TIMx->CR1 = tmpcr1;
1212 }
1213 
1229 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
1230 {
1231  uint16_t tmpsmcr = 0;
1232  /* Check the parameters */
1234  assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
1235  /* Get the TIMx SMCR register value */
1236  tmpsmcr = TIMx->SMCR;
1237  /* Reset the TS Bits */
1238  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
1239  /* Set the Input Trigger source */
1240  tmpsmcr |= TIM_InputTriggerSource;
1241  /* Write to TIMx SMCR */
1242  TIMx->SMCR = tmpsmcr;
1243 }
1244 
1264 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
1265  uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
1266 {
1267  uint16_t tmpsmcr = 0;
1268  uint16_t tmpccmr1 = 0;
1269  uint16_t tmpccer = 0;
1270 
1271  /* Check the parameters */
1273  assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
1274  assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
1275  assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
1276 
1277  /* Get the TIMx SMCR register value */
1278  tmpsmcr = TIMx->SMCR;
1279 
1280  /* Get the TIMx CCMR1 register value */
1281  tmpccmr1 = TIMx->CCMR1;
1282 
1283  /* Get the TIMx CCER register value */
1284  tmpccer = TIMx->CCER;
1285 
1286  /* Set the encoder Mode */
1287  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
1288  tmpsmcr |= TIM_EncoderMode;
1289 
1290  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
1291  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
1292  tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
1293 
1294  /* Set the TI1 and the TI2 Polarities */
1295  tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
1296  tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
1297 
1298  /* Write to TIMx SMCR */
1299  TIMx->SMCR = tmpsmcr;
1300  /* Write to TIMx CCMR1 */
1301  TIMx->CCMR1 = tmpccmr1;
1302  /* Write to TIMx CCER */
1303  TIMx->CCER = tmpccer;
1304 }
1305 
1315 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
1316 {
1317  uint16_t tmpccmr1 = 0;
1318  /* Check the parameters */
1320  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
1321  tmpccmr1 = TIMx->CCMR1;
1322  /* Reset the OC1M Bits */
1323  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
1324  /* Configure The Forced output Mode */
1325  tmpccmr1 |= TIM_ForcedAction;
1326  /* Write to TIMx CCMR1 register */
1327  TIMx->CCMR1 = tmpccmr1;
1328 }
1329 
1339 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
1340 {
1341  uint16_t tmpccmr1 = 0;
1342  /* Check the parameters */
1344  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
1345  tmpccmr1 = TIMx->CCMR1;
1346  /* Reset the OC2M Bits */
1347  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
1348  /* Configure The Forced output Mode */
1349  tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
1350  /* Write to TIMx CCMR1 register */
1351  TIMx->CCMR1 = tmpccmr1;
1352 }
1353 
1363 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
1364 {
1365  uint16_t tmpccmr2 = 0;
1366  /* Check the parameters */
1368  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
1369  tmpccmr2 = TIMx->CCMR2;
1370  /* Reset the OC1M Bits */
1371  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
1372  /* Configure The Forced output Mode */
1373  tmpccmr2 |= TIM_ForcedAction;
1374  /* Write to TIMx CCMR2 register */
1375  TIMx->CCMR2 = tmpccmr2;
1376 }
1377 
1387 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
1388 {
1389  uint16_t tmpccmr2 = 0;
1390  /* Check the parameters */
1392  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
1393  tmpccmr2 = TIMx->CCMR2;
1394  /* Reset the OC2M Bits */
1395  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
1396  /* Configure The Forced output Mode */
1397  tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
1398  /* Write to TIMx CCMR2 register */
1399  TIMx->CCMR2 = tmpccmr2;
1400 }
1401 
1410 {
1411  /* Check the parameters */
1413  assert_param(IS_FUNCTIONAL_STATE(NewState));
1414  if (NewState != DISABLE)
1415  {
1416  /* Set the ARR Preload Bit */
1417  TIMx->CR1 |= TIM_CR1_ARPE;
1418  }
1419  else
1420  {
1421  /* Reset the ARR Preload Bit */
1422  TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
1423  }
1424 }
1425 
1434 {
1435  /* Check the parameters */
1437  assert_param(IS_FUNCTIONAL_STATE(NewState));
1438  if (NewState != DISABLE)
1439  {
1440  /* Set the COM Bit */
1441  TIMx->CR2 |= TIM_CR2_CCUS;
1442  }
1443  else
1444  {
1445  /* Reset the COM Bit */
1446  TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);
1447  }
1448 }
1449 
1459 {
1460  /* Check the parameters */
1462  assert_param(IS_FUNCTIONAL_STATE(NewState));
1463  if (NewState != DISABLE)
1464  {
1465  /* Set the CCDS Bit */
1466  TIMx->CR2 |= TIM_CR2_CCDS;
1467  }
1468  else
1469  {
1470  /* Reset the CCDS Bit */
1471  TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
1472  }
1473 }
1474 
1484 {
1485  /* Check the parameters */
1487  assert_param(IS_FUNCTIONAL_STATE(NewState));
1488  if (NewState != DISABLE)
1489  {
1490  /* Set the CCPC Bit */
1491  TIMx->CR2 |= TIM_CR2_CCPC;
1492  }
1493  else
1494  {
1495  /* Reset the CCPC Bit */
1496  TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);
1497  }
1498 }
1499 
1509 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
1510 {
1511  uint16_t tmpccmr1 = 0;
1512  /* Check the parameters */
1514  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
1515  tmpccmr1 = TIMx->CCMR1;
1516  /* Reset the OC1PE Bit */
1517  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
1518  /* Enable or Disable the Output Compare Preload feature */
1519  tmpccmr1 |= TIM_OCPreload;
1520  /* Write to TIMx CCMR1 register */
1521  TIMx->CCMR1 = tmpccmr1;
1522 }
1523 
1534 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
1535 {
1536  uint16_t tmpccmr1 = 0;
1537  /* Check the parameters */
1539  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
1540  tmpccmr1 = TIMx->CCMR1;
1541  /* Reset the OC2PE Bit */
1542  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
1543  /* Enable or Disable the Output Compare Preload feature */
1544  tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
1545  /* Write to TIMx CCMR1 register */
1546  TIMx->CCMR1 = tmpccmr1;
1547 }
1548 
1558 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
1559 {
1560  uint16_t tmpccmr2 = 0;
1561  /* Check the parameters */
1563  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
1564  tmpccmr2 = TIMx->CCMR2;
1565  /* Reset the OC3PE Bit */
1566  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
1567  /* Enable or Disable the Output Compare Preload feature */
1568  tmpccmr2 |= TIM_OCPreload;
1569  /* Write to TIMx CCMR2 register */
1570  TIMx->CCMR2 = tmpccmr2;
1571 }
1572 
1582 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
1583 {
1584  uint16_t tmpccmr2 = 0;
1585  /* Check the parameters */
1587  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
1588  tmpccmr2 = TIMx->CCMR2;
1589  /* Reset the OC4PE Bit */
1590  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
1591  /* Enable or Disable the Output Compare Preload feature */
1592  tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
1593  /* Write to TIMx CCMR2 register */
1594  TIMx->CCMR2 = tmpccmr2;
1595 }
1596 
1606 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
1607 {
1608  uint16_t tmpccmr1 = 0;
1609  /* Check the parameters */
1611  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
1612  /* Get the TIMx CCMR1 register value */
1613  tmpccmr1 = TIMx->CCMR1;
1614  /* Reset the OC1FE Bit */
1615  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
1616  /* Enable or Disable the Output Compare Fast Bit */
1617  tmpccmr1 |= TIM_OCFast;
1618  /* Write to TIMx CCMR1 */
1619  TIMx->CCMR1 = tmpccmr1;
1620 }
1621 
1632 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
1633 {
1634  uint16_t tmpccmr1 = 0;
1635  /* Check the parameters */
1637  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
1638  /* Get the TIMx CCMR1 register value */
1639  tmpccmr1 = TIMx->CCMR1;
1640  /* Reset the OC2FE Bit */
1641  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
1642  /* Enable or Disable the Output Compare Fast Bit */
1643  tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
1644  /* Write to TIMx CCMR1 */
1645  TIMx->CCMR1 = tmpccmr1;
1646 }
1647 
1657 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
1658 {
1659  uint16_t tmpccmr2 = 0;
1660  /* Check the parameters */
1662  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
1663  /* Get the TIMx CCMR2 register value */
1664  tmpccmr2 = TIMx->CCMR2;
1665  /* Reset the OC3FE Bit */
1666  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
1667  /* Enable or Disable the Output Compare Fast Bit */
1668  tmpccmr2 |= TIM_OCFast;
1669  /* Write to TIMx CCMR2 */
1670  TIMx->CCMR2 = tmpccmr2;
1671 }
1672 
1682 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
1683 {
1684  uint16_t tmpccmr2 = 0;
1685  /* Check the parameters */
1687  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
1688  /* Get the TIMx CCMR2 register value */
1689  tmpccmr2 = TIMx->CCMR2;
1690  /* Reset the OC4FE Bit */
1691  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
1692  /* Enable or Disable the Output Compare Fast Bit */
1693  tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
1694  /* Write to TIMx CCMR2 */
1695  TIMx->CCMR2 = tmpccmr2;
1696 }
1697 
1707 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
1708 {
1709  uint16_t tmpccmr1 = 0;
1710  /* Check the parameters */
1712  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
1713 
1714  tmpccmr1 = TIMx->CCMR1;
1715 
1716  /* Reset the OC1CE Bit */
1717  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
1718  /* Enable or Disable the Output Compare Clear Bit */
1719  tmpccmr1 |= TIM_OCClear;
1720  /* Write to TIMx CCMR1 register */
1721  TIMx->CCMR1 = tmpccmr1;
1722 }
1723 
1733 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
1734 {
1735  uint16_t tmpccmr1 = 0;
1736  /* Check the parameters */
1738  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
1739  tmpccmr1 = TIMx->CCMR1;
1740  /* Reset the OC2CE Bit */
1741  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
1742  /* Enable or Disable the Output Compare Clear Bit */
1743  tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
1744  /* Write to TIMx CCMR1 register */
1745  TIMx->CCMR1 = tmpccmr1;
1746 }
1747 
1757 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
1758 {
1759  uint16_t tmpccmr2 = 0;
1760  /* Check the parameters */
1762  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
1763  tmpccmr2 = TIMx->CCMR2;
1764  /* Reset the OC3CE Bit */
1765  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
1766  /* Enable or Disable the Output Compare Clear Bit */
1767  tmpccmr2 |= TIM_OCClear;
1768  /* Write to TIMx CCMR2 register */
1769  TIMx->CCMR2 = tmpccmr2;
1770 }
1771 
1781 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
1782 {
1783  uint16_t tmpccmr2 = 0;
1784  /* Check the parameters */
1786  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
1787  tmpccmr2 = TIMx->CCMR2;
1788  /* Reset the OC4CE Bit */
1789  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
1790  /* Enable or Disable the Output Compare Clear Bit */
1791  tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
1792  /* Write to TIMx CCMR2 register */
1793  TIMx->CCMR2 = tmpccmr2;
1794 }
1795 
1805 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
1806 {
1807  uint16_t tmpccer = 0;
1808  /* Check the parameters */
1810  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
1811  tmpccer = TIMx->CCER;
1812  /* Set or Reset the CC1P Bit */
1813  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
1814  tmpccer |= TIM_OCPolarity;
1815  /* Write to TIMx CCER register */
1816  TIMx->CCER = tmpccer;
1817 }
1818 
1828 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
1829 {
1830  uint16_t tmpccer = 0;
1831  /* Check the parameters */
1833  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
1834 
1835  tmpccer = TIMx->CCER;
1836  /* Set or Reset the CC1NP Bit */
1837  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);
1838  tmpccer |= TIM_OCNPolarity;
1839  /* Write to TIMx CCER register */
1840  TIMx->CCER = tmpccer;
1841 }
1842 
1852 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
1853 {
1854  uint16_t tmpccer = 0;
1855  /* Check the parameters */
1857  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
1858  tmpccer = TIMx->CCER;
1859  /* Set or Reset the CC2P Bit */
1860  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
1861  tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
1862  /* Write to TIMx CCER register */
1863  TIMx->CCER = tmpccer;
1864 }
1865 
1875 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
1876 {
1877  uint16_t tmpccer = 0;
1878  /* Check the parameters */
1880  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
1881 
1882  tmpccer = TIMx->CCER;
1883  /* Set or Reset the CC2NP Bit */
1884  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);
1885  tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
1886  /* Write to TIMx CCER register */
1887  TIMx->CCER = tmpccer;
1888 }
1889 
1899 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
1900 {
1901  uint16_t tmpccer = 0;
1902  /* Check the parameters */
1904  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
1905  tmpccer = TIMx->CCER;
1906  /* Set or Reset the CC3P Bit */
1907  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
1908  tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
1909  /* Write to TIMx CCER register */
1910  TIMx->CCER = tmpccer;
1911 }
1912 
1922 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
1923 {
1924  uint16_t tmpccer = 0;
1925 
1926  /* Check the parameters */
1928  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
1929 
1930  tmpccer = TIMx->CCER;
1931  /* Set or Reset the CC3NP Bit */
1932  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);
1933  tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
1934  /* Write to TIMx CCER register */
1935  TIMx->CCER = tmpccer;
1936 }
1937 
1947 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
1948 {
1949  uint16_t tmpccer = 0;
1950  /* Check the parameters */
1952  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
1953  tmpccer = TIMx->CCER;
1954  /* Set or Reset the CC4P Bit */
1955  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
1956  tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
1957  /* Write to TIMx CCER register */
1958  TIMx->CCER = tmpccer;
1959 }
1960 
1974 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
1975 {
1976  uint16_t tmp = 0;
1977 
1978  /* Check the parameters */
1980  assert_param(IS_TIM_CHANNEL(TIM_Channel));
1981  assert_param(IS_TIM_CCX(TIM_CCx));
1982 
1983  tmp = CCER_CCE_Set << TIM_Channel;
1984 
1985  /* Reset the CCxE Bit */
1986  TIMx->CCER &= (uint16_t)~ tmp;
1987 
1988  /* Set or reset the CCxE Bit */
1989  TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
1990 }
1991 
2004 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
2005 {
2006  uint16_t tmp = 0;
2007 
2008  /* Check the parameters */
2011  assert_param(IS_TIM_CCXN(TIM_CCxN));
2012 
2013  tmp = CCER_CCNE_Set << TIM_Channel;
2014 
2015  /* Reset the CCxNE Bit */
2016  TIMx->CCER &= (uint16_t) ~tmp;
2017 
2018  /* Set or reset the CCxNE Bit */
2019  TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
2020 }
2021 
2045 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
2046 {
2047  uint32_t tmp = 0;
2048  uint16_t tmp1 = 0;
2049 
2050  /* Check the parameters */
2052  assert_param(IS_TIM_CHANNEL(TIM_Channel));
2053  assert_param(IS_TIM_OCM(TIM_OCMode));
2054 
2055  tmp = (uint32_t) TIMx;
2056  tmp += CCMR_Offset;
2057 
2058  tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;
2059 
2060  /* Disable the Channel: Reset the CCxE Bit */
2061  TIMx->CCER &= (uint16_t) ~tmp1;
2062 
2063  if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
2064  {
2065  tmp += (TIM_Channel>>1);
2066 
2067  /* Reset the OCxM bits in the CCMRx register */
2068  *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
2069 
2070  /* Configure the OCxM bits in the CCMRx register */
2071  *(__IO uint32_t *) tmp |= TIM_OCMode;
2072  }
2073  else
2074  {
2075  tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
2076 
2077  /* Reset the OCxM bits in the CCMRx register */
2078  *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
2079 
2080  /* Configure the OCxM bits in the CCMRx register */
2081  *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
2082  }
2083 }
2084 
2093 {
2094  /* Check the parameters */
2096  assert_param(IS_FUNCTIONAL_STATE(NewState));
2097  if (NewState != DISABLE)
2098  {
2099  /* Set the Update Disable Bit */
2100  TIMx->CR1 |= TIM_CR1_UDIS;
2101  }
2102  else
2103  {
2104  /* Reset the Update Disable Bit */
2105  TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
2106  }
2107 }
2108 
2120 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
2121 {
2122  /* Check the parameters */
2124  assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
2125  if (TIM_UpdateSource != TIM_UpdateSource_Global)
2126  {
2127  /* Set the URS Bit */
2128  TIMx->CR1 |= TIM_CR1_URS;
2129  }
2130  else
2131  {
2132  /* Reset the URS Bit */
2133  TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
2134  }
2135 }
2136 
2145 {
2146  /* Check the parameters */
2148  assert_param(IS_FUNCTIONAL_STATE(NewState));
2149  if (NewState != DISABLE)
2150  {
2151  /* Set the TI1S Bit */
2152  TIMx->CR2 |= TIM_CR2_TI1S;
2153  }
2154  else
2155  {
2156  /* Reset the TI1S Bit */
2157  TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
2158  }
2159 }
2160 
2170 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
2171 {
2172  /* Check the parameters */
2174  assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
2175  /* Reset the OPM Bit */
2176  TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
2177  /* Configure the OPM Mode */
2178  TIMx->CR1 |= TIM_OPMode;
2179 }
2180 
2202 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
2203 {
2204  /* Check the parameters */
2206  assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
2207  /* Reset the MMS Bits */
2208  TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
2209  /* Select the TRGO source */
2210  TIMx->CR2 |= TIM_TRGOSource;
2211 }
2212 
2225 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
2226 {
2227  /* Check the parameters */
2229  assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
2230  /* Reset the SMS Bits */
2231  TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
2232  /* Select the Slave Mode */
2233  TIMx->SMCR |= TIM_SlaveMode;
2234 }
2235 
2246 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
2247 {
2248  /* Check the parameters */
2250  assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
2251  /* Reset the MSM Bit */
2252  TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
2253 
2254  /* Set or Reset the MSM Bit */
2255  TIMx->SMCR |= TIM_MasterSlaveMode;
2256 }
2257 
2264 void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)
2265 {
2266  /* Check the parameters */
2268  /* Set the Counter Register value */
2269  TIMx->CNT = Counter;
2270 }
2271 
2278 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)
2279 {
2280  /* Check the parameters */
2282  /* Set the Autoreload Register value */
2283  TIMx->ARR = Autoreload;
2284 }
2285 
2292 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)
2293 {
2294  /* Check the parameters */
2296  /* Set the Capture Compare1 Register value */
2297  TIMx->CCR1 = Compare1;
2298 }
2299 
2306 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
2307 {
2308  /* Check the parameters */
2310  /* Set the Capture Compare2 Register value */
2311  TIMx->CCR2 = Compare2;
2312 }
2313 
2320 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
2321 {
2322  /* Check the parameters */
2324  /* Set the Capture Compare3 Register value */
2325  TIMx->CCR3 = Compare3;
2326 }
2327 
2334 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
2335 {
2336  /* Check the parameters */
2338  /* Set the Capture Compare4 Register value */
2339  TIMx->CCR4 = Compare4;
2340 }
2341 
2353 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
2354 {
2355  /* Check the parameters */
2357  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
2358  /* Reset the IC1PSC Bits */
2359  TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
2360  /* Set the IC1PSC value */
2361  TIMx->CCMR1 |= TIM_ICPSC;
2362 }
2363 
2375 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
2376 {
2377  /* Check the parameters */
2379  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
2380  /* Reset the IC2PSC Bits */
2381  TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
2382  /* Set the IC2PSC value */
2383  TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
2384 }
2385 
2397 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
2398 {
2399  /* Check the parameters */
2401  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
2402  /* Reset the IC3PSC Bits */
2403  TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
2404  /* Set the IC3PSC value */
2405  TIMx->CCMR2 |= TIM_ICPSC;
2406 }
2407 
2419 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
2420 {
2421  /* Check the parameters */
2423  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
2424  /* Reset the IC4PSC Bits */
2425  TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
2426  /* Set the IC4PSC value */
2427  TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
2428 }
2429 
2441 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
2442 {
2443  /* Check the parameters */
2445  assert_param(IS_TIM_CKD_DIV(TIM_CKD));
2446  /* Reset the CKD Bits */
2447  TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
2448  /* Set the CKD value */
2449  TIMx->CR1 |= TIM_CKD;
2450 }
2451 
2458 {
2459  /* Check the parameters */
2461  /* Get the Capture 1 Register value */
2462  return TIMx->CCR1;
2463 }
2464 
2471 {
2472  /* Check the parameters */
2474  /* Get the Capture 2 Register value */
2475  return TIMx->CCR2;
2476 }
2477 
2484 {
2485  /* Check the parameters */
2487  /* Get the Capture 3 Register value */
2488  return TIMx->CCR3;
2489 }
2490 
2497 {
2498  /* Check the parameters */
2500  /* Get the Capture 4 Register value */
2501  return TIMx->CCR4;
2502 }
2503 
2510 {
2511  /* Check the parameters */
2513  /* Get the Counter Register value */
2514  return TIMx->CNT;
2515 }
2516 
2523 {
2524  /* Check the parameters */
2526  /* Get the Prescaler Register value */
2527  return TIMx->PSC;
2528 }
2529 
2556 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
2557 {
2558  ITStatus bitstatus = RESET;
2559  /* Check the parameters */
2561  assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
2562 
2563  if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
2564  {
2565  bitstatus = SET;
2566  }
2567  else
2568  {
2569  bitstatus = RESET;
2570  }
2571  return bitstatus;
2572 }
2573 
2600 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
2601 {
2602  /* Check the parameters */
2604  assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
2605 
2606  /* Clear the flags */
2607  TIMx->SR = (uint16_t)~TIM_FLAG;
2608 }
2609 
2632 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
2633 {
2634  ITStatus bitstatus = RESET;
2635  uint16_t itstatus = 0x0, itenable = 0x0;
2636  /* Check the parameters */
2638  assert_param(IS_TIM_GET_IT(TIM_IT));
2639 
2640  itstatus = TIMx->SR & TIM_IT;
2641 
2642  itenable = TIMx->DIER & TIM_IT;
2643  if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
2644  {
2645  bitstatus = SET;
2646  }
2647  else
2648  {
2649  bitstatus = RESET;
2650  }
2651  return bitstatus;
2652 }
2653 
2676 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
2677 {
2678  /* Check the parameters */
2680  assert_param(IS_TIM_IT(TIM_IT));
2681  /* Clear the IT pending Bit */
2682  TIMx->SR = (uint16_t)~TIM_IT;
2683 }
2684 
2701 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
2702  uint16_t TIM_ICFilter)
2703 {
2704  uint16_t tmpccmr1 = 0, tmpccer = 0;
2705  /* Disable the Channel 1: Reset the CC1E Bit */
2706  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
2707  tmpccmr1 = TIMx->CCMR1;
2708  tmpccer = TIMx->CCER;
2709  /* Select the Input and set the filter */
2710  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
2711  tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
2712 
2713  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
2714  (TIMx == TIM4) ||(TIMx == TIM5))
2715  {
2716  /* Select the Polarity and set the CC1E Bit */
2717  tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P));
2718  tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
2719  }
2720  else
2721  {
2722  /* Select the Polarity and set the CC1E Bit */
2723  tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
2724  tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
2725  }
2726 
2727  /* Write to TIMx CCMR1 and CCER registers */
2728  TIMx->CCMR1 = tmpccmr1;
2729  TIMx->CCER = tmpccer;
2730 }
2731 
2748 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
2749  uint16_t TIM_ICFilter)
2750 {
2751  uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
2752  /* Disable the Channel 2: Reset the CC2E Bit */
2753  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
2754  tmpccmr1 = TIMx->CCMR1;
2755  tmpccer = TIMx->CCER;
2756  tmp = (uint16_t)(TIM_ICPolarity << 4);
2757  /* Select the Input and set the filter */
2758  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
2759  tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
2760  tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
2761 
2762  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
2763  (TIMx == TIM4) ||(TIMx == TIM5))
2764  {
2765  /* Select the Polarity and set the CC2E Bit */
2766  tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P));
2767  tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
2768  }
2769  else
2770  {
2771  /* Select the Polarity and set the CC2E Bit */
2772  tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
2773  tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E);
2774  }
2775 
2776  /* Write to TIMx CCMR1 and CCER registers */
2777  TIMx->CCMR1 = tmpccmr1 ;
2778  TIMx->CCER = tmpccer;
2779 }
2780 
2797 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
2798  uint16_t TIM_ICFilter)
2799 {
2800  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
2801  /* Disable the Channel 3: Reset the CC3E Bit */
2802  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
2803  tmpccmr2 = TIMx->CCMR2;
2804  tmpccer = TIMx->CCER;
2805  tmp = (uint16_t)(TIM_ICPolarity << 8);
2806  /* Select the Input and set the filter */
2807  tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
2808  tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
2809 
2810  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
2811  (TIMx == TIM4) ||(TIMx == TIM5))
2812  {
2813  /* Select the Polarity and set the CC3E Bit */
2814  tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P));
2815  tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
2816  }
2817  else
2818  {
2819  /* Select the Polarity and set the CC3E Bit */
2820  tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
2821  tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E);
2822  }
2823 
2824  /* Write to TIMx CCMR2 and CCER registers */
2825  TIMx->CCMR2 = tmpccmr2;
2826  TIMx->CCER = tmpccer;
2827 }
2828 
2845 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
2846  uint16_t TIM_ICFilter)
2847 {
2848  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
2849 
2850  /* Disable the Channel 4: Reset the CC4E Bit */
2851  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
2852  tmpccmr2 = TIMx->CCMR2;
2853  tmpccer = TIMx->CCER;
2854  tmp = (uint16_t)(TIM_ICPolarity << 12);
2855  /* Select the Input and set the filter */
2856  tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
2857  tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
2858  tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
2859 
2860  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
2861  (TIMx == TIM4) ||(TIMx == TIM5))
2862  {
2863  /* Select the Polarity and set the CC4E Bit */
2864  tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P));
2865  tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
2866  }
2867  else
2868  {
2869  /* Select the Polarity and set the CC4E Bit */
2870  tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP));
2871  tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E);
2872  }
2873  /* Write to TIMx CCMR2 and CCER registers */
2874  TIMx->CCMR2 = tmpccmr2;
2875  TIMx->CCER = tmpccer;
2876 }
2877 
2890 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
#define TIM_CCMR1_OC1FE
Definition: stm32f4xx.h:10528
void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
Configures the TIMx Encoder Interface.
#define IS_TIM_COUNTER_MODE(MODE)
FlagStatus
Definition: stm32f4xx.h:706
#define IS_TIM_CKD_DIV(DIV)
void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct)
Fills each TIM_OCInitStruct member with its default value.
void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeB...
#define TIM_PSCReloadMode_Immediate
#define IS_TIM_OC_MODE(MODE)
#define TIM_TS_ETRF
#define RCC_APB2Periph_TIM17
#define TIM_CCER_CC3NE
Definition: stm32f4xx.h:10636
void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode)
Specifies the TIMx Counter Mode to be used.
uint16_t TIM_OutputNState
Definition: stm32f4xx_tim.h:92
#define TIM4
Definition: stm32f4xx.h:2039
#define IS_TIM_EVENT_SOURCE(SOURCE)
void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 2 Fast feature.
#define IS_TIM_SLAVE_MODE(MODE)
uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx)
Gets the TIMx Prescaler value.
#define IS_TIM_LIST3_PERIPH(PERIPH)
#define IS_TIM_TIXCLK_SOURCE(SOURCE)
#define TIM_OSSIState_Disable
#define TIM_AutomaticOutput_Disable
#define TIM_ICSelection_DirectTI
#define TIM_LOCKLevel_OFF
#define TIM_CCER_CC4P
Definition: stm32f4xx.h:10639
FunctionalState
Definition: stm32f4xx.h:708
void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 1N polarity.
#define TIM1
Definition: stm32f4xx.h:2078
#define TIM_CCMR1_OC1M
Definition: stm32f4xx.h:10531
#define TIM_CR2_CCDS
Definition: stm32f4xx.h:10440
void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 1 Fast feature.
#define IS_TIM_TRGO_SOURCE(SOURCE)
#define IS_TIM_EXT_POLARITY(POLARITY)
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Fills each TIM_TimeBaseInitStruct member with its default value.
__IO uint16_t CCER
Definition: stm32f4xx.h:1684
#define TIM_CCMR2_CC4S
Definition: stm32f4xx.h:10589
#define TIM_Channel_3
#define TIM_CCER_CC1NP
Definition: stm32f4xx.h:10629
#define TIM3
Definition: stm32f4xx.h:2038
#define TIM_CR2_OIS3N
Definition: stm32f4xx.h:10453
void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload)
Sets the TIMx Autoreload Register value.
void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 4 polarity.
#define TIM12
Definition: stm32f4xx.h:2043
void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT)
Checks whether the TIM interrupt has occurred or not.
#define IS_TIM_OUTPUTN_STATE(STATE)
#define IS_TIM_BREAK_STATE(STATE)
void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 1 prescaler.
#define TIM_CCMR1_OC2FE
Definition: stm32f4xx.h:10542
#define TIM9
Definition: stm32f4xx.h:2091
#define TIM_OCNIdleState_Reset
void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR1.
#define TIM2
Definition: stm32f4xx.h:2037
#define TIM_OutputNState_Disable
#define TIM8
Definition: stm32f4xx.h:2079
#define CCER_CCNE_Set
Definition: stm32f10x_tim.c:51
#define TIM_CCMR1_CC1S
Definition: stm32f4xx.h:10524
void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter)
Sets the TIMx Counter Register value.
void TIM_InternalClockConfig(TIM_TypeDef *TIMx)
Configures the TIMx internal Clock.
#define IS_TIM_PRESCALER_RELOAD(RELOAD)
void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 3 waveform to active or inactive level.
uint16_t TIM_AutomaticOutput
#define TIM_ICSelection_IndirectTI
void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 3 prescaler.
#define TIM_CR1_CEN
Definition: stm32f4xx.h:10421
#define TIM_CCER_CC3P
Definition: stm32f4xx.h:10635
#define IS_TIM_GET_IT(IT)
void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2)
Sets the TIMx Capture Compare2 Register value.
__IO uint16_t PSC
Definition: stm32f4xx.h:1687
void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1)
Sets the TIMx Capture Compare1 Register value.
#define TIM_ICPolarity_Falling
#define TIM_CCMR2_IC3F
Definition: stm32f4xx.h:10609
void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the specified TIM peripheral.
#define IS_TIM_UPDATE_SOURCE(SOURCE)
#define TIM_CCMR2_CC3S
Definition: stm32f4xx.h:10575
#define TIM_SlaveMode_External1
#define TIM_CCER_CC1E
Definition: stm32f4xx.h:10626
#define IS_TIM_LIST5_PERIPH(PERIPH)
__IO uint16_t CCMR1
Definition: stm32f4xx.h:1680
#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE)
#define TIM_CR1_CMS
Definition: stm32f4xx.h:10427
#define TIM_Channel_2
void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
Configures the TIMx Prescaler.
#define TIM_CR2_OIS1N
Definition: stm32f4xx.h:10449
void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Configures the TIMx Internal Trigger as External Clock.
#define IS_TIM_ENCODER_MODE(MODE)
void assert_param(int val)
#define TIM_CR2_OIS3
Definition: stm32f4xx.h:10452
#define IS_TIM_OCFAST_STATE(STATE)
void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF3 signal on an external event.
#define IS_TIM_IC_PRESCALER(PRESCALER)
#define IS_TIM_OCM(MODE)
#define IS_TIM_CCX(CCX)
#define IS_TIM_GET_FLAG(FLAG)
#define TIM17
Definition: stm32f10x.h:1424
#define TIM_CCMR2_OC4FE
Definition: stm32f4xx.h:10593
#define TIM_CCMR2_OC3FE
Definition: stm32f4xx.h:10579
#define TIM_CCMR2_OC3CE
Definition: stm32f4xx.h:10587
This file contains all the functions prototypes for the TIM firmware library.
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
#define RCC_APB2Periph_TIM16
void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
Enables or disables the TIMx&#39;s DMA Requests.
uint16_t TIM_ICPolarity
#define SMCR_ETR_Mask
Definition: stm32f10x_tim.c:48
void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF4 signal on an external event.
__IO uint32_t CCR3
Definition: stm32f4xx.h:1694
#define TIM_CCMR1_OC2PE
Definition: stm32f4xx.h:10543
void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 2 prescaler.
void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or Disables the TIMx Update event.
#define TIM15
Definition: stm32f10x.h:1422
#define IS_TIM_BREAK_POLARITY(POLARITY)
#define TIM_CR2_OIS2N
Definition: stm32f4xx.h:10451
#define RCC_APB2Periph_TIM15
void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR4.
uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 4 value.
#define IS_TIM_OSSI_STATE(STATE)
__IO uint32_t CCR1
Definition: stm32f4xx.h:1692
#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL)
Definition: stm32f4xx.h:706
#define TIM_OSSRState_Disable
#define TIM_CR1_UDIS
Definition: stm32f4xx.h:10422
#define IS_TIM_LIST1_PERIPH(PERIPH)
uint16_t TIM_ICPrescaler
#define TIM_CR1_URS
Definition: stm32f4xx.h:10423
enum FlagStatus ITStatus
#define IS_TIM_LOCK_LEVEL(LEVEL)
void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Selects the Input Trigger source.
uint16_t TIM_OCPolarity
Definition: stm32f4xx_tim.h:99
#define TIM_CCER_CC4NP
Definition: stm32f4xx.h:10640
#define TIM_CCMR1_IC1F
Definition: stm32f4xx.h:10558
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
__IO uint16_t DCR
Definition: stm32f4xx.h:1698
void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF1 signal on an external event.
#define TIM_CCMR2_OC4CE
Definition: stm32f4xx.h:10601
#define IS_TIM_CLEAR_FLAG(TIM_FLAG)
#define TIM_TIxExternalCLK1Source_TI2
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Fills each TIM_BDTRInitStruct member with its default value.
void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.
#define TIM6
Definition: stm32f4xx.h:2041
#define TIM_CCMR1_CC2S_0
Definition: stm32f4xx.h:10539
#define __IO
Definition: core_cm0.h:198
#define TIM_CCER_CC3E
Definition: stm32f4xx.h:10634
#define IS_TIM_OSSR_STATE(STATE)
void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 2 polarity.
#define TIM_CCMR1_OC2CE
Definition: stm32f4xx.h:10550
#define TIM5
Definition: stm32f4xx.h:2040
void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIMx&#39;s Hall sensor interface.
void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 4 prescaler.
#define TIM_CKD_DIV1
static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI2 as Input.
#define IS_TIM_LIST2_PERIPH(PERIPH)
#define TIM_CR2_CCPC
Definition: stm32f4xx.h:10438
#define IS_TIM_CHANNEL(CHANNEL)
#define TIM_SMCR_ECE
Definition: stm32f4xx.h:10479
#define TIM_CR2_MMS
Definition: stm32f4xx.h:10442
#define TIM_CCMR2_OC4PE
Definition: stm32f4xx.h:10594
#define IS_TIM_EXT_FILTER(EXTFILTER)
#define TIM_Channel_1
#define TIM_CCMR2_OC3M
Definition: stm32f4xx.h:10582
#define TIM_ICPolarity_Rising
void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIM peripheral Main Outputs.
#define TIM_CR1_DIR
Definition: stm32f4xx.h:10425
uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 3 value.
void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource)
Selects the TIMx Trigger Output Mode.
#define TIM_CCER_CC2NP
Definition: stm32f4xx.h:10633
#define IS_TIM_OCCLEAR_STATE(STATE)
#define IS_TIM_CCXN(CCXN)
#define TIM10
Definition: stm32f4xx.h:2092
#define IS_TIM_IC_POLARITY(POLARITY)
#define IS_TIM_DMA_SOURCE(SOURCE)
uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 1 value.
__IO uint32_t ARR
Definition: stm32f4xx.h:1689
#define TIM_CCER_CC2P
Definition: stm32f4xx.h:10631
#define TIM_CCER_CC3NP
Definition: stm32f4xx.h:10637
#define TIM_CCER_CC2E
Definition: stm32f4xx.h:10630
#define IS_TIM_DMA_LENGTH(LENGTH)
void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR2.
void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct.
void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource)
Configures the TIMx Update Request Interrupt source.
#define IS_TIM_ALL_PERIPH(PERIPH)
void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode)
Sets or Resets the TIMx Master/Slave Mode.
#define IS_TIM_LIST9_PERIPH(PERIPH)
TIM Time Base Init structure definition.
Definition: stm32f4xx_tim.h:55
void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Configures the: Break feature, dead time, Lock level, the OSSI, the OSSR State and the AOE(automatic ...
#define TIM_CCMR2_IC4F
Definition: stm32f4xx.h:10619
#define TIM_ICPSC_DIV1
#define TIM_OutputState_Disable
This file contains all the functions prototypes for the RCC firmware library.
void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode)
Selects the TIMx Slave Mode.
#define TIM_CCER_CC4E
Definition: stm32f4xx.h:10638
#define TIM_OCMode_Timing
uint16_t TIM_OCNPolarity
void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct.
#define TIM_BDTR_MOE
Definition: stm32f4xx.h:10686
void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct.
void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF2 signal on an external event.
#define TIM_CR1_ARPE
Definition: stm32f4xx.h:10431
static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI4 as Input.
#define IS_TIM_LIST7_PERIPH(PERIPH)
void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 1 waveform to active or inactive level.
#define TIM_SMCR_TS
Definition: stm32f4xx.h:10462
#define TIM_SMCR_MSM
Definition: stm32f4xx.h:10467
#define TIM_CR1_OPM
Definition: stm32f4xx.h:10424
TIM Input Capture Init structure definition.
__IO uint16_t BDTR
Definition: stm32f4xx.h:1696
uint16_t TIM_BreakPolarity
__IO uint32_t CCR4
Definition: stm32f4xx.h:1695
#define TIM_CCMR2_OC4M
Definition: stm32f4xx.h:10596
uint16_t TIM_OutputState
Definition: stm32f4xx_tim.h:89
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct)
Fills each TIM_ICInitStruct member with its default value.
void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode)
Selects the TIMx&#39;s One Pulse Mode.
#define IS_TIM_IC_SELECTION(SELECTION)
#define TIM13
Definition: stm32f4xx.h:2044
static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI3 as Input.
#define TIM_CCMR1_OC1CE
Definition: stm32f4xx.h:10536
#define TIM_CCER_CC1NE
Definition: stm32f4xx.h:10628
#define TIM_CCER_CC2NE
Definition: stm32f4xx.h:10632
uint16_t TIM_ICSelection
#define TIM_CCMR1_IC2F
Definition: stm32f4xx.h:10568
#define TIM11
Definition: stm32f4xx.h:2093
void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Clears the TIMx&#39;s pending flags.
#define TIM_CCMR1_CC2S
Definition: stm32f4xx.h:10538
#define TIM_CR2_TI1S
Definition: stm32f4xx.h:10447
#define IS_TIM_OCNIDLE_STATE(STATE)
__IO uint16_t SR
Definition: stm32f4xx.h:1676
uint16_t TIM_OCNIdleState
#define TIM_CCMR2_IC3PSC
Definition: stm32f4xx.h:10605
#define TIM_CCMR2_OC3PE
Definition: stm32f4xx.h:10580
#define IS_TIM_TRIGGER_SELECTION(SELECTION)
void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measur...
void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR3.
#define TIM_CR2_OIS2
Definition: stm32f4xx.h:10450
#define TIM_OCPolarity_High
#define IS_TIM_IC_FILTER(ICFILTER)
void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD)
Sets the TIMx Clock Division value.
void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT)
Clears the TIMx&#39;s interrupt pending bits.
#define CCMR_Offset
Definition: stm32f10x_tim.c:49
#define TIM_BreakPolarity_Low
void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
Enables or disables the TIM Capture Compare Channel x.
#define IS_TIM_IT(IT)
#define TIM_SMCR_SMS
Definition: stm32f4xx.h:10457
uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 2 value.
__IO uint16_t CCMR2
Definition: stm32f4xx.h:1682
__IO uint16_t CR2
Definition: stm32f4xx.h:1670
#define IS_TIM_LIST4_PERIPH(PERIPH)
#define TIM_CCMR1_IC1PSC
Definition: stm32f4xx.h:10554
void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4)
Sets the TIMx Capture Compare4 Register value.
void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
Enables or disables the TIM Capture Compare Channel xN.
void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIMx peripheral Capture Compare DMA source.
void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter)
Configures the TIMx Trigger as External Clock.
void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode1.
uint16_t TIM_GetCounter(TIM_TypeDef *TIMx)
Gets the TIMx Counter value.
#define TIM_OCIdleState_Reset
#define TIM_UpdateSource_Global
#define IS_TIM_LIST6_PERIPH(TIMx)
__IO uint16_t CR1
Definition: stm32f4xx.h:1668
#define TIM_Break_Disable
#define IS_TIM_OC_POLARITY(POLARITY)
#define IS_TIM_OUTPUT_STATE(STATE)
void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 3N polarity.
#define IS_TIM_DMA_BASE(BASE)
#define TIM_CR2_CCUS
Definition: stm32f4xx.h:10439
void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 3 Fast feature.
FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Checks whether the specified TIM flag is set or not.
__IO uint16_t DIER
Definition: stm32f4xx.h:1674
void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState)
Enables or disables the specified TIM interrupts.
#define TIM_CR2_OIS1
Definition: stm32f4xx.h:10448
void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
Selects the TIM Output Compare Mode.
TIM Output Compare Init structure definition.
Definition: stm32f4xx_tim.h:84
void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 1 polarity.
#define TIM_CR2_OIS4
Definition: stm32f4xx.h:10454
#define TIM_CR1_CKD
Definition: stm32f4xx.h:10433
#define IS_TIM_MSM_STATE(STATE)
#define TIM_CCMR1_OC1PE
Definition: stm32f4xx.h:10529
void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode2.
void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct.
#define TIM_CCMR2_IC4PSC
Definition: stm32f4xx.h:10615
void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIM peripheral Commutation event.
#define TIM_CCER_CC1P
Definition: stm32f4xx.h:10627
void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 2N polarity.
BDTR structure definition.
__IO uint16_t SMCR
Definition: stm32f4xx.h:1672
void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 2 waveform to active or inactive level.
#define CCER_CCE_Set
Definition: stm32f10x_tim.c:50
#define IS_TIM_OCIDLE_STATE(STATE)
#define TIM14
Definition: stm32f4xx.h:2045
#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION)
void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 4 Fast feature.
#define TIM_CounterMode_Up
void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource)
Configures the TIMx event to be generate by software.
__IO uint32_t CNT
Definition: stm32f4xx.h:1686
#define IS_TIM_OPM_MODE(MODE)
__IO uint32_t CCR2
Definition: stm32f4xx.h:1693
#define IS_TIM_OCPRELOAD_STATE(STATE)
#define TIM_CCMR1_CC1S_0
Definition: stm32f4xx.h:10525
#define IS_TIM_OCN_POLARITY(POLARITY)
void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables TIMx peripheral Preload register on ARR.
#define IS_TIM_FORCED_ACTION(ACTION)
__IO uint16_t EGR
Definition: stm32f4xx.h:1678
#define TIM_CCMR1_OC2M
Definition: stm32f4xx.h:10545
uint16_t TIM_OCIdleState
static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter)
Configure the TI1 as Input.
#define TIM_CCMR1_IC2PSC
Definition: stm32f4xx.h:10564
#define IS_TIM_EXT_PRESCALER(PRESCALER)
void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3)
Sets the TIMx Capture Compare3 Register value.
void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 3 polarity.
void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
Configures the TIMx&#39;s DMA interface.
#define IS_TIM_LIST8_PERIPH(PERIPH)
#define IS_TIM_IC_POLARITY_LITE(POLARITY)
void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState)
Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 4 waveform to active or inactive level.
#define TIM7
Definition: stm32f4xx.h:2042
__IO uint16_t RCR
Definition: stm32f4xx.h:1690
void TIM_DeInit(TIM_TypeDef *TIMx)
Deinitializes the TIMx peripheral registers to their default reset values.
#define TIM16
Definition: stm32f10x.h:1423


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19