stm32f10x_i2c.c
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1 
22 /* Includes ------------------------------------------------------------------*/
23 #include "stm32f10x_i2c.h"
24 #include "stm32f10x_rcc.h"
25 
26 
48 /* I2C SPE mask */
49 #define CR1_PE_Set ((uint16_t)0x0001)
50 #define CR1_PE_Reset ((uint16_t)0xFFFE)
51 
52 /* I2C START mask */
53 #define CR1_START_Set ((uint16_t)0x0100)
54 #define CR1_START_Reset ((uint16_t)0xFEFF)
55 
56 /* I2C STOP mask */
57 #define CR1_STOP_Set ((uint16_t)0x0200)
58 #define CR1_STOP_Reset ((uint16_t)0xFDFF)
59 
60 /* I2C ACK mask */
61 #define CR1_ACK_Set ((uint16_t)0x0400)
62 #define CR1_ACK_Reset ((uint16_t)0xFBFF)
63 
64 /* I2C ENGC mask */
65 #define CR1_ENGC_Set ((uint16_t)0x0040)
66 #define CR1_ENGC_Reset ((uint16_t)0xFFBF)
67 
68 /* I2C SWRST mask */
69 #define CR1_SWRST_Set ((uint16_t)0x8000)
70 #define CR1_SWRST_Reset ((uint16_t)0x7FFF)
71 
72 /* I2C PEC mask */
73 #define CR1_PEC_Set ((uint16_t)0x1000)
74 #define CR1_PEC_Reset ((uint16_t)0xEFFF)
75 
76 /* I2C ENPEC mask */
77 #define CR1_ENPEC_Set ((uint16_t)0x0020)
78 #define CR1_ENPEC_Reset ((uint16_t)0xFFDF)
79 
80 /* I2C ENARP mask */
81 #define CR1_ENARP_Set ((uint16_t)0x0010)
82 #define CR1_ENARP_Reset ((uint16_t)0xFFEF)
83 
84 /* I2C NOSTRETCH mask */
85 #define CR1_NOSTRETCH_Set ((uint16_t)0x0080)
86 #define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F)
87 
88 /* I2C registers Masks */
89 #define CR1_CLEAR_Mask ((uint16_t)0xFBF5)
90 
91 /* I2C DMAEN mask */
92 #define CR2_DMAEN_Set ((uint16_t)0x0800)
93 #define CR2_DMAEN_Reset ((uint16_t)0xF7FF)
94 
95 /* I2C LAST mask */
96 #define CR2_LAST_Set ((uint16_t)0x1000)
97 #define CR2_LAST_Reset ((uint16_t)0xEFFF)
98 
99 /* I2C FREQ mask */
100 #define CR2_FREQ_Reset ((uint16_t)0xFFC0)
101 
102 /* I2C ADD0 mask */
103 #define OAR1_ADD0_Set ((uint16_t)0x0001)
104 #define OAR1_ADD0_Reset ((uint16_t)0xFFFE)
105 
106 /* I2C ENDUAL mask */
107 #define OAR2_ENDUAL_Set ((uint16_t)0x0001)
108 #define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE)
109 
110 /* I2C ADD2 mask */
111 #define OAR2_ADD2_Reset ((uint16_t)0xFF01)
112 
113 /* I2C F/S mask */
114 #define CCR_FS_Set ((uint16_t)0x8000)
115 
116 /* I2C CCR mask */
117 #define CCR_CCR_Set ((uint16_t)0x0FFF)
118 
119 /* I2C FLAG mask */
120 #define FLAG_Mask ((uint32_t)0x00FFFFFF)
121 
122 /* I2C Interrupt Enable mask */
123 #define ITEN_Mask ((uint32_t)0x07000000)
124 
163 {
164  /* Check the parameters */
166 
167  if (I2Cx == I2C1)
168  {
169  /* Enable I2C1 reset state */
171  /* Release I2C1 from reset state */
173  }
174  else
175  {
176  /* Enable I2C2 reset state */
178  /* Release I2C2 from reset state */
180  }
181 }
182 
191 void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
192 {
193  uint16_t tmpreg = 0, freqrange = 0;
194  uint16_t result = 0x04;
195  uint32_t pclk1 = 8000000;
196  RCC_ClocksTypeDef rcc_clocks;
197  /* Check the parameters */
200  assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
201  assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
203  assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
205 
206 /*---------------------------- I2Cx CR2 Configuration ------------------------*/
207  /* Get the I2Cx CR2 value */
208  tmpreg = I2Cx->CR2;
209  /* Clear frequency FREQ[5:0] bits */
210  tmpreg &= CR2_FREQ_Reset;
211  /* Get pclk1 frequency value */
212  RCC_GetClocksFreq(&rcc_clocks);
213  pclk1 = rcc_clocks.PCLK1_Frequency;
214  /* Set frequency bits depending on pclk1 value */
215  freqrange = (uint16_t)(pclk1 / 1000000);
216  tmpreg |= freqrange;
217  /* Write to I2Cx CR2 */
218  I2Cx->CR2 = tmpreg;
219 
220 /*---------------------------- I2Cx CCR Configuration ------------------------*/
221  /* Disable the selected I2C peripheral to configure TRISE */
222  I2Cx->CR1 &= CR1_PE_Reset;
223  /* Reset tmpreg value */
224  /* Clear F/S, DUTY and CCR[11:0] bits */
225  tmpreg = 0;
226 
227  /* Configure speed in standard mode */
228  if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
229  {
230  /* Standard mode speed calculate */
231  result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
232  /* Test if CCR value is under 0x4*/
233  if (result < 0x04)
234  {
235  /* Set minimum allowed value */
236  result = 0x04;
237  }
238  /* Set speed value for standard mode */
239  tmpreg |= result;
240  /* Set Maximum Rise Time for standard mode */
241  I2Cx->TRISE = freqrange + 1;
242  }
243  /* Configure speed in fast mode */
244  else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
245  {
246  if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
247  {
248  /* Fast mode speed calculate: Tlow/Thigh = 2 */
249  result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
250  }
251  else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
252  {
253  /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
254  result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
255  /* Set DUTY bit */
256  result |= I2C_DutyCycle_16_9;
257  }
258 
259  /* Test if CCR value is under 0x1*/
260  if ((result & CCR_CCR_Set) == 0)
261  {
262  /* Set minimum allowed value */
263  result |= (uint16_t)0x0001;
264  }
265  /* Set speed value and set F/S bit for fast mode */
266  tmpreg |= (uint16_t)(result | CCR_FS_Set);
267  /* Set Maximum Rise Time for fast mode */
268  I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
269  }
270 
271  /* Write to I2Cx CCR */
272  I2Cx->CCR = tmpreg;
273  /* Enable the selected I2C peripheral */
274  I2Cx->CR1 |= CR1_PE_Set;
275 
276 /*---------------------------- I2Cx CR1 Configuration ------------------------*/
277  /* Get the I2Cx CR1 value */
278  tmpreg = I2Cx->CR1;
279  /* Clear ACK, SMBTYPE and SMBUS bits */
280  tmpreg &= CR1_CLEAR_Mask;
281  /* Configure I2Cx: mode and acknowledgement */
282  /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
283  /* Set ACK bit according to I2C_Ack value */
284  tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
285  /* Write to I2Cx CR1 */
286  I2Cx->CR1 = tmpreg;
287 
288 /*---------------------------- I2Cx OAR1 Configuration -----------------------*/
289  /* Set I2Cx Own Address1 and acknowledged address */
290  I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
291 }
292 
298 void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
299 {
300 /*---------------- Reset I2C init structure parameters values ----------------*/
301  /* initialize the I2C_ClockSpeed member */
302  I2C_InitStruct->I2C_ClockSpeed = 5000;
303  /* Initialize the I2C_Mode member */
304  I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
305  /* Initialize the I2C_DutyCycle member */
306  I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
307  /* Initialize the I2C_OwnAddress1 member */
308  I2C_InitStruct->I2C_OwnAddress1 = 0;
309  /* Initialize the I2C_Ack member */
310  I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
311  /* Initialize the I2C_AcknowledgedAddress member */
313 }
314 
323 {
324  /* Check the parameters */
327  if (NewState != DISABLE)
328  {
329  /* Enable the selected I2C peripheral */
330  I2Cx->CR1 |= CR1_PE_Set;
331  }
332  else
333  {
334  /* Disable the selected I2C peripheral */
335  I2Cx->CR1 &= CR1_PE_Reset;
336  }
337 }
338 
347 {
348  /* Check the parameters */
351  if (NewState != DISABLE)
352  {
353  /* Enable the selected I2C DMA requests */
354  I2Cx->CR2 |= CR2_DMAEN_Set;
355  }
356  else
357  {
358  /* Disable the selected I2C DMA requests */
359  I2Cx->CR2 &= CR2_DMAEN_Reset;
360  }
361 }
362 
371 {
372  /* Check the parameters */
375  if (NewState != DISABLE)
376  {
377  /* Next DMA transfer is the last transfer */
378  I2Cx->CR2 |= CR2_LAST_Set;
379  }
380  else
381  {
382  /* Next DMA transfer is not the last transfer */
383  I2Cx->CR2 &= CR2_LAST_Reset;
384  }
385 }
386 
395 {
396  /* Check the parameters */
399  if (NewState != DISABLE)
400  {
401  /* Generate a START condition */
402  I2Cx->CR1 |= CR1_START_Set;
403  }
404  else
405  {
406  /* Disable the START condition generation */
407  I2Cx->CR1 &= CR1_START_Reset;
408  }
409 }
410 
419 {
420  /* Check the parameters */
423  if (NewState != DISABLE)
424  {
425  /* Generate a STOP condition */
426  I2Cx->CR1 |= CR1_STOP_Set;
427  }
428  else
429  {
430  /* Disable the STOP condition generation */
431  I2Cx->CR1 &= CR1_STOP_Reset;
432  }
433 }
434 
443 {
444  /* Check the parameters */
447  if (NewState != DISABLE)
448  {
449  /* Enable the acknowledgement */
450  I2Cx->CR1 |= CR1_ACK_Set;
451  }
452  else
453  {
454  /* Disable the acknowledgement */
455  I2Cx->CR1 &= CR1_ACK_Reset;
456  }
457 }
458 
465 void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
466 {
467  uint16_t tmpreg = 0;
468 
469  /* Check the parameters */
471 
472  /* Get the old register value */
473  tmpreg = I2Cx->OAR2;
474 
475  /* Reset I2Cx Own address2 bit [7:1] */
476  tmpreg &= OAR2_ADD2_Reset;
477 
478  /* Set I2Cx Own address2 */
479  tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
480 
481  /* Store the new register value */
482  I2Cx->OAR2 = tmpreg;
483 }
484 
493 {
494  /* Check the parameters */
497  if (NewState != DISABLE)
498  {
499  /* Enable dual addressing mode */
500  I2Cx->OAR2 |= OAR2_ENDUAL_Set;
501  }
502  else
503  {
504  /* Disable dual addressing mode */
505  I2Cx->OAR2 &= OAR2_ENDUAL_Reset;
506  }
507 }
508 
517 {
518  /* Check the parameters */
521  if (NewState != DISABLE)
522  {
523  /* Enable generall call */
524  I2Cx->CR1 |= CR1_ENGC_Set;
525  }
526  else
527  {
528  /* Disable generall call */
529  I2Cx->CR1 &= CR1_ENGC_Reset;
530  }
531 }
532 
545 void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
546 {
547  /* Check the parameters */
551 
552  if (NewState != DISABLE)
553  {
554  /* Enable the selected I2C interrupts */
555  I2Cx->CR2 |= I2C_IT;
556  }
557  else
558  {
559  /* Disable the selected I2C interrupts */
560  I2Cx->CR2 &= (uint16_t)~I2C_IT;
561  }
562 }
563 
570 void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
571 {
572  /* Check the parameters */
574  /* Write in the DR register the data to be sent */
575  I2Cx->DR = Data;
576 }
577 
584 {
585  /* Check the parameters */
587  /* Return the data in the DR register */
588  return (uint8_t)I2Cx->DR;
589 }
590 
601 void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
602 {
603  /* Check the parameters */
605  assert_param(IS_I2C_DIRECTION(I2C_Direction));
606  /* Test on the direction to set/reset the read/write bit */
607  if (I2C_Direction != I2C_Direction_Transmitter)
608  {
609  /* Set the address bit0 for read */
610  Address |= OAR1_ADD0_Set;
611  }
612  else
613  {
614  /* Reset the address bit0 for write */
615  Address &= OAR1_ADD0_Reset;
616  }
617  /* Send the address */
618  I2Cx->DR = Address;
619 }
620 
636 uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
637 {
638  __IO uint32_t tmp = 0;
639 
640  /* Check the parameters */
642  assert_param(IS_I2C_REGISTER(I2C_Register));
643 
644  tmp = (uint32_t) I2Cx;
645  tmp += I2C_Register;
646 
647  /* Return the selected register value */
648  return (*(__IO uint16_t *) tmp);
649 }
650 
659 {
660  /* Check the parameters */
663  if (NewState != DISABLE)
664  {
665  /* Peripheral under reset */
666  I2Cx->CR1 |= CR1_SWRST_Set;
667  }
668  else
669  {
670  /* Peripheral not under reset */
671  I2Cx->CR1 &= CR1_SWRST_Reset;
672  }
673 }
674 
696 void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)
697 {
698  /* Check the parameters */
700  assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition));
701 
702  /* Check the input parameter */
703  if (I2C_NACKPosition == I2C_NACKPosition_Next)
704  {
705  /* Next byte in shift register is the last received byte */
706  I2Cx->CR1 |= I2C_NACKPosition_Next;
707  }
708  else
709  {
710  /* Current byte in shift register is the last received byte */
711  I2Cx->CR1 &= I2C_NACKPosition_Current;
712  }
713 }
714 
724 void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
725 {
726  /* Check the parameters */
728  assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
729  if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
730  {
731  /* Drive the SMBusAlert pin Low */
732  I2Cx->CR1 |= I2C_SMBusAlert_Low;
733  }
734  else
735  {
736  /* Drive the SMBusAlert pin High */
737  I2Cx->CR1 &= I2C_SMBusAlert_High;
738  }
739 }
740 
749 {
750  /* Check the parameters */
753  if (NewState != DISABLE)
754  {
755  /* Enable the selected I2C PEC transmission */
756  I2Cx->CR1 |= CR1_PEC_Set;
757  }
758  else
759  {
760  /* Disable the selected I2C PEC transmission */
761  I2Cx->CR1 &= CR1_PEC_Reset;
762  }
763 }
764 
779 void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
780 {
781  /* Check the parameters */
783  assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
784  if (I2C_PECPosition == I2C_PECPosition_Next)
785  {
786  /* Next byte in shift register is PEC */
787  I2Cx->CR1 |= I2C_PECPosition_Next;
788  }
789  else
790  {
791  /* Current byte in shift register is PEC */
792  I2Cx->CR1 &= I2C_PECPosition_Current;
793  }
794 }
795 
804 {
805  /* Check the parameters */
808  if (NewState != DISABLE)
809  {
810  /* Enable the selected I2C PEC calculation */
811  I2Cx->CR1 |= CR1_ENPEC_Set;
812  }
813  else
814  {
815  /* Disable the selected I2C PEC calculation */
816  I2Cx->CR1 &= CR1_ENPEC_Reset;
817  }
818 }
819 
826 {
827  /* Check the parameters */
829  /* Return the selected I2C PEC value */
830  return ((I2Cx->SR2) >> 8);
831 }
832 
841 {
842  /* Check the parameters */
845  if (NewState != DISABLE)
846  {
847  /* Enable the selected I2C ARP */
848  I2Cx->CR1 |= CR1_ENARP_Set;
849  }
850  else
851  {
852  /* Disable the selected I2C ARP */
853  I2Cx->CR1 &= CR1_ENARP_Reset;
854  }
855 }
856 
865 {
866  /* Check the parameters */
869  if (NewState == DISABLE)
870  {
871  /* Enable the selected I2C Clock stretching */
872  I2Cx->CR1 |= CR1_NOSTRETCH_Set;
873  }
874  else
875  {
876  /* Disable the selected I2C Clock stretching */
877  I2Cx->CR1 &= CR1_NOSTRETCH_Reset;
878  }
879 }
880 
890 void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
891 {
892  /* Check the parameters */
894  assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
895  if (I2C_DutyCycle != I2C_DutyCycle_16_9)
896  {
897  /* I2C fast mode Tlow/Thigh=2 */
898  I2Cx->CCR &= I2C_DutyCycle_2;
899  }
900  else
901  {
902  /* I2C fast mode Tlow/Thigh=16/9 */
903  I2Cx->CCR |= I2C_DutyCycle_16_9;
904  }
905 }
906 
907 
908 
1031 {
1032  uint32_t lastevent = 0;
1033  uint32_t flag1 = 0, flag2 = 0;
1035 
1036  /* Check the parameters */
1038  assert_param(IS_I2C_EVENT(I2C_EVENT));
1039 
1040  /* Read the I2Cx status register */
1041  flag1 = I2Cx->SR1;
1042  flag2 = I2Cx->SR2;
1043  flag2 = flag2 << 16;
1044 
1045  /* Get the last event value from I2C status register */
1046  lastevent = (flag1 | flag2) & FLAG_Mask;
1047 
1048  /* Check whether the last event contains the I2C_EVENT */
1049  if ((lastevent & I2C_EVENT) == I2C_EVENT)
1050  {
1051  /* SUCCESS: last event is equal to I2C_EVENT */
1052  status = SUCCESS;
1053  }
1054  else
1055  {
1056  /* ERROR: last event is different from I2C_EVENT */
1057  status = ERROR;
1058  }
1059  /* Return status */
1060  return status;
1061 }
1062 
1079 {
1080  uint32_t lastevent = 0;
1081  uint32_t flag1 = 0, flag2 = 0;
1082 
1083  /* Check the parameters */
1085 
1086  /* Read the I2Cx status register */
1087  flag1 = I2Cx->SR1;
1088  flag2 = I2Cx->SR2;
1089  flag2 = flag2 << 16;
1090 
1091  /* Get the last event value from I2C status register */
1092  lastevent = (flag1 | flag2) & FLAG_Mask;
1093 
1094  /* Return status */
1095  return lastevent;
1096 }
1097 
1134 {
1135  FlagStatus bitstatus = RESET;
1136  __IO uint32_t i2creg = 0, i2cxbase = 0;
1137 
1138  /* Check the parameters */
1140  assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
1141 
1142  /* Get the I2Cx peripheral base address */
1143  i2cxbase = (uint32_t)I2Cx;
1144 
1145  /* Read flag register index */
1146  i2creg = I2C_FLAG >> 28;
1147 
1148  /* Get bit[23:0] of the flag */
1149  I2C_FLAG &= FLAG_Mask;
1150 
1151  if(i2creg != 0)
1152  {
1153  /* Get the I2Cx SR1 register address */
1154  i2cxbase += 0x14;
1155  }
1156  else
1157  {
1158  /* Flag in I2Cx SR2 Register */
1159  I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
1160  /* Get the I2Cx SR2 register address */
1161  i2cxbase += 0x18;
1162  }
1163 
1164  if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
1165  {
1166  /* I2C_FLAG is set */
1167  bitstatus = SET;
1168  }
1169  else
1170  {
1171  /* I2C_FLAG is reset */
1172  bitstatus = RESET;
1173  }
1174 
1175  /* Return the I2C_FLAG status */
1176  return bitstatus;
1177 }
1178 
1179 
1180 
1212 void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
1213 {
1214  uint32_t flagpos = 0;
1215  /* Check the parameters */
1217  assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
1218  /* Get the I2C flag position */
1219  flagpos = I2C_FLAG & FLAG_Mask;
1220  /* Clear the selected I2C flag */
1221  I2Cx->SR1 = (uint16_t)~flagpos;
1222 }
1223 
1247 {
1248  ITStatus bitstatus = RESET;
1249  uint32_t enablestatus = 0;
1250 
1251  /* Check the parameters */
1253  assert_param(IS_I2C_GET_IT(I2C_IT));
1254 
1255  /* Check if the interrupt source is enabled or not */
1256  enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ;
1257 
1258  /* Get bit[23:0] of the flag */
1259  I2C_IT &= FLAG_Mask;
1260 
1261  /* Check the status of the specified I2C flag */
1262  if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
1263  {
1264  /* I2C_IT is set */
1265  bitstatus = SET;
1266  }
1267  else
1268  {
1269  /* I2C_IT is reset */
1270  bitstatus = RESET;
1271  }
1272  /* Return the I2C_IT status */
1273  return bitstatus;
1274 }
1275 
1307 void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
1308 {
1309  uint32_t flagpos = 0;
1310  /* Check the parameters */
1312  assert_param(IS_I2C_CLEAR_IT(I2C_IT));
1313  /* Get the I2C flag position */
1314  flagpos = I2C_IT & FLAG_Mask;
1315  /* Clear the selected I2C flag */
1316  I2Cx->SR1 = (uint16_t)~flagpos;
1317 }
1318 
1331 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle)
Selects the specified I2C fast mode duty cycle.
FlagStatus
Definition: stm32f4xx.h:706
#define CR1_ENGC_Set
Definition: stm32f10x_i2c.c:65
uint16_t I2C_Ack
Definition: stm32f4xx_i2c.h:68
#define IS_I2C_CLEAR_FLAG(FLAG)
void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
Initializes the I2Cx peripheral according to the specified parameters in the I2C_InitStruct.
#define CR1_CLEAR_Mask
Definition: stm32f10x_i2c.c:89
#define CR1_NOSTRETCH_Reset
Definition: stm32f10x_i2c.c:86
void I2C_DeInit(I2C_TypeDef *I2Cx)
Deinitializes the I2Cx peripheral registers to their default reset values.
#define IS_I2C_CONFIG_IT(IT)
FunctionalState
Definition: stm32f4xx.h:708
#define IS_I2C_EVENT(EVENT)
#define CR1_START_Reset
Definition: stm32f10x_i2c.c:54
#define CR2_LAST_Set
Definition: stm32f10x_i2c.c:96
#define CR1_NOSTRETCH_Set
Definition: stm32f10x_i2c.c:85
uint16_t I2C_AcknowledgedAddress
Definition: stm32f4xx_i2c.h:71
void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C ARP.
#define IS_I2C_REGISTER(REGISTER)
#define CR1_ACK_Reset
Definition: stm32f10x_i2c.c:62
#define I2C_DutyCycle_2
#define I2C_Mode_I2C
void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Specifies if the next DMA transfer will be the last one.
#define IS_I2C_SMBUS_ALERT(ALERT)
#define I2C_DutyCycle_16_9
#define IS_I2C_NACK_POSITION(POSITION)
#define IS_I2C_PEC_POSITION(POSITION)
__IO uint16_t CCR
Definition: stm32f4xx.h:1336
__IO uint16_t CR2
Definition: stm32f4xx.h:1324
#define CR1_ENGC_Reset
Definition: stm32f10x_i2c.c:66
__IO uint16_t OAR1
Definition: stm32f4xx.h:1326
__IO uint16_t DR
Definition: stm32f4xx.h:1330
uint16_t I2C_OwnAddress1
Definition: stm32f4xx_i2c.h:65
void assert_param(int val)
#define CR1_ENARP_Set
Definition: stm32f10x_i2c.c:81
static I2C_TypeDef * I2Cx
Definition: drv_i2c.c:64
void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C acknowledge feature.
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition)
Selects the specified I2C NACK position in master receiver mode. This function is useful in I2C Maste...
static volatile uint8_t * status
Definition: drv_i2c.c:102
void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C PEC transfer.
#define I2C_Direction_Transmitter
void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data)
Sends a data byte through the I2Cx peripheral.
#define I2C_NACKPosition_Next
__IO uint16_t SR2
Definition: stm32f4xx.h:1334
#define I2C_AcknowledgedAddress_7bit
ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
I2C State Monitoring Functions.
Definition: stm32f4xx.h:706
FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
Checks whether the specified I2C flag is set or not.
#define CR2_DMAEN_Set
Definition: stm32f10x_i2c.c:92
#define IS_I2C_ACK_STATE(STATE)
#define I2C_PECPosition_Next
void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
Clears the I2Cx&#39;s pending flags.
enum FlagStatus ITStatus
#define I2C_SMBusAlert_Low
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
#define CR1_PEC_Reset
Definition: stm32f10x_i2c.c:74
void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C peripheral.
#define OAR2_ADD2_Reset
#define CR1_PEC_Set
Definition: stm32f10x_i2c.c:73
#define OAR1_ADD0_Set
__IO uint16_t TRISE
Definition: stm32f4xx.h:1338
ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Checks whether the specified I2C interrupt has occurred or not.
#define __IO
Definition: core_cm0.h:198
#define CR1_PE_Set
Definition: stm32f10x_i2c.c:49
void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert)
Drives the SMBusAlert pin high or low for the specified I2C.
uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx)
Returns the most recent received data by the I2Cx peripheral.
#define IS_I2C_OWN_ADDRESS1(ADDRESS1)
#define CR1_STOP_Set
Definition: stm32f10x_i2c.c:57
#define IS_I2C_MODE(MODE)
#define IS_I2C_DIRECTION(DIRECTION)
#define FLAG_Mask
void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication START condition.
#define CR1_ENPEC_Reset
Definition: stm32f10x_i2c.c:78
#define I2C_SMBusAlert_High
This file contains all the functions prototypes for the RCC firmware library.
#define CR2_DMAEN_Reset
Definition: stm32f10x_i2c.c:93
void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Clears the I2Cxs interrupt pending bits.
uint32_t I2C_ClockSpeed
Definition: stm32f4xx_i2c.h:56
ErrorStatus
Definition: stm32f4xx.h:711
#define CCR_CCR_Set
__IO uint16_t SR1
Definition: stm32f4xx.h:1332
__IO uint16_t OAR2
Definition: stm32f4xx.h:1328
void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address)
Configures the specified I2C own address2.
#define CR1_ACK_Set
Definition: stm32f10x_i2c.c:61
I2C Init structure definition.
Definition: stm32f4xx_i2c.h:54
uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx)
Returns the PEC value for the specified I2C.
#define CR1_STOP_Reset
Definition: stm32f10x_i2c.c:58
void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C DMA requests.
void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C dual addressing mode.
#define OAR2_ENDUAL_Reset
#define IS_I2C_GET_IT(IT)
#define CR2_LAST_Reset
Definition: stm32f10x_i2c.c:97
#define CR1_PE_Reset
Definition: stm32f10x_i2c.c:50
#define IS_I2C_CLEAR_IT(IT)
#define CR1_ENPEC_Set
Definition: stm32f10x_i2c.c:77
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS)
void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication STOP condition.
#define CCR_FS_Set
#define I2C_NACKPosition_Current
#define CR2_FREQ_Reset
#define IS_I2C_CLOCK_SPEED(SPEED)
#define IS_I2C_GET_FLAG(FLAG)
#define OAR1_ADD0_Reset
Inter-integrated Circuit Interface.
Definition: stm32f4xx.h:1320
void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks)
Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2.
#define CR1_START_Set
Definition: stm32f10x_i2c.c:53
#define I2C_PECPosition_Current
__IO uint16_t CR1
Definition: stm32f4xx.h:1322
void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition)
Selects the specified I2C PEC position.
This file contains all the functions prototypes for the I2C firmware library.
#define I2C1
Definition: stm32f4xx.h:2060
void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction)
Transmits the address byte to select the slave device.
void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C Clock stretching.
void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C software reset.
#define CR1_SWRST_Set
Definition: stm32f10x_i2c.c:69
uint16_t I2C_DutyCycle
Definition: stm32f4xx_i2c.h:62
void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the PEC value calculation of the transferred bytes.
uint16_t I2C_Mode
Definition: stm32f4xx_i2c.h:59
#define IS_I2C_DUTY_CYCLE(CYCLE)
uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx)
Returns the last I2Cx Event.
void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState)
Enables or disables the specified I2C interrupts.
#define CR1_ENARP_Reset
Definition: stm32f10x_i2c.c:82
void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct)
Fills each I2C_InitStruct member with its default value.
uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register)
Reads the specified I2C register and returns its value.
#define I2C_Ack_Disable
void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C general call feature.
#define ITEN_Mask
#define CR1_SWRST_Reset
Definition: stm32f10x_i2c.c:70
#define IS_I2C_ALL_PERIPH(PERIPH)
Definition: stm32f4xx_i2c.h:82
#define OAR2_ENDUAL_Set


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19