stm32f10x_flash.c
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1 
22 /* Includes ------------------------------------------------------------------*/
23 #include "stm32f10x_flash.h"
24 
46 /* Flash Access Control Register bits */
47 #define ACR_LATENCY_Mask ((uint32_t)0x00000038)
48 #define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7)
49 #define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF)
50 
51 /* Flash Access Control Register bits */
52 #define ACR_PRFTBS_Mask ((uint32_t)0x00000020)
53 
54 /* Flash Control Register bits */
55 #define CR_PG_Set ((uint32_t)0x00000001)
56 #define CR_PG_Reset ((uint32_t)0x00001FFE)
57 #define CR_PER_Set ((uint32_t)0x00000002)
58 #define CR_PER_Reset ((uint32_t)0x00001FFD)
59 #define CR_MER_Set ((uint32_t)0x00000004)
60 #define CR_MER_Reset ((uint32_t)0x00001FFB)
61 #define CR_OPTPG_Set ((uint32_t)0x00000010)
62 #define CR_OPTPG_Reset ((uint32_t)0x00001FEF)
63 #define CR_OPTER_Set ((uint32_t)0x00000020)
64 #define CR_OPTER_Reset ((uint32_t)0x00001FDF)
65 #define CR_STRT_Set ((uint32_t)0x00000040)
66 #define CR_LOCK_Set ((uint32_t)0x00000080)
67 
68 /* FLASH Mask */
69 #define RDPRT_Mask ((uint32_t)0x00000002)
70 #define WRP0_Mask ((uint32_t)0x000000FF)
71 #define WRP1_Mask ((uint32_t)0x0000FF00)
72 #define WRP2_Mask ((uint32_t)0x00FF0000)
73 #define WRP3_Mask ((uint32_t)0xFF000000)
74 #define OB_USER_BFB2 ((uint16_t)0x0008)
75 
76 /* FLASH Keys */
77 #define RDP_Key ((uint16_t)0x00A5)
78 #define FLASH_KEY1 ((uint32_t)0x45670123)
79 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
80 
81 /* FLASH BANK address */
82 #define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF)
83 
84 /* Delay definition */
85 #define EraseTimeout ((uint32_t)0x000B0000)
86 #define ProgramTimeout ((uint32_t)0x00002000)
87 
254 void FLASH_SetLatency(uint32_t FLASH_Latency)
255 {
256  uint32_t tmpreg = 0;
257 
258  /* Check the parameters */
259  assert_param(IS_FLASH_LATENCY(FLASH_Latency));
260 
261  /* Read the ACR register */
262  tmpreg = FLASH->ACR;
263 
264  /* Sets the Latency value */
265  tmpreg &= ACR_LATENCY_Mask;
266  tmpreg |= FLASH_Latency;
267 
268  /* Write the ACR register */
269  FLASH->ACR = tmpreg;
270 }
271 
281 void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)
282 {
283  /* Check the parameters */
284  assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess));
285 
286  /* Enable or disable the Half cycle access */
287  FLASH->ACR &= ACR_HLFCYA_Mask;
288  FLASH->ACR |= FLASH_HalfCycleAccess;
289 }
290 
300 void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)
301 {
302  /* Check the parameters */
303  assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer));
304 
305  /* Enable or disable the Prefetch Buffer */
306  FLASH->ACR &= ACR_PRFTBE_Mask;
307  FLASH->ACR |= FLASH_PrefetchBuffer;
308 }
309 
319 void FLASH_Unlock(void)
320 {
321  /* Authorize the FPEC of Bank1 Access */
322  FLASH->KEYR = FLASH_KEY1;
323  FLASH->KEYR = FLASH_KEY2;
324 
325 #ifdef STM32F10X_XL
326  /* Authorize the FPEC of Bank2 Access */
327  FLASH->KEYR2 = FLASH_KEY1;
328  FLASH->KEYR2 = FLASH_KEY2;
329 #endif /* STM32F10X_XL */
330 }
341 {
342  /* Authorize the FPEC of Bank1 Access */
343  FLASH->KEYR = FLASH_KEY1;
344  FLASH->KEYR = FLASH_KEY2;
345 }
346 
347 #ifdef STM32F10X_XL
348 
354 void FLASH_UnlockBank2(void)
355 {
356  /* Authorize the FPEC of Bank2 Access */
357  FLASH->KEYR2 = FLASH_KEY1;
358  FLASH->KEYR2 = FLASH_KEY2;
359 
360 }
361 #endif /* STM32F10X_XL */
362 
372 void FLASH_Lock(void)
373 {
374  /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */
375  FLASH->CR |= CR_LOCK_Set;
376 
377 #ifdef STM32F10X_XL
378  /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */
379  FLASH->CR2 |= CR_LOCK_Set;
380 #endif /* STM32F10X_XL */
381 }
382 
392 void FLASH_LockBank1(void)
393 {
394  /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */
395  FLASH->CR |= CR_LOCK_Set;
396 }
397 
398 #ifdef STM32F10X_XL
399 
405 void FLASH_LockBank2(void)
406 {
407  /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */
408  FLASH->CR2 |= CR_LOCK_Set;
409 }
410 #endif /* STM32F10X_XL */
411 
419 FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
420 {
422  /* Check the parameters */
423  assert_param(IS_FLASH_ADDRESS(Page_Address));
424 
425 #ifdef STM32F10X_XL
426  if(Page_Address < FLASH_BANK1_END_ADDRESS)
427  {
428  /* Wait for last operation to be completed */
430  if(status == FLASH_COMPLETE)
431  {
432  /* if the previous operation is completed, proceed to erase the page */
433  FLASH->CR|= CR_PER_Set;
434  FLASH->AR = Page_Address;
435  FLASH->CR|= CR_STRT_Set;
436 
437  /* Wait for last operation to be completed */
439 
440  /* Disable the PER Bit */
441  FLASH->CR &= CR_PER_Reset;
442  }
443  }
444  else
445  {
446  /* Wait for last operation to be completed */
447  status = FLASH_WaitForLastBank2Operation(EraseTimeout);
448  if(status == FLASH_COMPLETE)
449  {
450  /* if the previous operation is completed, proceed to erase the page */
451  FLASH->CR2|= CR_PER_Set;
452  FLASH->AR2 = Page_Address;
453  FLASH->CR2|= CR_STRT_Set;
454 
455  /* Wait for last operation to be completed */
456  status = FLASH_WaitForLastBank2Operation(EraseTimeout);
457 
458  /* Disable the PER Bit */
459  FLASH->CR2 &= CR_PER_Reset;
460  }
461  }
462 #else
463  /* Wait for last operation to be completed */
465 
466  if(status == FLASH_COMPLETE)
467  {
468  /* if the previous operation is completed, proceed to erase the page */
469  FLASH->CR|= CR_PER_Set;
470  FLASH->AR = Page_Address;
471  FLASH->CR|= CR_STRT_Set;
472 
473  /* Wait for last operation to be completed */
475 
476  /* Disable the PER Bit */
477  FLASH->CR &= CR_PER_Reset;
478  }
479 #endif /* STM32F10X_XL */
480 
481  /* Return the Erase Status */
482  return status;
483 }
484 
493 {
495 
496 #ifdef STM32F10X_XL
497  /* Wait for last operation to be completed */
499 
500  if(status == FLASH_COMPLETE)
501  {
502  /* if the previous operation is completed, proceed to erase all pages */
503  FLASH->CR |= CR_MER_Set;
504  FLASH->CR |= CR_STRT_Set;
505 
506  /* Wait for last operation to be completed */
508 
509  /* Disable the MER Bit */
510  FLASH->CR &= CR_MER_Reset;
511  }
512  if(status == FLASH_COMPLETE)
513  {
514  /* if the previous operation is completed, proceed to erase all pages */
515  FLASH->CR2 |= CR_MER_Set;
516  FLASH->CR2 |= CR_STRT_Set;
517 
518  /* Wait for last operation to be completed */
519  status = FLASH_WaitForLastBank2Operation(EraseTimeout);
520 
521  /* Disable the MER Bit */
522  FLASH->CR2 &= CR_MER_Reset;
523  }
524 #else
525  /* Wait for last operation to be completed */
527  if(status == FLASH_COMPLETE)
528  {
529  /* if the previous operation is completed, proceed to erase all pages */
530  FLASH->CR |= CR_MER_Set;
531  FLASH->CR |= CR_STRT_Set;
532 
533  /* Wait for last operation to be completed */
535 
536  /* Disable the MER Bit */
537  FLASH->CR &= CR_MER_Reset;
538  }
539 #endif /* STM32F10X_XL */
540 
541  /* Return the Erase Status */
542  return status;
543 }
544 
556 {
558  /* Wait for last operation to be completed */
560 
561  if(status == FLASH_COMPLETE)
562  {
563  /* if the previous operation is completed, proceed to erase all pages */
564  FLASH->CR |= CR_MER_Set;
565  FLASH->CR |= CR_STRT_Set;
566 
567  /* Wait for last operation to be completed */
569 
570  /* Disable the MER Bit */
571  FLASH->CR &= CR_MER_Reset;
572  }
573  /* Return the Erase Status */
574  return status;
575 }
576 
577 #ifdef STM32F10X_XL
578 
585 FLASH_Status FLASH_EraseAllBank2Pages(void)
586 {
588  /* Wait for last operation to be completed */
589  status = FLASH_WaitForLastBank2Operation(EraseTimeout);
590 
591  if(status == FLASH_COMPLETE)
592  {
593  /* if the previous operation is completed, proceed to erase all pages */
594  FLASH->CR2 |= CR_MER_Set;
595  FLASH->CR2 |= CR_STRT_Set;
596 
597  /* Wait for last operation to be completed */
598  status = FLASH_WaitForLastBank2Operation(EraseTimeout);
599 
600  /* Disable the MER Bit */
601  FLASH->CR2 &= CR_MER_Reset;
602  }
603  /* Return the Erase Status */
604  return status;
605 }
606 #endif /* STM32F10X_XL */
607 
617 {
618  uint16_t rdptmp = RDP_Key;
619 
621 
622  /* Get the actual read protection Option Byte value */
624  {
625  rdptmp = 0x00;
626  }
627 
628  /* Wait for last operation to be completed */
630  if(status == FLASH_COMPLETE)
631  {
632  /* Authorize the small information block programming */
633  FLASH->OPTKEYR = FLASH_KEY1;
634  FLASH->OPTKEYR = FLASH_KEY2;
635 
636  /* if the previous operation is completed, proceed to erase the option bytes */
637  FLASH->CR |= CR_OPTER_Set;
638  FLASH->CR |= CR_STRT_Set;
639  /* Wait for last operation to be completed */
641 
642  if(status == FLASH_COMPLETE)
643  {
644  /* if the erase operation is completed, disable the OPTER Bit */
645  FLASH->CR &= CR_OPTER_Reset;
646 
647  /* Enable the Option Bytes Programming operation */
648  FLASH->CR |= CR_OPTPG_Set;
649  /* Restore the last read protection Option Byte value */
650  OB->RDP = (uint16_t)rdptmp;
651  /* Wait for last operation to be completed */
653 
654  if(status != FLASH_TIMEOUT)
655  {
656  /* if the program operation is completed, disable the OPTPG Bit */
657  FLASH->CR &= CR_OPTPG_Reset;
658  }
659  }
660  else
661  {
662  if (status != FLASH_TIMEOUT)
663  {
664  /* Disable the OPTPG Bit */
665  FLASH->CR &= CR_OPTPG_Reset;
666  }
667  }
668  }
669  /* Return the erase status */
670  return status;
671 }
672 
681 FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
682 {
684  __IO uint32_t tmp = 0;
685 
686  /* Check the parameters */
687  assert_param(IS_FLASH_ADDRESS(Address));
688 
689 #ifdef STM32F10X_XL
690  if(Address < FLASH_BANK1_END_ADDRESS - 2)
691  {
692  /* Wait for last operation to be completed */
694  if(status == FLASH_COMPLETE)
695  {
696  /* if the previous operation is completed, proceed to program the new first
697  half word */
698  FLASH->CR |= CR_PG_Set;
699 
700  *(__IO uint16_t*)Address = (uint16_t)Data;
701  /* Wait for last operation to be completed */
703 
704  if(status == FLASH_COMPLETE)
705  {
706  /* if the previous operation is completed, proceed to program the new second
707  half word */
708  tmp = Address + 2;
709 
710  *(__IO uint16_t*) tmp = Data >> 16;
711 
712  /* Wait for last operation to be completed */
714 
715  /* Disable the PG Bit */
716  FLASH->CR &= CR_PG_Reset;
717  }
718  else
719  {
720  /* Disable the PG Bit */
721  FLASH->CR &= CR_PG_Reset;
722  }
723  }
724  }
725  else if(Address == (FLASH_BANK1_END_ADDRESS - 1))
726  {
727  /* Wait for last operation to be completed */
729 
730  if(status == FLASH_COMPLETE)
731  {
732  /* if the previous operation is completed, proceed to program the new first
733  half word */
734  FLASH->CR |= CR_PG_Set;
735 
736  *(__IO uint16_t*)Address = (uint16_t)Data;
737 
738  /* Wait for last operation to be completed */
740 
741  /* Disable the PG Bit */
742  FLASH->CR &= CR_PG_Reset;
743  }
744  else
745  {
746  /* Disable the PG Bit */
747  FLASH->CR &= CR_PG_Reset;
748  }
749 
750  /* Wait for last operation to be completed */
751  status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
752 
753  if(status == FLASH_COMPLETE)
754  {
755  /* if the previous operation is completed, proceed to program the new second
756  half word */
757  FLASH->CR2 |= CR_PG_Set;
758  tmp = Address + 2;
759 
760  *(__IO uint16_t*) tmp = Data >> 16;
761 
762  /* Wait for last operation to be completed */
763  status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
764 
765  /* Disable the PG Bit */
766  FLASH->CR2 &= CR_PG_Reset;
767  }
768  else
769  {
770  /* Disable the PG Bit */
771  FLASH->CR2 &= CR_PG_Reset;
772  }
773  }
774  else
775  {
776  /* Wait for last operation to be completed */
777  status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
778 
779  if(status == FLASH_COMPLETE)
780  {
781  /* if the previous operation is completed, proceed to program the new first
782  half word */
783  FLASH->CR2 |= CR_PG_Set;
784 
785  *(__IO uint16_t*)Address = (uint16_t)Data;
786  /* Wait for last operation to be completed */
787  status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
788 
789  if(status == FLASH_COMPLETE)
790  {
791  /* if the previous operation is completed, proceed to program the new second
792  half word */
793  tmp = Address + 2;
794 
795  *(__IO uint16_t*) tmp = Data >> 16;
796 
797  /* Wait for last operation to be completed */
798  status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
799 
800  /* Disable the PG Bit */
801  FLASH->CR2 &= CR_PG_Reset;
802  }
803  else
804  {
805  /* Disable the PG Bit */
806  FLASH->CR2 &= CR_PG_Reset;
807  }
808  }
809  }
810 #else
811  /* Wait for last operation to be completed */
813 
814  if(status == FLASH_COMPLETE)
815  {
816  /* if the previous operation is completed, proceed to program the new first
817  half word */
818  FLASH->CR |= CR_PG_Set;
819 
820  *(__IO uint16_t*)Address = (uint16_t)Data;
821  /* Wait for last operation to be completed */
823 
824  if(status == FLASH_COMPLETE)
825  {
826  /* if the previous operation is completed, proceed to program the new second
827  half word */
828  tmp = Address + 2;
829 
830  *(__IO uint16_t*) tmp = Data >> 16;
831 
832  /* Wait for last operation to be completed */
834 
835  /* Disable the PG Bit */
836  FLASH->CR &= CR_PG_Reset;
837  }
838  else
839  {
840  /* Disable the PG Bit */
841  FLASH->CR &= CR_PG_Reset;
842  }
843  }
844 #endif /* STM32F10X_XL */
845 
846  /* Return the Program Status */
847  return status;
848 }
849 
858 FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
859 {
861  /* Check the parameters */
862  assert_param(IS_FLASH_ADDRESS(Address));
863 
864 #ifdef STM32F10X_XL
865  /* Wait for last operation to be completed */
867 
868  if(Address < FLASH_BANK1_END_ADDRESS)
869  {
870  if(status == FLASH_COMPLETE)
871  {
872  /* if the previous operation is completed, proceed to program the new data */
873  FLASH->CR |= CR_PG_Set;
874 
875  *(__IO uint16_t*)Address = Data;
876  /* Wait for last operation to be completed */
878 
879  /* Disable the PG Bit */
880  FLASH->CR &= CR_PG_Reset;
881  }
882  }
883  else
884  {
885  if(status == FLASH_COMPLETE)
886  {
887  /* if the previous operation is completed, proceed to program the new data */
888  FLASH->CR2 |= CR_PG_Set;
889 
890  *(__IO uint16_t*)Address = Data;
891  /* Wait for last operation to be completed */
892  status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
893 
894  /* Disable the PG Bit */
895  FLASH->CR2 &= CR_PG_Reset;
896  }
897  }
898 #else
899  /* Wait for last operation to be completed */
901 
902  if(status == FLASH_COMPLETE)
903  {
904  /* if the previous operation is completed, proceed to program the new data */
905  FLASH->CR |= CR_PG_Set;
906 
907  *(__IO uint16_t*)Address = Data;
908  /* Wait for last operation to be completed */
910 
911  /* Disable the PG Bit */
912  FLASH->CR &= CR_PG_Reset;
913  }
914 #endif /* STM32F10X_XL */
915 
916  /* Return the Program Status */
917  return status;
918 }
919 
929 FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
930 {
932  /* Check the parameters */
935 
936  if(status == FLASH_COMPLETE)
937  {
938  /* Authorize the small information block programming */
939  FLASH->OPTKEYR = FLASH_KEY1;
940  FLASH->OPTKEYR = FLASH_KEY2;
941  /* Enables the Option Bytes Programming operation */
942  FLASH->CR |= CR_OPTPG_Set;
943  *(__IO uint16_t*)Address = Data;
944 
945  /* Wait for last operation to be completed */
947  if(status != FLASH_TIMEOUT)
948  {
949  /* if the program operation is completed, disable the OPTPG Bit */
950  FLASH->CR &= CR_OPTPG_Reset;
951  }
952  }
953  /* Return the Option Byte Data Program Status */
954  return status;
955 }
956 
976 {
977  uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
978 
980 
981  /* Check the parameters */
982  assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages));
983 
984  FLASH_Pages = (uint32_t)(~FLASH_Pages);
985  WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask);
986  WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8);
987  WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16);
988  WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24);
989 
990  /* Wait for last operation to be completed */
992 
993  if(status == FLASH_COMPLETE)
994  {
995  /* Authorizes the small information block programming */
996  FLASH->OPTKEYR = FLASH_KEY1;
997  FLASH->OPTKEYR = FLASH_KEY2;
998  FLASH->CR |= CR_OPTPG_Set;
999  if(WRP0_Data != 0xFF)
1000  {
1001  OB->WRP0 = WRP0_Data;
1002 
1003  /* Wait for last operation to be completed */
1005  }
1006  if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
1007  {
1008  OB->WRP1 = WRP1_Data;
1009 
1010  /* Wait for last operation to be completed */
1012  }
1013  if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
1014  {
1015  OB->WRP2 = WRP2_Data;
1016 
1017  /* Wait for last operation to be completed */
1019  }
1020 
1021  if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF))
1022  {
1023  OB->WRP3 = WRP3_Data;
1024 
1025  /* Wait for last operation to be completed */
1027  }
1028 
1029  if(status != FLASH_TIMEOUT)
1030  {
1031  /* if the program operation is completed, disable the OPTPG Bit */
1032  FLASH->CR &= CR_OPTPG_Reset;
1033  }
1034  }
1035  /* Return the write protection operation Status */
1036  return status;
1037 }
1038 
1050 {
1052  /* Check the parameters */
1053  assert_param(IS_FUNCTIONAL_STATE(NewState));
1055  if(status == FLASH_COMPLETE)
1056  {
1057  /* Authorizes the small information block programming */
1058  FLASH->OPTKEYR = FLASH_KEY1;
1059  FLASH->OPTKEYR = FLASH_KEY2;
1060  FLASH->CR |= CR_OPTER_Set;
1061  FLASH->CR |= CR_STRT_Set;
1062  /* Wait for last operation to be completed */
1064  if(status == FLASH_COMPLETE)
1065  {
1066  /* if the erase operation is completed, disable the OPTER Bit */
1067  FLASH->CR &= CR_OPTER_Reset;
1068  /* Enable the Option Bytes Programming operation */
1069  FLASH->CR |= CR_OPTPG_Set;
1070  if(NewState != DISABLE)
1071  {
1072  OB->RDP = 0x00;
1073  }
1074  else
1075  {
1076  OB->RDP = RDP_Key;
1077  }
1078  /* Wait for last operation to be completed */
1080 
1081  if(status != FLASH_TIMEOUT)
1082  {
1083  /* if the program operation is completed, disable the OPTPG Bit */
1084  FLASH->CR &= CR_OPTPG_Reset;
1085  }
1086  }
1087  else
1088  {
1089  if(status != FLASH_TIMEOUT)
1090  {
1091  /* Disable the OPTER Bit */
1092  FLASH->CR &= CR_OPTER_Reset;
1093  }
1094  }
1095  }
1096  /* Return the protection operation Status */
1097  return status;
1098 }
1099 
1118 FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
1119 {
1121 
1122  /* Check the parameters */
1123  assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
1124  assert_param(IS_OB_STOP_SOURCE(OB_STOP));
1125  assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
1126 
1127  /* Authorize the small information block programming */
1128  FLASH->OPTKEYR = FLASH_KEY1;
1129  FLASH->OPTKEYR = FLASH_KEY2;
1130 
1131  /* Wait for last operation to be completed */
1133 
1134  if(status == FLASH_COMPLETE)
1135  {
1136  /* Enable the Option Bytes Programming operation */
1137  FLASH->CR |= CR_OPTPG_Set;
1138 
1139  OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8)));
1140 
1141  /* Wait for last operation to be completed */
1143  if(status != FLASH_TIMEOUT)
1144  {
1145  /* if the program operation is completed, disable the OPTPG Bit */
1146  FLASH->CR &= CR_OPTPG_Reset;
1147  }
1148  }
1149  /* Return the Option Byte program Status */
1150  return status;
1151 }
1152 
1153 #ifdef STM32F10X_XL
1154 
1172 FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT)
1173 {
1175  assert_param(IS_FLASH_BOOT(FLASH_BOOT));
1176  /* Authorize the small information block programming */
1177  FLASH->OPTKEYR = FLASH_KEY1;
1178  FLASH->OPTKEYR = FLASH_KEY2;
1179 
1180  /* Wait for last operation to be completed */
1182 
1183  if(status == FLASH_COMPLETE)
1184  {
1185  /* Enable the Option Bytes Programming operation */
1186  FLASH->CR |= CR_OPTPG_Set;
1187 
1188  if(FLASH_BOOT == FLASH_BOOT_Bank1)
1189  {
1190  OB->USER |= OB_USER_BFB2;
1191  }
1192  else
1193  {
1194  OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2));
1195  }
1196  /* Wait for last operation to be completed */
1198  if(status != FLASH_TIMEOUT)
1199  {
1200  /* if the program operation is completed, disable the OPTPG Bit */
1201  FLASH->CR &= CR_OPTPG_Reset;
1202  }
1203  }
1204  /* Return the Option Byte program Status */
1205  return status;
1206 }
1207 #endif /* STM32F10X_XL */
1208 
1217 {
1218  /* Return the User Option Byte */
1219  return (uint32_t)(FLASH->OBR >> 2);
1220 }
1221 
1229 {
1230  /* Return the Flash write protection Register value */
1231  return (uint32_t)(FLASH->WRPR);
1232 }
1233 
1241 {
1242  FlagStatus readoutstatus = RESET;
1243  if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)
1244  {
1245  readoutstatus = SET;
1246  }
1247  else
1248  {
1249  readoutstatus = RESET;
1250  }
1251  return readoutstatus;
1252 }
1253 
1261 {
1262  FlagStatus bitstatus = RESET;
1263 
1264  if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET)
1265  {
1266  bitstatus = SET;
1267  }
1268  else
1269  {
1270  bitstatus = RESET;
1271  }
1272  /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
1273  return bitstatus;
1274 }
1275 
1290 void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
1291 {
1292 #ifdef STM32F10X_XL
1293  /* Check the parameters */
1294  assert_param(IS_FLASH_IT(FLASH_IT));
1295  assert_param(IS_FUNCTIONAL_STATE(NewState));
1296 
1297  if((FLASH_IT & 0x80000000) != 0x0)
1298  {
1299  if(NewState != DISABLE)
1300  {
1301  /* Enable the interrupt sources */
1302  FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF);
1303  }
1304  else
1305  {
1306  /* Disable the interrupt sources */
1307  FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF);
1308  }
1309  }
1310  else
1311  {
1312  if(NewState != DISABLE)
1313  {
1314  /* Enable the interrupt sources */
1315  FLASH->CR |= FLASH_IT;
1316  }
1317  else
1318  {
1319  /* Disable the interrupt sources */
1320  FLASH->CR &= ~(uint32_t)FLASH_IT;
1321  }
1322  }
1323 #else
1324  /* Check the parameters */
1325  assert_param(IS_FLASH_IT(FLASH_IT));
1326  assert_param(IS_FUNCTIONAL_STATE(NewState));
1327 
1328  if(NewState != DISABLE)
1329  {
1330  /* Enable the interrupt sources */
1331  FLASH->CR |= FLASH_IT;
1332  }
1333  else
1334  {
1335  /* Disable the interrupt sources */
1336  FLASH->CR &= ~(uint32_t)FLASH_IT;
1337  }
1338 #endif /* STM32F10X_XL */
1339 }
1340 
1357 FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
1358 {
1359  FlagStatus bitstatus = RESET;
1360 
1361 #ifdef STM32F10X_XL
1362  /* Check the parameters */
1363  assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
1364  if(FLASH_FLAG == FLASH_FLAG_OPTERR)
1365  {
1366  if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
1367  {
1368  bitstatus = SET;
1369  }
1370  else
1371  {
1372  bitstatus = RESET;
1373  }
1374  }
1375  else
1376  {
1377  if((FLASH_FLAG & 0x80000000) != 0x0)
1378  {
1379  if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET)
1380  {
1381  bitstatus = SET;
1382  }
1383  else
1384  {
1385  bitstatus = RESET;
1386  }
1387  }
1388  else
1389  {
1390  if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
1391  {
1392  bitstatus = SET;
1393  }
1394  else
1395  {
1396  bitstatus = RESET;
1397  }
1398  }
1399  }
1400 #else
1401  /* Check the parameters */
1402  assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
1403  if(FLASH_FLAG == FLASH_FLAG_OPTERR)
1404  {
1405  if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
1406  {
1407  bitstatus = SET;
1408  }
1409  else
1410  {
1411  bitstatus = RESET;
1412  }
1413  }
1414  else
1415  {
1416  if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
1417  {
1418  bitstatus = SET;
1419  }
1420  else
1421  {
1422  bitstatus = RESET;
1423  }
1424  }
1425 #endif /* STM32F10X_XL */
1426 
1427  /* Return the new state of FLASH_FLAG (SET or RESET) */
1428  return bitstatus;
1429 }
1430 
1443 void FLASH_ClearFlag(uint32_t FLASH_FLAG)
1444 {
1445 #ifdef STM32F10X_XL
1446  /* Check the parameters */
1447  assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
1448 
1449  if((FLASH_FLAG & 0x80000000) != 0x0)
1450  {
1451  /* Clear the flags */
1452  FLASH->SR2 = FLASH_FLAG;
1453  }
1454  else
1455  {
1456  /* Clear the flags */
1457  FLASH->SR = FLASH_FLAG;
1458  }
1459 
1460 #else
1461  /* Check the parameters */
1462  assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
1463 
1464  /* Clear the flags */
1465  FLASH->SR = FLASH_FLAG;
1466 #endif /* STM32F10X_XL */
1467 }
1468 
1478 {
1479  FLASH_Status flashstatus = FLASH_COMPLETE;
1480 
1481  if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
1482  {
1483  flashstatus = FLASH_BUSY;
1484  }
1485  else
1486  {
1487  if((FLASH->SR & FLASH_FLAG_PGERR) != 0)
1488  {
1489  flashstatus = FLASH_ERROR_PG;
1490  }
1491  else
1492  {
1493  if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 )
1494  {
1495  flashstatus = FLASH_ERROR_WRP;
1496  }
1497  else
1498  {
1499  flashstatus = FLASH_COMPLETE;
1500  }
1501  }
1502  }
1503  /* Return the Flash Status */
1504  return flashstatus;
1505 }
1506 
1516 {
1517  FLASH_Status flashstatus = FLASH_COMPLETE;
1518 
1519  if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY)
1520  {
1521  flashstatus = FLASH_BUSY;
1522  }
1523  else
1524  {
1525  if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0)
1526  {
1527  flashstatus = FLASH_ERROR_PG;
1528  }
1529  else
1530  {
1531  if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 )
1532  {
1533  flashstatus = FLASH_ERROR_WRP;
1534  }
1535  else
1536  {
1537  flashstatus = FLASH_COMPLETE;
1538  }
1539  }
1540  }
1541  /* Return the Flash Status */
1542  return flashstatus;
1543 }
1544 
1545 #ifdef STM32F10X_XL
1546 
1553 FLASH_Status FLASH_GetBank2Status(void)
1554 {
1555  FLASH_Status flashstatus = FLASH_COMPLETE;
1556 
1557  if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF))
1558  {
1559  flashstatus = FLASH_BUSY;
1560  }
1561  else
1562  {
1563  if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0)
1564  {
1565  flashstatus = FLASH_ERROR_PG;
1566  }
1567  else
1568  {
1569  if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 )
1570  {
1571  flashstatus = FLASH_ERROR_WRP;
1572  }
1573  else
1574  {
1575  flashstatus = FLASH_COMPLETE;
1576  }
1577  }
1578  }
1579  /* Return the Flash Status */
1580  return flashstatus;
1581 }
1582 #endif /* STM32F10X_XL */
1583 
1596 {
1598 
1599  /* Check for the Flash Status */
1600  status = FLASH_GetBank1Status();
1601  /* Wait for a Flash operation to complete or a TIMEOUT to occur */
1602  while((status == FLASH_BUSY) && (Timeout != 0x00))
1603  {
1604  status = FLASH_GetBank1Status();
1605  Timeout--;
1606  }
1607  if(Timeout == 0x00 )
1608  {
1609  status = FLASH_TIMEOUT;
1610  }
1611  /* Return the operation status */
1612  return status;
1613 }
1614 
1624 {
1626 
1627  /* Check for the Flash Status */
1628  status = FLASH_GetBank1Status();
1629  /* Wait for a Flash operation to complete or a TIMEOUT to occur */
1630  while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00))
1631  {
1632  status = FLASH_GetBank1Status();
1633  Timeout--;
1634  }
1635  if(Timeout == 0x00 )
1636  {
1637  status = FLASH_TIMEOUT;
1638  }
1639  /* Return the operation status */
1640  return status;
1641 }
1642 
1643 #ifdef STM32F10X_XL
1644 
1651 FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout)
1652 {
1654 
1655  /* Check for the Flash Status */
1656  status = FLASH_GetBank2Status();
1657  /* Wait for a Flash operation to complete or a TIMEOUT to occur */
1658  while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00))
1659  {
1660  status = FLASH_GetBank2Status();
1661  Timeout--;
1662  }
1663  if(Timeout == 0x00 )
1664  {
1665  status = FLASH_TIMEOUT;
1666  }
1667  /* Return the operation status */
1668  return status;
1669 }
1670 #endif /* STM32F10X_XL */
1671 
1684 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
FlagStatus
Definition: stm32f4xx.h:706
#define IS_OB_IWDG_SOURCE(SOURCE)
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
Programs a half word at a specified address.
FlagStatus FLASH_GetReadOutProtectionStatus(void)
Checks whether the FLASH Read Out Protection Status is set or not.
#define IS_OB_STOP_SOURCE(SOURCE)
FunctionalState
Definition: stm32f4xx.h:708
#define CR_OPTER_Reset
#define CR_PER_Set
#define FLASH_FLAG_OPTERR
#define CR_MER_Set
#define IS_FLASH_GET_FLAG(FLAG)
#define EraseTimeout
#define IS_FLASH_CLEAR_FLAG(FLAG)
#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE)
FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout)
Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.
#define ACR_PRFTBE_Mask
void assert_param(int val)
void FLASH_Unlock(void)
Unlocks the FLASH Program Erase Controller.
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
Enables or disables the specified FLASH interrupts.
FLASH_Status FLASH_EraseOptionBytes(void)
Erases the FLASH option bytes.
FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
Erases a specified FLASH page.
#define CR_OPTER_Set
#define WRP3_Mask
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
#define FLASH_FLAG_WRPRTERR
#define FLASH
Definition: stm32f4xx.h:2123
#define ACR_LATENCY_Mask
static volatile uint8_t * status
Definition: drv_i2c.c:102
void FLASH_UnlockBank1(void)
Unlocks the FLASH Bank1 Program Erase Controller.
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
Waits for a Flash operation to complete or a TIMEOUT to occur.
Definition: stm32f4xx.h:706
#define ACR_HLFCYA_Mask
#define ProgramTimeout
#define RDPRT_Mask
#define IS_FLASH_WRPROT_PAGE(PAGE)
FLASH_Status FLASH_EraseAllPages(void)
Erases all FLASH pages.
#define CR_LOCK_Set
#define __IO
Definition: core_cm0.h:198
#define WRP1_Mask
void FLASH_LockBank1(void)
Locks the FLASH Bank1 Program Erase Controller.
#define FLASH_FLAG_BSY
void FLASH_SetLatency(uint32_t FLASH_Latency)
Sets the code latency value.
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
Checks whether the specified FLASH flag is set or not.
#define IS_OB_DATA_ADDRESS(ADDRESS)
#define IS_FLASH_PREFETCHBUFFER_STATE(STATE)
#define CR_OPTPG_Reset
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
Enables or disables the read out protection.
#define CR_PER_Reset
#define ACR_PRFTBS_Mask
#define CR_STRT_Set
#define WRP0_Mask
FLASH_Status FLASH_GetBank1Status(void)
Returns the FLASH Bank1 Status.
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)
Write protects the desired pages.
#define CR_PG_Set
uint32_t FLASH_GetUserOptionByte(void)
Returns the FLASH User Option Bytes values.
#define CR_PG_Reset
#define IS_FLASH_IT(IT)
#define OB
Definition: stm32f10x.h:1446
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
This file contains all the functions prototypes for the FLASH firmware library.
FLASH_Status FLASH_EraseAllBank1Pages(void)
Erases all Bank1 FLASH pages.
void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)
Enables or disables the Half cycle flash access.
#define IS_FLASH_LATENCY(LATENCY)
#define IS_FLASH_ADDRESS(ADDRESS)
#define FLASH_FLAG_BANK1_WRPRTERR
#define CR_OPTPG_Set
#define RDP_Key
#define IS_OB_STDBY_SOURCE(SOURCE)
#define FLASH_FLAG_PGERR
#define FLASH_KEY1
#define OB_USER_BFB2
#define FLASH_KEY2
void FLASH_Lock(void)
Locks the FLASH Program Erase Controller.
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
Programs a half word at a specified Option Byte Data address.
#define CR_MER_Reset
#define WRP2_Mask
#define FLASH_FLAG_BANK1_BSY
FLASH_Status FLASH_GetStatus(void)
Returns the FLASH Status.
FLASH_Status
FLASH Status.
FlagStatus FLASH_GetPrefetchBufferStatus(void)
Checks whether the FLASH Prefetch Buffer status is set or not.
void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)
Enables or disables the Prefetch Buffer.
uint32_t FLASH_GetWriteProtectionOptionByte(void)
Returns the FLASH Write Protection Option Bytes Register value.
#define FLASH_FLAG_BANK1_PGERR
#define FLASH_BANK1_END_ADDRESS
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
Programs a word at a specified address.
void FLASH_ClearFlag(uint32_t FLASH_FLAG)
Clears the FLASH&#39;s pending flags.


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19