stm32f10x_dac.c
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1 
22 /* Includes ------------------------------------------------------------------*/
23 #include "stm32f10x_dac.h"
24 #include "stm32f10x_rcc.h"
25 
47 /* CR register Mask */
48 #define CR_CLEAR_MASK ((uint32_t)0x00000FFE)
49 
50 /* DAC Dual Channels SWTRIG masks */
51 #define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
52 #define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
53 
54 /* DHR registers offsets */
55 #define DHR12R1_OFFSET ((uint32_t)0x00000008)
56 #define DHR12R2_OFFSET ((uint32_t)0x00000014)
57 #define DHR12RD_OFFSET ((uint32_t)0x00000020)
58 
59 /* DOR register offset */
60 #define DOR_OFFSET ((uint32_t)0x0000002C)
61 
98 void DAC_DeInit(void)
99 {
100  /* Enable DAC reset state */
102  /* Release DAC from reset state */
104 }
105 
117 void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
118 {
119  uint32_t tmpreg1 = 0, tmpreg2 = 0;
120  /* Check the DAC parameters */
121  assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
125 /*---------------------------- DAC CR Configuration --------------------------*/
126  /* Get the DAC CR value */
127  tmpreg1 = DAC->CR;
128  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
129  tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
130  /* Configure for the selected DAC channel: buffer output, trigger, wave generation,
131  mask/amplitude for wave generation */
132  /* Set TSELx and TENx bits according to DAC_Trigger value */
133  /* Set WAVEx bits according to DAC_WaveGeneration value */
134  /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
135  /* Set BOFFx bit according to DAC_OutputBuffer value */
136  tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
137  DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
138  /* Calculate CR register value depending on DAC_Channel */
139  tmpreg1 |= tmpreg2 << DAC_Channel;
140  /* Write to DAC CR */
141  DAC->CR = tmpreg1;
142 }
143 
150 void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
151 {
152 /*--------------- Reset DAC init structure parameters values -----------------*/
153  /* Initialize the DAC_Trigger member */
154  DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
155  /* Initialize the DAC_WaveGeneration member */
157  /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
159  /* Initialize the DAC_OutputBuffer member */
160  DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
161 }
162 
173 void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
174 {
175  /* Check the parameters */
176  assert_param(IS_DAC_CHANNEL(DAC_Channel));
178  if (NewState != DISABLE)
179  {
180  /* Enable the selected DAC channel */
181  DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
182  }
183  else
184  {
185  /* Disable the selected DAC channel */
186  DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel);
187  }
188 }
189 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
190 
203 void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
204 {
205  /* Check the parameters */
206  assert_param(IS_DAC_CHANNEL(DAC_Channel));
208  assert_param(IS_DAC_IT(DAC_IT));
209 
210  if (NewState != DISABLE)
211  {
212  /* Enable the selected DAC interrupts */
213  DAC->CR |= (DAC_IT << DAC_Channel);
214  }
215  else
216  {
217  /* Disable the selected DAC interrupts */
218  DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
219  }
220 }
221 #endif
222 
233 void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
234 {
235  /* Check the parameters */
236  assert_param(IS_DAC_CHANNEL(DAC_Channel));
238  if (NewState != DISABLE)
239  {
240  /* Enable the selected DAC channel DMA request */
241  DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
242  }
243  else
244  {
245  /* Disable the selected DAC channel DMA request */
246  DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel);
247  }
248 }
249 
260 void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
261 {
262  /* Check the parameters */
263  assert_param(IS_DAC_CHANNEL(DAC_Channel));
265  if (NewState != DISABLE)
266  {
267  /* Enable software trigger for the selected DAC channel */
268  DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
269  }
270  else
271  {
272  /* Disable software trigger for the selected DAC channel */
273  DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
274  }
275 }
276 
285 {
286  /* Check the parameters */
288  if (NewState != DISABLE)
289  {
290  /* Enable software trigger for both DAC channels */
291  DAC->SWTRIGR |= DUAL_SWTRIG_SET ;
292  }
293  else
294  {
295  /* Disable software trigger for both DAC channels */
296  DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
297  }
298 }
299 
314 void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
315 {
316  /* Check the parameters */
317  assert_param(IS_DAC_CHANNEL(DAC_Channel));
318  assert_param(IS_DAC_WAVE(DAC_Wave));
320  if (NewState != DISABLE)
321  {
322  /* Enable the selected wave generation for the selected DAC channel */
323  DAC->CR |= DAC_Wave << DAC_Channel;
324  }
325  else
326  {
327  /* Disable the selected wave generation for the selected DAC channel */
328  DAC->CR &= ~(DAC_Wave << DAC_Channel);
329  }
330 }
331 
342 void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
343 {
344  __IO uint32_t tmp = 0;
345 
346  /* Check the parameters */
347  assert_param(IS_DAC_ALIGN(DAC_Align));
348  assert_param(IS_DAC_DATA(Data));
349 
350  tmp = (uint32_t)DAC_BASE;
351  tmp += DHR12R1_OFFSET + DAC_Align;
352 
353  /* Set the DAC channel1 selected data holding register */
354  *(__IO uint32_t *) tmp = Data;
355 }
356 
367 void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
368 {
369  __IO uint32_t tmp = 0;
370 
371  /* Check the parameters */
372  assert_param(IS_DAC_ALIGN(DAC_Align));
373  assert_param(IS_DAC_DATA(Data));
374 
375  tmp = (uint32_t)DAC_BASE;
376  tmp += DHR12R2_OFFSET + DAC_Align;
377 
378  /* Set the DAC channel2 selected data holding register */
379  *(__IO uint32_t *)tmp = Data;
380 }
381 
396 void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
397 {
398  uint32_t data = 0, tmp = 0;
399 
400  /* Check the parameters */
401  assert_param(IS_DAC_ALIGN(DAC_Align));
402  assert_param(IS_DAC_DATA(Data1));
403  assert_param(IS_DAC_DATA(Data2));
404 
405  /* Calculate and set dual DAC data holding register value */
406  if (DAC_Align == DAC_Align_8b_R)
407  {
408  data = ((uint32_t)Data2 << 8) | Data1;
409  }
410  else
411  {
412  data = ((uint32_t)Data2 << 16) | Data1;
413  }
414 
415  tmp = (uint32_t)DAC_BASE;
416  tmp += DHR12RD_OFFSET + DAC_Align;
417 
418  /* Set the dual DAC selected data holding register */
419  *(__IO uint32_t *)tmp = data;
420 }
421 
430 uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
431 {
432  __IO uint32_t tmp = 0;
433 
434  /* Check the parameters */
435  assert_param(IS_DAC_CHANNEL(DAC_Channel));
436 
437  tmp = (uint32_t) DAC_BASE ;
438  tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
439 
440  /* Returns the DAC channel data output register value */
441  return (uint16_t) (*(__IO uint32_t*) tmp);
442 }
443 
444 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
445 
456 FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
457 {
458  FlagStatus bitstatus = RESET;
459  /* Check the parameters */
460  assert_param(IS_DAC_CHANNEL(DAC_Channel));
461  assert_param(IS_DAC_FLAG(DAC_FLAG));
462 
463  /* Check the status of the specified DAC flag */
464  if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
465  {
466  /* DAC_FLAG is set */
467  bitstatus = SET;
468  }
469  else
470  {
471  /* DAC_FLAG is reset */
472  bitstatus = RESET;
473  }
474  /* Return the DAC_FLAG status */
475  return bitstatus;
476 }
477 
489 void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
490 {
491  /* Check the parameters */
492  assert_param(IS_DAC_CHANNEL(DAC_Channel));
493  assert_param(IS_DAC_FLAG(DAC_FLAG));
494 
495  /* Clear the selected DAC flags */
496  DAC->SR = (DAC_FLAG << DAC_Channel);
497 }
498 
510 ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
511 {
512  ITStatus bitstatus = RESET;
513  uint32_t enablestatus = 0;
514 
515  /* Check the parameters */
516  assert_param(IS_DAC_CHANNEL(DAC_Channel));
517  assert_param(IS_DAC_IT(DAC_IT));
518 
519  /* Get the DAC_IT enable bit status */
520  enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
521 
522  /* Check the status of the specified DAC interrupt */
523  if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
524  {
525  /* DAC_IT is set */
526  bitstatus = SET;
527  }
528  else
529  {
530  /* DAC_IT is reset */
531  bitstatus = RESET;
532  }
533  /* Return the DAC_IT status */
534  return bitstatus;
535 }
536 
548 void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
549 {
550  /* Check the parameters */
551  assert_param(IS_DAC_CHANNEL(DAC_Channel));
552  assert_param(IS_DAC_IT(DAC_IT));
553 
554  /* Clear the selected DAC interrupt pending bits */
555  DAC->SR = (DAC_IT << DAC_Channel);
556 }
557 #endif
558 
571 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
Set the specified data holding register value for dual channel DAC.
FlagStatus
Definition: stm32f4xx.h:706
void DAC_DeInit(void)
Deinitializes the DAC peripheral registers to their default reset values.
Definition: stm32f10x_dac.c:98
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
Enables or disables the specified DAC interrupts.
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
Checks whether the specified DAC flag is set or not.
#define DAC_BASE
Definition: stm32f4xx.h:1920
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
Enables or disables the selected DAC channel wave generation.
uint32_t DAC_OutputBuffer
Definition: stm32f4xx_dac.h:67
FunctionalState
Definition: stm32f4xx.h:708
#define DAC_Align_8b_R
#define DHR12RD_OFFSET
Definition: stm32f10x_dac.c:57
#define DAC_OutputBuffer_Enable
#define DHR12R2_OFFSET
Definition: stm32f10x_dac.c:56
#define DAC_Trigger_None
Definition: stm32f4xx_dac.h:81
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
Enables or disables simultaneously the two DAC channels software triggers.
#define DAC_SWTRIGR_SWTRIG1
Definition: stm32f4xx.h:3972
#define IS_DAC_FLAG(FLAG)
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE)
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the specified DAC channel.
#define DHR12R1_OFFSET
Definition: stm32f10x_dac.c:55
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
Clears the DAC channel&#39;s pending flags.
#define DOR_OFFSET
Definition: stm32f10x_dac.c:60
void assert_param(int val)
#define IS_DAC_WAVE(WAVE)
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)
#define IS_FUNCTIONAL_STATE(STATE)
Definition: stm32f4xx.h:709
#define DAC_CR_EN1
Definition: stm32f4xx.h:3930
#define DAC_CR_DMAEN1
Definition: stm32f4xx.h:3949
This file contains all the functions prototypes for the DAC firmware library.
Definition: stm32f4xx.h:706
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct)
Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.
enum FlagStatus ITStatus
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
#define __IO
Definition: core_cm0.h:198
#define DUAL_SWTRIG_SET
Definition: stm32f10x_dac.c:51
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the selected DAC channel software trigger.
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
Set the specified data holding register value for DAC channel1.
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
Checks whether the specified DAC interrupt has occurred or not.
#define DAC_LFSRUnmask_Bit0
This file contains all the functions prototypes for the RCC firmware library.
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
Set the specified data holding register value for DAC channel2.
uint32_t DAC_LFSRUnmask_TriangleAmplitude
Definition: stm32f4xx_dac.h:63
#define IS_DAC_IT(IT)
#define DUAL_SWTRIG_RESET
Definition: stm32f10x_dac.c:52
uint32_t DAC_Trigger
Definition: stm32f4xx_dac.h:56
#define CR_CLEAR_MASK
Definition: stm32f10x_dac.c:48
#define IS_DAC_ALIGN(ALIGN)
#define IS_DAC_GENERATE_WAVE(WAVE)
void DAC_StructInit(DAC_InitTypeDef *DAC_InitStruct)
Fills each DAC_InitStruct member with its default value.
#define IS_DAC_DATA(DATA)
DAC Init structure definition.
Definition: stm32f4xx_dac.h:54
#define IS_DAC_CHANNEL(CHANNEL)
uint32_t DAC_WaveGeneration
Definition: stm32f4xx_dac.h:59
#define DAC
Definition: stm32f4xx.h:2075
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
Clears the DAC channel&#39;s interrupt pending bits.
#define IS_DAC_TRIGGER(TRIGGER)
Definition: stm32f4xx_dac.h:94
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
Returns the last data output value of the selected DAC channel.
#define DAC_WaveGeneration_None
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the specified DAC channel DMA request.


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:19