core_sc000.h
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1 /**************************************************************************/
10 /* Copyright (c) 2009 - 2014 ARM LIMITED
11 
12  All rights reserved.
13  Redistribution and use in source and binary forms, with or without
14  modification, are permitted provided that the following conditions are met:
15  - Redistributions of source code must retain the above copyright
16  notice, this list of conditions and the following disclaimer.
17  - Redistributions in binary form must reproduce the above copyright
18  notice, this list of conditions and the following disclaimer in the
19  documentation and/or other materials provided with the distribution.
20  - Neither the name of ARM nor the names of its contributors may be used
21  to endorse or promote products derived from this software without
22  specific prior written permission.
23  *
24  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34  POSSIBILITY OF SUCH DAMAGE.
35  ---------------------------------------------------------------------------*/
36 
37 
38 #if defined ( __ICCARM__ )
39  #pragma system_include /* treat file as system include file for MISRA check */
40 #endif
41 
42 #ifndef __CORE_SC000_H_GENERIC
43 #define __CORE_SC000_H_GENERIC
44 
45 #ifdef __cplusplus
46  extern "C" {
47 #endif
48 
63 /*******************************************************************************
64  * CMSIS definitions
65  ******************************************************************************/
70 /* CMSIS SC000 definitions */
71 #define __SC000_CMSIS_VERSION_MAIN (0x04)
72 #define __SC000_CMSIS_VERSION_SUB (0x00)
73 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
74  __SC000_CMSIS_VERSION_SUB )
76 #define __CORTEX_SC (000)
79 #if defined ( __CC_ARM )
80  #define __ASM __asm
81  #define __INLINE __inline
82  #define __STATIC_INLINE static __inline
83 
84 #elif defined ( __GNUC__ )
85  #define __ASM __asm
86  #define __INLINE inline
87  #define __STATIC_INLINE static inline
88 
89 #elif defined ( __ICCARM__ )
90  #define __ASM __asm
91  #define __INLINE inline
92  #define __STATIC_INLINE static inline
93 
94 #elif defined ( __TMS470__ )
95  #define __ASM __asm
96  #define __STATIC_INLINE static inline
97 
98 #elif defined ( __TASKING__ )
99  #define __ASM __asm
100  #define __INLINE inline
101  #define __STATIC_INLINE static inline
102 
103 #elif defined ( __CSMC__ )
104  #define __packed
105  #define __ASM _asm
106  #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
107  #define __STATIC_INLINE static inline
108 
109 #endif
110 
114 #define __FPU_USED 0
115 
116 #if defined ( __CC_ARM )
117  #if defined __TARGET_FPU_VFP
118  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
119  #endif
120 
121 #elif defined ( __GNUC__ )
122  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
123  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
124  #endif
125 
126 #elif defined ( __ICCARM__ )
127  #if defined __ARMVFP__
128  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129  #endif
130 
131 #elif defined ( __TMS470__ )
132  #if defined __TI__VFP_SUPPORT____
133  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
134  #endif
135 
136 #elif defined ( __TASKING__ )
137  #if defined __FPU_VFP__
138  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
139  #endif
140 
141 #elif defined ( __CSMC__ ) /* Cosmic */
142  #if ( __CSMC__ & 0x400) // FPU present for parser
143  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144  #endif
145 #endif
146 
147 #include <stdint.h> /* standard types definitions */
148 #include <core_cmInstr.h> /* Core Instruction Access */
149 #include <core_cmFunc.h> /* Core Function Access */
150 
151 #ifdef __cplusplus
152 }
153 #endif
154 
155 #endif /* __CORE_SC000_H_GENERIC */
156 
157 #ifndef __CMSIS_GENERIC
158 
159 #ifndef __CORE_SC000_H_DEPENDANT
160 #define __CORE_SC000_H_DEPENDANT
161 
162 #ifdef __cplusplus
163  extern "C" {
164 #endif
165 
166 /* check device defines and use defaults */
167 #if defined __CHECK_DEVICE_DEFINES
168  #ifndef __SC000_REV
169  #define __SC000_REV 0x0000
170  #warning "__SC000_REV not defined in device header file; using default!"
171  #endif
172 
173  #ifndef __MPU_PRESENT
174  #define __MPU_PRESENT 0
175  #warning "__MPU_PRESENT not defined in device header file; using default!"
176  #endif
177 
178  #ifndef __NVIC_PRIO_BITS
179  #define __NVIC_PRIO_BITS 2
180  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
181  #endif
182 
183  #ifndef __Vendor_SysTickConfig
184  #define __Vendor_SysTickConfig 0
185  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
186  #endif
187 #endif
188 
189 /* IO definitions (access restrictions to peripheral registers) */
197 #ifdef __cplusplus
198  #define __I volatile
199 #else
200  #define __I volatile const
201 #endif
202 #define __O volatile
203 #define __IO volatile
205 
209 /*******************************************************************************
210  * Register Abstraction
211  Core Register contain:
212  - Core Register
213  - Core NVIC Register
214  - Core SCB Register
215  - Core SysTick Register
216  - Core MPU Register
217  ******************************************************************************/
218 
230 typedef union
231 {
232  struct
233  {
234 #if (__CORTEX_M != 0x04)
235  uint32_t _reserved0:27;
236 #else
237  uint32_t _reserved0:16;
238  uint32_t GE:4;
239  uint32_t _reserved1:7;
240 #endif
241  uint32_t Q:1;
242  uint32_t V:1;
243  uint32_t C:1;
244  uint32_t Z:1;
245  uint32_t N:1;
246  } b;
247  uint32_t w;
248 } APSR_Type;
249 
250 
253 typedef union
254 {
255  struct
256  {
257  uint32_t ISR:9;
258  uint32_t _reserved0:23;
259  } b;
260  uint32_t w;
261 } IPSR_Type;
262 
263 
266 typedef union
267 {
268  struct
269  {
270  uint32_t ISR:9;
271 #if (__CORTEX_M != 0x04)
272  uint32_t _reserved0:15;
273 #else
274  uint32_t _reserved0:7;
275  uint32_t GE:4;
276  uint32_t _reserved1:4;
277 #endif
278  uint32_t T:1;
279  uint32_t IT:2;
280  uint32_t Q:1;
281  uint32_t V:1;
282  uint32_t C:1;
283  uint32_t Z:1;
284  uint32_t N:1;
285  } b;
286  uint32_t w;
287 } xPSR_Type;
288 
289 
292 typedef union
293 {
294  struct
295  {
296  uint32_t nPRIV:1;
297  uint32_t SPSEL:1;
298  uint32_t FPCA:1;
299  uint32_t _reserved0:29;
300  } b;
301  uint32_t w;
302 } CONTROL_Type;
303 
315 typedef struct
316 {
317  __IO uint32_t ISER[1];
318  uint32_t RESERVED0[31];
319  __IO uint32_t ICER[1];
320  uint32_t RSERVED1[31];
321  __IO uint32_t ISPR[1];
322  uint32_t RESERVED2[31];
323  __IO uint32_t ICPR[1];
324  uint32_t RESERVED3[31];
325  uint32_t RESERVED4[64];
326  __IO uint32_t IP[8];
327 } NVIC_Type;
328 
340 typedef struct
341 {
342  __I uint32_t CPUID;
343  __IO uint32_t ICSR;
344  __IO uint32_t VTOR;
345  __IO uint32_t AIRCR;
346  __IO uint32_t SCR;
347  __IO uint32_t CCR;
348  uint32_t RESERVED0[1];
349  __IO uint32_t SHP[2];
350  __IO uint32_t SHCSR;
351  uint32_t RESERVED1[154];
352  __IO uint32_t SFCR;
353 } SCB_Type;
354 
355 /* SCB CPUID Register Definitions */
356 #define SCB_CPUID_IMPLEMENTER_Pos 24
357 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
359 #define SCB_CPUID_VARIANT_Pos 20
360 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
362 #define SCB_CPUID_ARCHITECTURE_Pos 16
363 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
365 #define SCB_CPUID_PARTNO_Pos 4
366 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
368 #define SCB_CPUID_REVISION_Pos 0
369 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)
371 /* SCB Interrupt Control State Register Definitions */
372 #define SCB_ICSR_NMIPENDSET_Pos 31
373 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
375 #define SCB_ICSR_PENDSVSET_Pos 28
376 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
378 #define SCB_ICSR_PENDSVCLR_Pos 27
379 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
381 #define SCB_ICSR_PENDSTSET_Pos 26
382 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
384 #define SCB_ICSR_PENDSTCLR_Pos 25
385 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
387 #define SCB_ICSR_ISRPREEMPT_Pos 23
388 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
390 #define SCB_ICSR_ISRPENDING_Pos 22
391 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
393 #define SCB_ICSR_VECTPENDING_Pos 12
394 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
396 #define SCB_ICSR_VECTACTIVE_Pos 0
397 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
399 /* SCB Interrupt Control State Register Definitions */
400 #define SCB_VTOR_TBLOFF_Pos 7
401 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
403 /* SCB Application Interrupt and Reset Control Register Definitions */
404 #define SCB_AIRCR_VECTKEY_Pos 16
405 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
407 #define SCB_AIRCR_VECTKEYSTAT_Pos 16
408 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
410 #define SCB_AIRCR_ENDIANESS_Pos 15
411 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
413 #define SCB_AIRCR_SYSRESETREQ_Pos 2
414 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
416 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1
417 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
419 /* SCB System Control Register Definitions */
420 #define SCB_SCR_SEVONPEND_Pos 4
421 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
423 #define SCB_SCR_SLEEPDEEP_Pos 2
424 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
426 #define SCB_SCR_SLEEPONEXIT_Pos 1
427 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
429 /* SCB Configuration Control Register Definitions */
430 #define SCB_CCR_STKALIGN_Pos 9
431 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
433 #define SCB_CCR_UNALIGN_TRP_Pos 3
434 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
436 /* SCB System Handler Control and State Register Definitions */
437 #define SCB_SHCSR_SVCALLPENDED_Pos 15
438 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
440 /* SCB Security Features Register Definitions */
441 #define SCB_SFCR_UNIBRTIMING_Pos 0
442 #define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
444 #define SCB_SFCR_SECKEY_Pos 16
445 #define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos)
447 
458 typedef struct
459 {
460  uint32_t RESERVED0[2];
461  __IO uint32_t ACTLR;
462 } SCnSCB_Type;
463 
464 /* Auxiliary Control Register Definitions */
465 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0
466 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)
468 
479 typedef struct
480 {
481  __IO uint32_t CTRL;
482  __IO uint32_t LOAD;
483  __IO uint32_t VAL;
484  __I uint32_t CALIB;
485 } SysTick_Type;
486 
487 /* SysTick Control / Status Register Definitions */
488 #define SysTick_CTRL_COUNTFLAG_Pos 16
489 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
491 #define SysTick_CTRL_CLKSOURCE_Pos 2
492 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
494 #define SysTick_CTRL_TICKINT_Pos 1
495 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
497 #define SysTick_CTRL_ENABLE_Pos 0
498 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos)
500 /* SysTick Reload Register Definitions */
501 #define SysTick_LOAD_RELOAD_Pos 0
502 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)
504 /* SysTick Current Register Definitions */
505 #define SysTick_VAL_CURRENT_Pos 0
506 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)
508 /* SysTick Calibration Register Definitions */
509 #define SysTick_CALIB_NOREF_Pos 31
510 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
512 #define SysTick_CALIB_SKEW_Pos 30
513 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
515 #define SysTick_CALIB_TENMS_Pos 0
516 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)
518 
520 #if (__MPU_PRESENT == 1)
521 
529 typedef struct
530 {
531  __I uint32_t TYPE;
532  __IO uint32_t CTRL;
533  __IO uint32_t RNR;
534  __IO uint32_t RBAR;
535  __IO uint32_t RASR;
536 } MPU_Type;
537 
538 /* MPU Type Register */
539 #define MPU_TYPE_IREGION_Pos 16
540 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
542 #define MPU_TYPE_DREGION_Pos 8
543 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
545 #define MPU_TYPE_SEPARATE_Pos 0
546 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos)
548 /* MPU Control Register */
549 #define MPU_CTRL_PRIVDEFENA_Pos 2
550 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
552 #define MPU_CTRL_HFNMIENA_Pos 1
553 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
555 #define MPU_CTRL_ENABLE_Pos 0
556 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos)
558 /* MPU Region Number Register */
559 #define MPU_RNR_REGION_Pos 0
560 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos)
562 /* MPU Region Base Address Register */
563 #define MPU_RBAR_ADDR_Pos 8
564 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
566 #define MPU_RBAR_VALID_Pos 4
567 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
569 #define MPU_RBAR_REGION_Pos 0
570 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos)
572 /* MPU Region Attribute and Size Register */
573 #define MPU_RASR_ATTRS_Pos 16
574 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
576 #define MPU_RASR_XN_Pos 28
577 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
579 #define MPU_RASR_AP_Pos 24
580 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
582 #define MPU_RASR_TEX_Pos 19
583 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
585 #define MPU_RASR_S_Pos 18
586 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
588 #define MPU_RASR_C_Pos 17
589 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
591 #define MPU_RASR_B_Pos 16
592 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
594 #define MPU_RASR_SRD_Pos 8
595 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
597 #define MPU_RASR_SIZE_Pos 1
598 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
600 #define MPU_RASR_ENABLE_Pos 0
601 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos)
603 
604 #endif
605 
606 
614 
623 /* Memory mapping of SC000 Hardware */
624 #define SCS_BASE (0xE000E000UL)
625 #define SysTick_BASE (SCS_BASE + 0x0010UL)
626 #define NVIC_BASE (SCS_BASE + 0x0100UL)
627 #define SCB_BASE (SCS_BASE + 0x0D00UL)
629 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
630 #define SCB ((SCB_Type *) SCB_BASE )
631 #define SysTick ((SysTick_Type *) SysTick_BASE )
632 #define NVIC ((NVIC_Type *) NVIC_BASE )
634 #if (__MPU_PRESENT == 1)
635  #define MPU_BASE (SCS_BASE + 0x0D90UL)
636  #define MPU ((MPU_Type *) MPU_BASE )
637 #endif
638 
643 /*******************************************************************************
644  * Hardware Abstraction Layer
645  Core Function Interface contains:
646  - Core NVIC Functions
647  - Core SysTick Functions
648  - Core Register Access Functions
649  ******************************************************************************/
655 /* ########################## NVIC functions #################################### */
662 /* Interrupt Priorities are WORD accessible only under ARMv6M */
663 /* The following MACROS handle generation of the register offset and byte masks */
664 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
665 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
666 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
667 
668 
675 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
676 {
677  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
678 }
679 
680 
687 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
688 {
689  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
690 }
691 
692 
703 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
704 {
705  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
706 }
707 
708 
715 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
716 {
717  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
718 }
719 
720 
727 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
728 {
729  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
730 }
731 
732 
742 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
743 {
744  if(IRQn < 0) {
745  SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
746  (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
747  else {
748  NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
749  (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
750 }
751 
752 
764 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
765 {
766 
767  if(IRQn < 0) {
768  return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
769  else {
770  return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
771 }
772 
773 
778 __STATIC_INLINE void NVIC_SystemReset(void)
779 {
780  __DSB(); /* Ensure all outstanding memory accesses included
781  buffered write are completed before reset */
782  SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
784  __DSB(); /* Ensure completion of memory access */
785  while(1); /* wait until reset */
786 }
787 
792 /* ################################## SysTick function ############################################ */
799 #if (__Vendor_SysTickConfig == 0)
800 
816 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
817 {
818  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
819 
820  SysTick->LOAD = ticks - 1; /* set reload register */
821  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
822  SysTick->VAL = 0; /* Load the SysTick Counter Value */
825  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
826  return (0); /* Function successful */
827 }
828 
829 #endif
830 
836 #ifdef __cplusplus
837 }
838 #endif
839 
840 #endif /* __CORE_SC000_H_DEPENDANT */
841 
842 #endif /* __CMSIS_GENERIC */
CMSIS Cortex-M Core Function Access Header File.
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_sc000.h:404
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm0.h:309
enum IRQn IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
#define _SHP_IDX(IRQn)
Definition: core_sc000.h:665
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_sc000.h:492
Structure type to access the System Control Block (SCB).
Definition: core_cm0.h:334
CMSIS Cortex-M Core Instruction Access Header File.
IRQn
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f4xx.h:186
#define __IO
Definition: core_sc000.h:203
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm0.h:611
#define _BIT_SHIFT(IRQn)
Definition: core_sc000.h:664
#define SysTick_CTRL_TICKINT_Msk
Definition: core_sc000.h:495
#define SCB
Definition: core_sc000.h:630
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Definition: core_cm0.h:556
Structure type to access the System Timer (SysTick).
Definition: core_cm0.h:439
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Definition: core_cm0.h:647
Union type to access the Application Program Status Register (APSR).
Definition: core_cm0.h:224
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
Definition: core_cm0.h:544
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm0.h:572
#define SysTick
Definition: core_sc000.h:631
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition: core_cm0.h:685
Union type to access the Control Registers (CONTROL).
Definition: core_cm0.h:286
#define NVIC
Definition: core_sc000.h:632
#define SysTick_LOAD_RELOAD_Msk
Definition: core_sc000.h:502
Structure type to access the System Control and ID Register not in the SCB.
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm0.h:584
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm0.h:596
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm0.h:247
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm0.h:260
#define _IP_IDX(IRQn)
Definition: core_sc000.h:666
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm0.h:633
#define SysTick_CTRL_ENABLE_Msk
Definition: core_sc000.h:498
#define __NVIC_PRIO_BITS
Definition: stm32f4xx.h:178
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_sc000.h:414
#define __I
Definition: core_sc000.h:200
__IO uint32_t SFCR
Definition: core_sc000.h:352


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:18