core_cmFunc.h
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1 /**************************************************************************/
10 /* Copyright (c) 2009 - 2014 ARM LIMITED
11 
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23  *
24  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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35  ---------------------------------------------------------------------------*/
36 
37 
38 #ifndef __CORE_CMFUNC_H
39 #define __CORE_CMFUNC_H
40 
41 
42 /* ########################### Core Function Access ########################### */
48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
49 /* ARM armcc specific functions */
50 
51 #if (__ARMCC_VERSION < 400677)
52  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
53 #endif
54 
55 /* intrinsic void __enable_irq(); */
56 /* intrinsic void __disable_irq(); */
57 
64 __STATIC_INLINE uint32_t __get_CONTROL(void)
65 {
66  register uint32_t __regControl __ASM("control");
67  return(__regControl);
68 }
69 
70 
77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
78 {
79  register uint32_t __regControl __ASM("control");
80  __regControl = control;
81 }
82 
83 
90 __STATIC_INLINE uint32_t __get_IPSR(void)
91 {
92  register uint32_t __regIPSR __ASM("ipsr");
93  return(__regIPSR);
94 }
95 
96 
103 __STATIC_INLINE uint32_t __get_APSR(void)
104 {
105  register uint32_t __regAPSR __ASM("apsr");
106  return(__regAPSR);
107 }
108 
109 
116 __STATIC_INLINE uint32_t __get_xPSR(void)
117 {
118  register uint32_t __regXPSR __ASM("xpsr");
119  return(__regXPSR);
120 }
121 
122 
129 __STATIC_INLINE uint32_t __get_PSP(void)
130 {
131  register uint32_t __regProcessStackPointer __ASM("psp");
132  return(__regProcessStackPointer);
133 }
134 
135 
142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
143 {
144  register uint32_t __regProcessStackPointer __ASM("psp");
145  __regProcessStackPointer = topOfProcStack;
146 }
147 
148 
155 __STATIC_INLINE uint32_t __get_MSP(void)
156 {
157  register uint32_t __regMainStackPointer __ASM("msp");
158  return(__regMainStackPointer);
159 }
160 
161 
168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
169 {
170  register uint32_t __regMainStackPointer __ASM("msp");
171  __regMainStackPointer = topOfMainStack;
172 }
173 
174 
181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
182 {
183  register uint32_t __regPriMask __ASM("primask");
184  return(__regPriMask);
185 }
186 
187 
194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
195 {
196  register uint32_t __regPriMask __ASM("primask");
197  __regPriMask = (priMask);
198 }
199 
200 
201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
202 
208 #define __enable_fault_irq __enable_fiq
209 
210 
216 #define __disable_fault_irq __disable_fiq
217 
218 
225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
226 {
227  register uint32_t __regBasePri __ASM("basepri");
228  return(__regBasePri);
229 }
230 
231 
238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
239 {
240  register uint32_t __regBasePri __ASM("basepri");
241  __regBasePri = (basePri & 0xff);
242 }
243 
244 
251 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
252 {
253  register uint32_t __regFaultMask __ASM("faultmask");
254  return(__regFaultMask);
255 }
256 
257 
264 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
265 {
266  register uint32_t __regFaultMask __ASM("faultmask");
267  __regFaultMask = (faultMask & (uint32_t)1);
268 }
269 
270 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
271 
272 
273 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
274 
281 __STATIC_INLINE uint32_t __get_FPSCR(void)
282 {
283 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
284  register uint32_t __regfpscr __ASM("fpscr");
285  return(__regfpscr);
286 #else
287  return(0);
288 #endif
289 }
290 
291 
298 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
299 {
300 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
301  register uint32_t __regfpscr __ASM("fpscr");
302  __regfpscr = (fpscr);
303 #endif
304 }
305 
306 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
307 
308 
309 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
310 /* GNU gcc specific functions */
311 
317 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
318 {
319  __ASM volatile ("cpsie i" : : : "memory");
320 }
321 
322 
328 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
329 {
330  __ASM volatile ("cpsid i" : : : "memory");
331 }
332 
333 
340 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
341 {
342  uint32_t result;
343 
344  __ASM volatile ("MRS %0, control" : "=r" (result) );
345  return(result);
346 }
347 
348 
355 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
356 {
357  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
358 }
359 
360 
367 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
368 {
369  uint32_t result;
370 
371  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
372  return(result);
373 }
374 
375 
382 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
383 {
384  uint32_t result;
385 
386  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
387  return(result);
388 }
389 
390 
397 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
398 {
399  uint32_t result;
400 
401  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
402  return(result);
403 }
404 
405 
412 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
413 {
414  register uint32_t result;
415 
416  __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
417  return(result);
418 }
419 
420 
427 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
428 {
429  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
430 }
431 
432 
439 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
440 {
441  register uint32_t result;
442 
443  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
444  return(result);
445 }
446 
447 
454 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
455 {
456  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
457 }
458 
459 
466 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
467 {
468  uint32_t result;
469 
470  __ASM volatile ("MRS %0, primask" : "=r" (result) );
471  return(result);
472 }
473 
474 
481 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
482 {
483  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
484 }
485 
486 
487 #if (__CORTEX_M >= 0x03)
488 
494 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
495 {
496  __ASM volatile ("cpsie f" : : : "memory");
497 }
498 
499 
505 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
506 {
507  __ASM volatile ("cpsid f" : : : "memory");
508 }
509 
510 
517 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
518 {
519  uint32_t result;
520 
521  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
522  return(result);
523 }
524 
525 
532 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
533 {
534  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
535 }
536 
537 
544 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
545 {
546  uint32_t result;
547 
548  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
549  return(result);
550 }
551 
552 
559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
560 {
561  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
562 }
563 
564 #endif /* (__CORTEX_M >= 0x03) */
565 
566 
567 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
568 
575 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
576 {
577 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
578  uint32_t result;
579 
580  /* Empty asm statement works as a scheduling barrier */
581  __ASM volatile ("");
582  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
583  __ASM volatile ("");
584  return(result);
585 #else
586  return(0);
587 #endif
588 }
589 
590 
597 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
598 {
599 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
600  /* Empty asm statement works as a scheduling barrier */
601  __ASM volatile ("");
602  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
603  __ASM volatile ("");
604 #endif
605 }
606 
607 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
608 
609 
610 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
611 /* IAR iccarm specific functions */
612 #include <cmsis_iar.h>
613 
614 
615 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
616 /* TI CCS specific functions */
617 #include <cmsis_ccs.h>
618 
619 
620 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
621 /* TASKING carm specific functions */
622 /*
623  * The CMSIS functions have been implemented as intrinsics in the compiler.
624  * Please use "carm -?i" to get an up to date list of all intrinsics,
625  * Including the CMSIS ones.
626  */
627 
628 
629 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
630 /* Cosmic specific functions */
631 #include <cmsis_csm.h>
632 
633 #endif
634 
637 #endif /* __CORE_CMFUNC_H */
struct __attribute__((packed))
Definition: usbd_cdc_vcp.h:66


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:18