core_cm0plus.h
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1 /**************************************************************************/
10 /* Copyright (c) 2009 - 2014 ARM LIMITED
11 
12  All rights reserved.
13  Redistribution and use in source and binary forms, with or without
14  modification, are permitted provided that the following conditions are met:
15  - Redistributions of source code must retain the above copyright
16  notice, this list of conditions and the following disclaimer.
17  - Redistributions in binary form must reproduce the above copyright
18  notice, this list of conditions and the following disclaimer in the
19  documentation and/or other materials provided with the distribution.
20  - Neither the name of ARM nor the names of its contributors may be used
21  to endorse or promote products derived from this software without
22  specific prior written permission.
23  *
24  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34  POSSIBILITY OF SUCH DAMAGE.
35  ---------------------------------------------------------------------------*/
36 
37 
38 #if defined ( __ICCARM__ )
39  #pragma system_include /* treat file as system include file for MISRA check */
40 #endif
41 
42 #ifndef __CORE_CM0PLUS_H_GENERIC
43 #define __CORE_CM0PLUS_H_GENERIC
44 
45 #ifdef __cplusplus
46  extern "C" {
47 #endif
48 
63 /*******************************************************************************
64  * CMSIS definitions
65  ******************************************************************************/
70 /* CMSIS CM0P definitions */
71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04)
72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00)
73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
74  __CM0PLUS_CMSIS_VERSION_SUB)
76 #define __CORTEX_M (0x00)
79 #if defined ( __CC_ARM )
80  #define __ASM __asm
81  #define __INLINE __inline
82  #define __STATIC_INLINE static __inline
83 
84 #elif defined ( __GNUC__ )
85  #define __ASM __asm
86  #define __INLINE inline
87  #define __STATIC_INLINE static inline
88 
89 #elif defined ( __ICCARM__ )
90  #define __ASM __asm
91  #define __INLINE inline
92  #define __STATIC_INLINE static inline
93 
94 #elif defined ( __TMS470__ )
95  #define __ASM __asm
96  #define __STATIC_INLINE static inline
97 
98 #elif defined ( __TASKING__ )
99  #define __ASM __asm
100  #define __INLINE inline
101  #define __STATIC_INLINE static inline
102 
103 #elif defined ( __CSMC__ )
104  #define __packed
105  #define __ASM _asm
106  #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
107  #define __STATIC_INLINE static inline
108 
109 #endif
110 
114 #define __FPU_USED 0
115 
116 #if defined ( __CC_ARM )
117  #if defined __TARGET_FPU_VFP
118  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
119  #endif
120 
121 #elif defined ( __GNUC__ )
122  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
123  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
124  #endif
125 
126 #elif defined ( __ICCARM__ )
127  #if defined __ARMVFP__
128  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129  #endif
130 
131 #elif defined ( __TMS470__ )
132  #if defined __TI__VFP_SUPPORT____
133  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
134  #endif
135 
136 #elif defined ( __TASKING__ )
137  #if defined __FPU_VFP__
138  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
139  #endif
140 
141 #elif defined ( __CSMC__ ) /* Cosmic */
142  #if ( __CSMC__ & 0x400) // FPU present for parser
143  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144  #endif
145 #endif
146 
147 #include <stdint.h> /* standard types definitions */
148 #include <core_cmInstr.h> /* Core Instruction Access */
149 #include <core_cmFunc.h> /* Core Function Access */
150 
151 #ifdef __cplusplus
152 }
153 #endif
154 
155 #endif /* __CORE_CM0PLUS_H_GENERIC */
156 
157 #ifndef __CMSIS_GENERIC
158 
159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
160 #define __CORE_CM0PLUS_H_DEPENDANT
161 
162 #ifdef __cplusplus
163  extern "C" {
164 #endif
165 
166 /* check device defines and use defaults */
167 #if defined __CHECK_DEVICE_DEFINES
168  #ifndef __CM0PLUS_REV
169  #define __CM0PLUS_REV 0x0000
170  #warning "__CM0PLUS_REV not defined in device header file; using default!"
171  #endif
172 
173  #ifndef __MPU_PRESENT
174  #define __MPU_PRESENT 0
175  #warning "__MPU_PRESENT not defined in device header file; using default!"
176  #endif
177 
178  #ifndef __VTOR_PRESENT
179  #define __VTOR_PRESENT 0
180  #warning "__VTOR_PRESENT not defined in device header file; using default!"
181  #endif
182 
183  #ifndef __NVIC_PRIO_BITS
184  #define __NVIC_PRIO_BITS 2
185  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
186  #endif
187 
188  #ifndef __Vendor_SysTickConfig
189  #define __Vendor_SysTickConfig 0
190  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
191  #endif
192 #endif
193 
194 /* IO definitions (access restrictions to peripheral registers) */
202 #ifdef __cplusplus
203  #define __I volatile
204 #else
205  #define __I volatile const
206 #endif
207 #define __O volatile
208 #define __IO volatile
210 
214 /*******************************************************************************
215  * Register Abstraction
216  Core Register contain:
217  - Core Register
218  - Core NVIC Register
219  - Core SCB Register
220  - Core SysTick Register
221  - Core MPU Register
222  ******************************************************************************/
223 
235 typedef union
236 {
237  struct
238  {
239 #if (__CORTEX_M != 0x04)
240  uint32_t _reserved0:27;
241 #else
242  uint32_t _reserved0:16;
243  uint32_t GE:4;
244  uint32_t _reserved1:7;
245 #endif
246  uint32_t Q:1;
247  uint32_t V:1;
248  uint32_t C:1;
249  uint32_t Z:1;
250  uint32_t N:1;
251  } b;
252  uint32_t w;
253 } APSR_Type;
254 
255 
258 typedef union
259 {
260  struct
261  {
262  uint32_t ISR:9;
263  uint32_t _reserved0:23;
264  } b;
265  uint32_t w;
266 } IPSR_Type;
267 
268 
271 typedef union
272 {
273  struct
274  {
275  uint32_t ISR:9;
276 #if (__CORTEX_M != 0x04)
277  uint32_t _reserved0:15;
278 #else
279  uint32_t _reserved0:7;
280  uint32_t GE:4;
281  uint32_t _reserved1:4;
282 #endif
283  uint32_t T:1;
284  uint32_t IT:2;
285  uint32_t Q:1;
286  uint32_t V:1;
287  uint32_t C:1;
288  uint32_t Z:1;
289  uint32_t N:1;
290  } b;
291  uint32_t w;
292 } xPSR_Type;
293 
294 
297 typedef union
298 {
299  struct
300  {
301  uint32_t nPRIV:1;
302  uint32_t SPSEL:1;
303  uint32_t FPCA:1;
304  uint32_t _reserved0:29;
305  } b;
306  uint32_t w;
307 } CONTROL_Type;
308 
320 typedef struct
321 {
322  __IO uint32_t ISER[1];
323  uint32_t RESERVED0[31];
324  __IO uint32_t ICER[1];
325  uint32_t RSERVED1[31];
326  __IO uint32_t ISPR[1];
327  uint32_t RESERVED2[31];
328  __IO uint32_t ICPR[1];
329  uint32_t RESERVED3[31];
330  uint32_t RESERVED4[64];
331  __IO uint32_t IP[8];
332 } NVIC_Type;
333 
345 typedef struct
346 {
347  __I uint32_t CPUID;
348  __IO uint32_t ICSR;
349 #if (__VTOR_PRESENT == 1)
350  __IO uint32_t VTOR;
351 #else
352  uint32_t RESERVED0;
353 #endif
354  __IO uint32_t AIRCR;
355  __IO uint32_t SCR;
356  __IO uint32_t CCR;
357  uint32_t RESERVED1;
358  __IO uint32_t SHP[2];
359  __IO uint32_t SHCSR;
360 } SCB_Type;
361 
362 /* SCB CPUID Register Definitions */
363 #define SCB_CPUID_IMPLEMENTER_Pos 24
364 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
366 #define SCB_CPUID_VARIANT_Pos 20
367 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
369 #define SCB_CPUID_ARCHITECTURE_Pos 16
370 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
372 #define SCB_CPUID_PARTNO_Pos 4
373 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
375 #define SCB_CPUID_REVISION_Pos 0
376 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)
378 /* SCB Interrupt Control State Register Definitions */
379 #define SCB_ICSR_NMIPENDSET_Pos 31
380 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
382 #define SCB_ICSR_PENDSVSET_Pos 28
383 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
385 #define SCB_ICSR_PENDSVCLR_Pos 27
386 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
388 #define SCB_ICSR_PENDSTSET_Pos 26
389 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
391 #define SCB_ICSR_PENDSTCLR_Pos 25
392 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
394 #define SCB_ICSR_ISRPREEMPT_Pos 23
395 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
397 #define SCB_ICSR_ISRPENDING_Pos 22
398 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
400 #define SCB_ICSR_VECTPENDING_Pos 12
401 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
403 #define SCB_ICSR_VECTACTIVE_Pos 0
404 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
406 #if (__VTOR_PRESENT == 1)
407 /* SCB Interrupt Control State Register Definitions */
408 #define SCB_VTOR_TBLOFF_Pos 8
409 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)
410 #endif
411 
412 /* SCB Application Interrupt and Reset Control Register Definitions */
413 #define SCB_AIRCR_VECTKEY_Pos 16
414 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
416 #define SCB_AIRCR_VECTKEYSTAT_Pos 16
417 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
419 #define SCB_AIRCR_ENDIANESS_Pos 15
420 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
422 #define SCB_AIRCR_SYSRESETREQ_Pos 2
423 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
425 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1
426 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
428 /* SCB System Control Register Definitions */
429 #define SCB_SCR_SEVONPEND_Pos 4
430 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
432 #define SCB_SCR_SLEEPDEEP_Pos 2
433 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
435 #define SCB_SCR_SLEEPONEXIT_Pos 1
436 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
438 /* SCB Configuration Control Register Definitions */
439 #define SCB_CCR_STKALIGN_Pos 9
440 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
442 #define SCB_CCR_UNALIGN_TRP_Pos 3
443 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
445 /* SCB System Handler Control and State Register Definitions */
446 #define SCB_SHCSR_SVCALLPENDED_Pos 15
447 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
449 
460 typedef struct
461 {
462  __IO uint32_t CTRL;
463  __IO uint32_t LOAD;
464  __IO uint32_t VAL;
465  __I uint32_t CALIB;
466 } SysTick_Type;
467 
468 /* SysTick Control / Status Register Definitions */
469 #define SysTick_CTRL_COUNTFLAG_Pos 16
470 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
472 #define SysTick_CTRL_CLKSOURCE_Pos 2
473 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
475 #define SysTick_CTRL_TICKINT_Pos 1
476 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
478 #define SysTick_CTRL_ENABLE_Pos 0
479 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos)
481 /* SysTick Reload Register Definitions */
482 #define SysTick_LOAD_RELOAD_Pos 0
483 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)
485 /* SysTick Current Register Definitions */
486 #define SysTick_VAL_CURRENT_Pos 0
487 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)
489 /* SysTick Calibration Register Definitions */
490 #define SysTick_CALIB_NOREF_Pos 31
491 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
493 #define SysTick_CALIB_SKEW_Pos 30
494 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
496 #define SysTick_CALIB_TENMS_Pos 0
497 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)
499 
501 #if (__MPU_PRESENT == 1)
502 
510 typedef struct
511 {
512  __I uint32_t TYPE;
513  __IO uint32_t CTRL;
514  __IO uint32_t RNR;
515  __IO uint32_t RBAR;
516  __IO uint32_t RASR;
517 } MPU_Type;
518 
519 /* MPU Type Register */
520 #define MPU_TYPE_IREGION_Pos 16
521 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
523 #define MPU_TYPE_DREGION_Pos 8
524 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
526 #define MPU_TYPE_SEPARATE_Pos 0
527 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos)
529 /* MPU Control Register */
530 #define MPU_CTRL_PRIVDEFENA_Pos 2
531 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
533 #define MPU_CTRL_HFNMIENA_Pos 1
534 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
536 #define MPU_CTRL_ENABLE_Pos 0
537 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos)
539 /* MPU Region Number Register */
540 #define MPU_RNR_REGION_Pos 0
541 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos)
543 /* MPU Region Base Address Register */
544 #define MPU_RBAR_ADDR_Pos 8
545 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
547 #define MPU_RBAR_VALID_Pos 4
548 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
550 #define MPU_RBAR_REGION_Pos 0
551 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos)
553 /* MPU Region Attribute and Size Register */
554 #define MPU_RASR_ATTRS_Pos 16
555 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
557 #define MPU_RASR_XN_Pos 28
558 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
560 #define MPU_RASR_AP_Pos 24
561 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
563 #define MPU_RASR_TEX_Pos 19
564 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
566 #define MPU_RASR_S_Pos 18
567 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
569 #define MPU_RASR_C_Pos 17
570 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
572 #define MPU_RASR_B_Pos 16
573 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
575 #define MPU_RASR_SRD_Pos 8
576 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
578 #define MPU_RASR_SIZE_Pos 1
579 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
581 #define MPU_RASR_ENABLE_Pos 0
582 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos)
584 
585 #endif
586 
587 
595 
604 /* Memory mapping of Cortex-M0+ Hardware */
605 #define SCS_BASE (0xE000E000UL)
606 #define SysTick_BASE (SCS_BASE + 0x0010UL)
607 #define NVIC_BASE (SCS_BASE + 0x0100UL)
608 #define SCB_BASE (SCS_BASE + 0x0D00UL)
610 #define SCB ((SCB_Type *) SCB_BASE )
611 #define SysTick ((SysTick_Type *) SysTick_BASE )
612 #define NVIC ((NVIC_Type *) NVIC_BASE )
614 #if (__MPU_PRESENT == 1)
615  #define MPU_BASE (SCS_BASE + 0x0D90UL)
616  #define MPU ((MPU_Type *) MPU_BASE )
617 #endif
618 
623 /*******************************************************************************
624  * Hardware Abstraction Layer
625  Core Function Interface contains:
626  - Core NVIC Functions
627  - Core SysTick Functions
628  - Core Register Access Functions
629  ******************************************************************************/
635 /* ########################## NVIC functions #################################### */
642 /* Interrupt Priorities are WORD accessible only under ARMv6M */
643 /* The following MACROS handle generation of the register offset and byte masks */
644 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
645 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
646 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
647 
648 
655 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
656 {
657  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
658 }
659 
660 
667 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
668 {
669  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
670 }
671 
672 
683 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
684 {
685  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
686 }
687 
688 
695 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
696 {
697  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
698 }
699 
700 
707 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
708 {
709  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
710 }
711 
712 
722 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
723 {
724  if(IRQn < 0) {
725  SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
726  (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
727  else {
728  NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
729  (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
730 }
731 
732 
744 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
745 {
746 
747  if(IRQn < 0) {
748  return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
749  else {
750  return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
751 }
752 
753 
758 __STATIC_INLINE void NVIC_SystemReset(void)
759 {
760  __DSB(); /* Ensure all outstanding memory accesses included
761  buffered write are completed before reset */
762  SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
764  __DSB(); /* Ensure completion of memory access */
765  while(1); /* wait until reset */
766 }
767 
772 /* ################################## SysTick function ############################################ */
779 #if (__Vendor_SysTickConfig == 0)
780 
796 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
797 {
798  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
799 
800  SysTick->LOAD = ticks - 1; /* set reload register */
801  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
802  SysTick->VAL = 0; /* Load the SysTick Counter Value */
805  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
806  return (0); /* Function successful */
807 }
808 
809 #endif
810 
816 #ifdef __cplusplus
817 }
818 #endif
819 
820 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
821 
822 #endif /* __CMSIS_GENERIC */
CMSIS Cortex-M Core Function Access Header File.
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm0plus.h:413
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm0.h:309
enum IRQn IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
#define _SHP_IDX(IRQn)
Definition: core_cm0plus.h:645
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm0plus.h:473
Structure type to access the System Control Block (SCB).
Definition: core_cm0.h:334
CMSIS Cortex-M Core Instruction Access Header File.
IRQn
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f4xx.h:186
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm0.h:611
#define _BIT_SHIFT(IRQn)
Definition: core_cm0plus.h:644
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm0plus.h:476
#define SCB
Definition: core_cm0plus.h:610
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Definition: core_cm0.h:556
Structure type to access the System Timer (SysTick).
Definition: core_cm0.h:439
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Definition: core_cm0.h:647
Union type to access the Application Program Status Register (APSR).
Definition: core_cm0.h:224
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
Definition: core_cm0.h:544
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm0.h:572
#define SysTick
Definition: core_cm0plus.h:611
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition: core_cm0.h:685
Union type to access the Control Registers (CONTROL).
Definition: core_cm0.h:286
#define __I
Definition: core_cm0plus.h:205
#define NVIC
Definition: core_cm0plus.h:612
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm0plus.h:483
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm0.h:584
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm0.h:596
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm0.h:247
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm0.h:260
#define __IO
Definition: core_cm0plus.h:208
#define _IP_IDX(IRQn)
Definition: core_cm0plus.h:646
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm0.h:633
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm0plus.h:479
#define __NVIC_PRIO_BITS
Definition: stm32f4xx.h:178
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm0plus.h:423


rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Oct 24 2019 03:17:18