sensor_epsonG364DC0.h
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1 //==============================================================================
2 //
3 // sensor_epsonG364DC0.h - Epson G364DC0 sensor specific definitions
4 //
5 //
6 // THE SOFTWARE IS RELEASED INTO THE PUBLIC DOMAIN.
7 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
8 // INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT,
9 // SECURITY, SATISFACTORY QUALITY, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
10 // SHALL EPSON BE LIABLE FOR ANY LOSS, DAMAGE OR CLAIM, ARISING FROM OR IN CONNECTION
11 // WITH THE SOFTWARE OR THE USE OF THE SOFTWARE.
12 //
13 //==============================================================================
14 #ifndef EPSONG364DC0_H_
15 #define EPSONG364DC0_H_
16 #include<math.h>
17 #include<stdio.h>
18 
19 #define TRUE 1
20 #define FALSE 0
21 
22 #define EPSON_ACCL_SF (.125)
23 #define EPSON_GYRO_SF (.0075)
24 #define EPSON_TEMP_SF (-0.0037918)
25 #define EPSON_COUNT_SF (21330)
26 
27 #define EPSON_DA_SF0 3.750E-06
28 #define EPSON_DA_SF1 7.500E-06
29 #define EPSON_DA_SF2 1.500E-05
30 #define EPSON_DA_SF3 3.000E-05
31 #define EPSON_DA_SF4 6.000E-05
32 #define EPSON_DA_SF5 1.200E-04
33 #define EPSON_DA_SF6 2.400E-04
34 #define EPSON_DA_SF7 4.800E-04
35 #define EPSON_DA_SF8 9.600E-04
36 #define EPSON_DA_SF9 1.920E-03
37 #define EPSON_DA_SF10 3.840E-03
38 #define EPSON_DA_SF11 7.680E-03
39 #define EPSON_DA_SF12 1.536E-02
40 #define EPSON_DA_SF13 3.072E-02
41 #define EPSON_DA_SF14 6.144E-02
42 #define EPSON_DA_SF15 1.229E-01
43 
44 #define EPSON_DV_SF0 6.129E-07
45 #define EPSON_DV_SF1 1.226E-06
46 #define EPSON_DV_SF2 2.452E-06
47 #define EPSON_DV_SF3 4.903E-06
48 #define EPSON_DV_SF4 9.807E-06
49 #define EPSON_DV_SF5 1.961E-05
50 #define EPSON_DV_SF6 3.923E-05
51 #define EPSON_DV_SF7 7.845E-05
52 #define EPSON_DV_SF8 1.569E-04
53 #define EPSON_DV_SF9 3.138E-04
54 #define EPSON_DV_SF10 6.276E-04
55 #define EPSON_DV_SF11 1.255E-03
56 #define EPSON_DV_SF12 2.511E-03
57 #define EPSON_DV_SF13 5.021E-03
58 #define EPSON_DV_SF14 1.004E-02
59 #define EPSON_DV_SF15 2.008E-02
60 
61 // G364 sensor read output is configured for 32-bit
62 // Define length in 16-bit words
63 // # Bytes = Gyro(12) + Accel(12) + Count(2) + CHKSM(2)
64 // Do not count Header/Delimiter byte which is discarded by low-level function
65 #define SENSOR_READ_LEN 14
66 // This is defined in bytes and includes Header/Delimiter byte
67 #define BURSTLEN 30
68 
69 
70 /* -- Commands --
71  - ADDR_ address byte of transfer to select the register to access
72  - VAL_ data byte of transfer to write to the register selected
73 
74  - All accesses are 16 bit transfers
75  - For SPI IF:
76  - For SPI write accesses - 8-bit address with msb=1b (can be even or odd) + 8-bit write data
77  - No response
78  - For SPI read accesses - 8-bit address with msb=0b(even only) + 8-bit dummy data
79  - Response is transferred on MOSI on next SPI access
80  - Return value is 16-bit read data (high byte + low byte)
81  - For UART IF:
82  - For UART write accesses - 8-bit address with msb=1b(can be even or odd) + 8-bit write data + Delimiter Byte
83  - No response
84  - For UART read accesses - 8-bit address with msb=0b(even only) + 8-bit dummy data + Delimiter Byte
85  - Response is transferred immediately
86  - Return value consists of Register Read Address + 16-bit read data (high byte + low byte) + Delimiter Byte
87 
88  - NOTE: G354/G364/G352/G362/G320 have Register Address Maps that depend on the WINDOW_ID (page) */
89 
90 
91 // WINDOW_ID 0
92 #define ADDR_MODE_CTRL_LO 0x02 // MODE_CTRL Byte0 (W0)
93 #define ADDR_MODE_CTRL_HI 0x03 // MODE_CTRL Byte1 (W0)
94 #define ADDR_DIAG_STAT 0x04 // DIAG_STAT Byte0 (W0)
95 #define ADDR_FLAG 0x06 // FLAG(ND/EA) (W0)
96 #define ADDR_GPIO 0x08 // GPIO (W0)
97 #define ADDR_COUNT 0x0A // COUNT (W0)
98 #define ADDR_TEMP_HIGH 0x0E // TEMPC HIGH (W0)
99 #define ADDR_TEMP_LOW 0x10 // TEMPC LOW (W0)
100 #define ADDR_XGYRO_HIGH 0x12 // XGYRO HIGH (W0)
101 #define ADDR_XGYRO_LOW 0x14 // XGYRO LOW (W0)
102 #define ADDR_YGYRO_HIGH 0x16 // YGYRO HIGH (W0)
103 #define ADDR_YGYRO_LOW 0x18 // YGYRO LOW (W0)
104 #define ADDR_ZGYRO_HIGH 0x1A // ZGYRO HIGH (W0)
105 #define ADDR_ZGYRO_LOW 0x1C // ZGYRO LOW (W0)
106 #define ADDR_XACCL_HIGH 0x1E // XACCL HIGH (W0)
107 #define ADDR_XACCL_LOW 0x20 // XACCL LOW (W0)
108 #define ADDR_YACCL_HIGH 0x22 // YACCL HIGH (W0)
109 #define ADDR_YACCL_LOW 0x24 // YACCL LOW (W0)
110 #define ADDR_ZACCL_HIGH 0x26 // ZACCL HIGH (W0)
111 #define ADDR_ZACCL_LOW 0x28 // ZACCL LOW (W0)
112 
113 #define ADDR_XDLTA_HIGH 0x64 // XDLTA HIGH (W0)
114 #define ADDR_XDLTA_LOW 0x66 // XDLTA LOW (W0)
115 #define ADDR_YDLTA_HIGH 0x68 // YDLTA HIGH (W0)
116 #define ADDR_YDLTA_LOW 0x6A // YDLTA LOW (W0)
117 #define ADDR_ZDLTA_HIGH 0x6C // ZDLTA HIGH (W0)
118 #define ADDR_ZDLTA_LOW 0x6E // ZDLTA LOW (W0)
119 #define ADDR_XDLTV_HIGH 0x70 // XDLTV HIGH (W0)
120 #define ADDR_XDLTV_LOW 0x72 // XDLTV LOW (W0)
121 #define ADDR_YDLTV_HIGH 0x74 // YDLTV HIGH (W0)
122 #define ADDR_YDLTV_LOW 0x76 // YDLTV LOW (W0)
123 #define ADDR_ZDLTV_HIGH 0x78 // ZDLTV HIGH (W0)
124 #define ADDR_ZDLTV_LOW 0x7A // ZDLTV LOW (W0)
125 
126 // WINDOW_ID 1
127 #define ADDR_SIG_CTRL_LO 0x00 // SIG_CTRL Byte0 (W1)
128 #define ADDR_SIG_CTRL_HI 0x01 // SIG_CTRL Byte1 (W1)
129 #define ADDR_MSC_CTRL_LO 0x02 // MSC_CTRL Byte0 (W1)
130 #define ADDR_MSC_CTRL_HI 0x03 // MSC_CTRL Byte1 (W1)
131 #define ADDR_SMPL_CTRL_LO 0x04 // SMPL_CTRL Byte0 (W1)
132 #define ADDR_SMPL_CTRL_HI 0x05 // SMPL_CTRL Byte1 (W1)
133 #define ADDR_FILTER_CTRL_LO 0x06 // FILTER_CTRL Byte0 (W1)
134 #define ADDR_FILTER_CTRL_HI 0x07 // FILTER_CTRL Byte1 (W1)
135 #define ADDR_UART_CTRL_LO 0x08 // UART_CTRL Byte0 (W1)
136 #define ADDR_UART_CTRL_HI 0x09 // UART_CTRL Byte1 (W1)
137 #define ADDR_GLOB_CMD_LO 0x0A // GLOB_CMD Byte0 (W1)
138 #define ADDR_GLOB_CMD_HI 0x0B // GLOB_CMD Byte1 (W1)
139 #define ADDR_BURST_CTRL1_LO 0x0C // BURST_CTRL1 Byte0 (W1)
140 #define ADDR_BURST_CTRL1_HI 0x0D // BURST_CTRL1 Byte1 (W1)
141 #define ADDR_BURST_CTRL2_LO 0x0E // BURST_CTRL2 Byte0 (W1)
142 #define ADDR_BURST_CTRL2_HI 0x0F // BURST_CTRL2 Byte1 (W1)
143 #define ADDR_POL_CTRL_LO 0x10 // POL_CTRL Byte0 (W1)
144 #define ADDR_POL_CTRL_HI 0x11 // POL_CTRL Byte1 (W1)
145 #define ADDR_DLT_CTRL_LO 0x12 // DLT_CTRL Byte0 (W1)
146 #define ADDR_DLT_CTRL_HI 0x13 // DLT_CTRL Byte1 (W1)
147 
148 #define ADDR_PROD_ID1 0x6A // PROD_ID1(W1)
149 #define ADDR_PROD_ID2 0x6C // PROD_ID2(W1)
150 #define ADDR_PROD_ID3 0x6E // PROD_ID3(W1)
151 #define ADDR_PROD_ID4 0x70 // PROD_ID4(W1)
152 #define ADDR_VERSION 0x72 // VERSION(W1)
153 #define ADDR_SERIAL_NUM1 0x74 // SERIAL_NUM1(W1)
154 #define ADDR_SERIAL_NUM2 0x76 // SERIAL_NUM2(W1)
155 #define ADDR_SERIAL_NUM3 0x78 // SERIAL_NUM3(W1)
156 #define ADDR_SERIAL_NUM4 0x7A // SERIAL_NUM4(W1)
157 #define ADDR_WIN_CTRL 0x7E // WIN_CTRL(W0 or W1)
158 
159 #define CMD_BURST 0x80 // Write value to Issue Burst Read
160 
161 #define CMD_EN_NDFLAGS 0x7E // Write value for SIG_CTRL_HI to Enables new data (ND) flags in FLAG for Gyros, Accelerometers
162 #define CMD_EN_BRSTDATA_LO 0x03 // Write value for BURST_CTRL1_LO to enable CHKSM, and COUNT bytes in burst mode
163 #define CMD_EN_BRSTDATA_HI 0x30 // Write value for BURST_CTRL1_HI to enable GYRO, and ACCL registers in burst mode (0xB0 for FLAG as well)
164 #define CMD_WINDOW0 0x00 // Write value for WIN_CTRL to change to Window 0
165 #define CMD_WINDOW1 0x01 // Write value for WIN_CTRL to change to Window 1
166 #define CMD_RSTCNTR_DRDY 0x44 // Write value for MSC_CTRL_LO to enable EXT_SEL to Reset counter and active low DRDY on GPIO1
167 #define CMD_32BIT 0x30 // Write value for BURST_CTRL2_HI to enable 32 bit mode for gyro and accl data
168 #define CMD_BEGIN_SAMPLING 0x01 // Write value for MODE_CMD_HI to begin sampling
169 #define CMD_END_SAMPLING 0x02 // Write value for MODE_CMD_HI to stop sampling
170 #define CMD_SOFTRESET 0x80 // Write value for GLOB_CMD_LO to issue Software Reset
171 #define CMD_FLASHTEST 0x08 // Write value for MSC_CTRL_HI to issue Flashtest
172 #define CMD_SELFTEST 0x04 // Write value for MSC_CTRL_HI to issue Selftest
173 
174 // Write values for ADDR_SMPL_CTRL_HI to set Output Rate
175 #define CMD_RATE2000 0x00 // TAP>=0
176 #define CMD_RATE1000 0x01 // TAP>=2
177 #define CMD_RATE500 0x02 // TAP>=4
178 #define CMD_RATE250 0x03 // TAP>=8
179 #define CMD_RATE125 0x04 // TAP>=16
180 #define CMD_RATE62_5 0x05 // TAP>=32
181 #define CMD_RATE31_25 0x06 // TAP>=64
182 #define CMD_RATE15_625 0x07 // TAP=128
183 #define CMD_RATE400 0x08 // TAP>=8
184 #define CMD_RATE200 0x09 // TAP>=16
185 #define CMD_RATE100 0x0A // TAP>=32
186 #define CMD_RATE80 0x0B // TAP>=32
187 #define CMD_RATE50 0x0C // TAP>=64
188 #define CMD_RATE40 0x0D // TAP>=64
189 #define CMD_RATE25 0x0E // TAP=128
190 #define CMD_RATE20 0x0F // TAP=128
191 
192 // Write values for FILTER_CTRL_LO to set Filter
193 #define CMD_FLTAP0 0x00
194 #define CMD_FLTAP2 0x01
195 #define CMD_FLTAP4 0x02
196 #define CMD_FLTAP8 0x03
197 #define CMD_FLTAP16 0x04
198 #define CMD_FLTAP32 0x05
199 #define CMD_FLTAP64 0x06
200 #define CMD_FLTAP128 0x07
201 #define CMD_FIRTAP32FC50 0x08
202 #define CMD_FIRTAP32FC100 0x09
203 #define CMD_FIRTAP32FC200 0x0A
204 #define CMD_FIRTAP32FC400 0x0B
205 #define CMD_FIRTAP64FC50 0x0C
206 #define CMD_FIRTAP64FC100 0x0D
207 #define CMD_FIRTAP64FC200 0x0E
208 #define CMD_FIRTAP64FC400 0x0F
209 #define CMD_FIRTAP128FC50 0x10
210 #define CMD_FIRTAP128FC100 0x11
211 #define CMD_FIRTAP128FC200 0x12
212 #define CMD_FIRTAP128FC400 0x13
213 
214 // MODE STAT
215 #define VAL_SAMPLING_MODE 0x00
216 #define VAL_CONFIG_MODE 0x04
217 
218 #endif /* EPSONG364DC0_H_ */

epson_g364_imu_driver
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autogenerated on Mon Jun 10 2019 13:12:32