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00020 #ifndef RONEX_PROTOCOL_0x02000002_SPI_H_INCLUDED
00021 #define RONEX_PROTOCOL_0x02000002_SPI_H_INCLUDED
00022
00023 #include "typedefs_shadow.h"
00024
00025 #if defined(__GNUC__)
00026
00027 #else
00028 #define __attribute__(x)
00029 #endif
00030
00031 #define RONEX_COMMAND_02000002_MASTER_CLOCK_SPEED_HZ 64000000 //!< Master clock. This is divided down to create the SPI clock.
00032 #define RONEX_COMMAND_02000002_ADC_SAMPLE_RATE_HZ 1000 //!< Maximum possible ADC sample rate. Don't send EtherCAT packets faster than this.
00033 #define NUM_ANALOGUE_INPUTS 6
00034 #define ANALOGUE_INPUT_RESOLUTION 12 //!<
00035 #define ANALOGUE_INPUT_JUSTIFICATION RIGHT
00036 #define NUM_ANALOGUE_OUTPUTS 0
00037 #define ANALOGUE_OUTPUT_RESOLUTION 0
00038 #define ANALOGUE_OUTPUT_JUSTIFICATION RIGHT
00039 #define NUM_DIGITAL_IO 6
00040 #define NUM_DIO_SAMPLES 4
00041 #define NUM_SPI_OUTPUTS 4
00042 #define PRODUCT_NAME "spi"
00043 #define PRODUCT_ID 0x02000002
00044 #define MAXIMUM_NUM_STACKERS 2
00045 #define STACKER_TYPE 2 //!< range [1..13]
00046 #define SPI_TRANSACTION_MAX_SIZE 32
00047
00056 #define RONEX_COMMAND_02000002_COMMAND_TYPE_INVALID 0x0000 //!< Zeros imply a failed EtherCAT packet, so this it taken to be invalid.
00057 #define RONEX_COMMAND_02000002_COMMAND_TYPE_NORMAL 0x0001 //!< This is for normal operation.
00058 #define RONEX_COMMAND_02000002_COMMAND_TYPE_CONFIG_INFO 0x0002 //!< This requests a CONFIG_INFO_02000002 block from the node.
00059 #define RONEX_COMMAND_02000002_COMMAND_TYPE_ERROR 0x00FF //!< If this is returned from the node, then some kind of error has happened.
00060
00061
00062
00069 #define RONEX_02000002_FLAGS_STACKER_0_PRESENT 0x1000
00070 #define RONEX_02000002_FLAGS_STACKER_1_PRESENT 0x2000
00071 #define RONEX_02000002_FLAGS_STACKER_2_PRESENT 0x4000
00072 #define RONEX_02000002_FLAGS_STACKER_3_PRESENT 0x8000
00073 #define RONEX_02000002_FLAGS_STACKER_0_ERROR 0x0100
00074 #define RONEX_02000002_FLAGS_STACKER_1_ERROR 0x0200
00075 #define RONEX_02000002_FLAGS_STACKER_2_ERROR 0x0400
00076 #define RONEX_02000002_FLAGS_STACKER_3_ERROR 0x0800
00077 #define RONEX_02000002_FLAGS_RESERVED_ERRORS 0x00FC
00078 #define RONEX_02000002_FLAGS_OVER_TEMPERATURE_ERROR 0x0002
00079 #define RONEX_02000002_FLAGS_UNKNOWN_ERROR 0x0001
00080
00081 #define SPI_MODE_00_NAME "Mode 0: Pha=0 Pol=0"
00082 #define SPI_MODE_01_NAME "Mode 1: Pha=1 Pol=0"
00083 #define SPI_MODE_10_NAME "Mode 2: Pha=0 Pol=1"
00084 #define SPI_MODE_11_NAME "Mode 3: Pha=1 Pol=1"
00085
00086 #define SPI_MODE_00_DESCRIPTION "Clock normally low, sample on rising edge"
00087 #define SPI_MODE_01_DESCRIPTION "Clock normally low, sample on falling edge"
00088 #define SPI_MODE_10_DESCRIPTION "Clock normally high, sample on falling edge"
00089 #define SPI_MODE_11_DESCRIPTION "Clock normally high, sample on rising edge"
00090
00096 #define SPI_CONFIG_MODE_00 0x0000
00097 #define SPI_CONFIG_MODE_01 0x0001
00098 #define SPI_CONFIG_MODE_10 0x0002
00099 #define SPI_CONFIG_MODE_11 0x0003
00100 #define SPI_CONFIG_INPUT_TRIGGER_NONE 0x0000
00101 #define SPI_CONFIG_INPUT_TRIGGER_D0 0x0004
00102 #define SPI_CONFIG_INPUT_TRIGGER_D1 0x0008
00103 #define SPI_CONFIG_INPUT_TRIGGER_D2 0x000c
00104 #define SPI_CONFIG_INPUT_TRIGGER_D3 0x0010
00105 #define SPI_CONFIG_INPUT_TRIGGER_D4 0x0014
00106 #define SPI_CONFIG_INPUT_TRIGGER_D5 0x0018
00107 #define SPI_CONFIG_MOSI_SOMI_DIFFERENT_PIN 0x0000
00108 #define SPI_CONFIG_MOSI_SOMI_SAME_PIN 0x0020
00109
00110
00111
00123 #define IMPLEMENTED_FEATURE_TRANSACTION_SIZE 0x0001
00124 #define IMPLEMENTED_FEATURE_CLOCK_DIVIDER 0x0002
00125 #define IMPLEMENTED_FEATURE_PIN_OUTPUTS 0x0004
00126
00127 #define IMPLEMENTED_FEATURE_SPI_MODE_00 0x0008
00128 #define IMPLEMENTED_FEATURE_SPI_MODE_01 0x0010
00129 #define IMPLEMENTED_FEATURE_SPI_MODE_10 0x0020
00130 #define IMPLEMENTED_FEATURE_SPI_MODE_11 0x0040
00131 #define IMPLEMENTED_FEATURE_INTER_BYTE_DELAY 0x0080
00132
00133 #define IMPLEMENTED_FEATURE_INPUT_TRIGGERING 0x0100
00134 #define IMPLEMENTED_FEATURE_MOSI_SOMI_SAME_PIN 0x0200
00135
00136 #define IMPLEMENTED_FEATURE_ANALOGUE_INPUTS 0x0400
00137
00138
00139
00147 #define PIN_OUTPUT_STATE_DIO_0 0x0001
00148 #define PIN_OUTPUT_STATE_DIO_1 0x0002
00149 #define PIN_OUTPUT_STATE_DIO_2 0x0004
00150 #define PIN_OUTPUT_STATE_DIO_3 0x0008
00151 #define PIN_OUTPUT_STATE_DIO_4 0x0010
00152 #define PIN_OUTPUT_STATE_DIO_5 0x0020
00153 #define PIN_OUTPUT_STATE_CS_0 0x0100
00154 #define PIN_OUTPUT_STATE_CS_1 0x0200
00155 #define PIN_OUTPUT_STATE_CS_2 0x0400
00156 #define PIN_OUTPUT_STATE_CS_3 0x0800
00157
00158
00159
00167 #define PIN_INPUT_STATE_MOSI_0 0x0001
00168 #define PIN_INPUT_STATE_MOSI_1 0x0002
00169 #define PIN_INPUT_STATE_MOSI_2 0x0004
00170 #define PIN_INPUT_STATE_MOSI_3 0x0008
00171
00172
00173 typedef struct
00174 {
00175 int16u clock_divider;
00176 int16u SPI_config;
00177 int8u inter_byte_gap;
00178 int8u num_bytes;
00179 int8u data_bytes[SPI_TRANSACTION_MAX_SIZE];
00180 }__attribute__((packed)) SPI_PACKET_OUT;
00181
00182
00183 typedef struct
00184 {
00185 int16u command_type;
00186
00187 int16u pin_output_states_pre;
00188 int16u pin_output_states_post;
00189
00190 SPI_PACKET_OUT spi_out[NUM_SPI_OUTPUTS];
00191
00192 }__attribute__((packed)) RONEX_COMMAND_02000002;
00193
00194
00195
00196
00197
00198 typedef struct
00199 {
00200 int8u data_bytes[SPI_TRANSACTION_MAX_SIZE];
00201 }__attribute__((packed)) SPI_PACKET_IN;
00202
00203 typedef struct
00204 {
00205 int8u pin_input_states_DIO[NUM_DIO_SAMPLES];
00206 int8u pin_input_states_SOMI[NUM_DIO_SAMPLES];
00207
00208 SPI_PACKET_IN spi_in[NUM_SPI_OUTPUTS];
00209
00210 int16u analogue_in[6];
00211 }STATUS_DATA_02000002;
00212
00213 typedef struct
00214 {
00215 int32u implemented_features;
00216 int16u flags;
00217 int8u padding[sizeof(STATUS_DATA_02000002) - (sizeof(int32u)+sizeof(int16u))];
00218 }CONFIG_INFO_02000002;
00219
00220 typedef struct
00221 {
00222 int16u command_type;
00223
00224 union
00225 {
00226 STATUS_DATA_02000002 status_data;
00227 CONFIG_INFO_02000002 config_info;
00228 }info_type;
00229
00230 }__attribute__((packed)) RONEX_STATUS_02000002;
00231
00232
00233 #define COMMAND_ARRAY_SIZE_BYTES (sizeof(RONEX_COMMAND_02000002))
00234 #define COMMAND_ARRAY_SIZE_WORDS (sizeof(RONEX_COMMAND_02000002)/2)
00235 #define STATUS_ARRAY_SIZE_BYTES (sizeof(RONEX_STATUS_02000002))
00236 #define STATUS_ARRAY_SIZE_WORDS (sizeof(RONEX_STATUS_02000002)/2)
00237
00238
00239
00240
00241
00242 #define PROTOCOL_TYPE EC_QUEUED // Synchronous communication
00243 #define COMMAND_ADDRESS 0x1000 //!< ET1200 address containing the Command Structure
00244 #define STATUS_ADDRESS (COMMAND_ADDRESS+sizeof(RONEX_COMMAND_02000002) *4) //!< ET1200 address containing the Status Structure
00245
00246 #define RONEX_COMMAND_STRUCT RONEX_COMMAND_02000002 //!< Required for et1200_interface.h to be generic
00247 #define RONEX_STATUS_STRUCT RONEX_STATUS_02000002 //!< Required for et1200_interface.h to be generic
00248
00249 #endif