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00020 #ifndef RONEX_PROTOCOL_0x02000002_SPI_H_INCLUDED
00021 #define RONEX_PROTOCOL_0x02000002_SPI_H_INCLUDED
00022
00023 #include "typedefs_shadow.h"
00024
00025 #if defined(__GNUC__)
00026
00027 #else
00028 #define __attribute__(x)
00029 #endif
00030
00031 #define RONEX_COMMAND_02000002_MASTER_CLOCK_SPEED_HZ 64000000 //!< Master clock. This is divided down to create the SPI clock.
00032 #define RONEX_COMMAND_02000002_ADC_SAMPLE_RATE_HZ 1000 //!< Maximum possible ADC sample rate. Don't send EtherCAT packets faster than this.
00033 #define NUM_ANALOGUE_INPUTS 6
00034 #define ANALOGUE_INPUT_RESOLUTION 12 //!<
00035 #define ANALOGUE_INPUT_JUSTIFICATION RIGHT
00036 #define NUM_ANALOGUE_OUTPUTS 0
00037 #define ANALOGUE_OUTPUT_RESOLUTION 0
00038 #define ANALOGUE_OUTPUT_JUSTIFICATION RIGHT
00039 #define NUM_DIGITAL_IO 6
00040 #define NUM_DIO_SAMPLES 4
00041 #define NUM_SPI_OUTPUTS 4
00042 #define PRODUCT_NAME "spi"
00043 #define PRODUCT_ID 0x02000002
00044 #define MAXIMUM_NUM_STACKERS 2
00045 #define STACKER_TYPE 2 //!< range [1..13]
00046 #define SPI_TRANSACTION_MAX_SIZE 32
00047
00048
00057 #define RONEX_COMMAND_02000002_COMMAND_TYPE_INVALID 0x0000 //!< Zeros imply a failed EtherCAT packet, so this it taken to be invalid.
00058 #define RONEX_COMMAND_02000002_COMMAND_TYPE_NORMAL 0x0001 //!< This is for normal operation.
00059 #define RONEX_COMMAND_02000002_COMMAND_TYPE_CONFIG_INFO 0x0002 //!< This requests a CONFIG_INFO_02000002 block from the node.
00060 #define RONEX_COMMAND_02000002_COMMAND_TYPE_ERROR 0x00FF //!< If this is returned from the node, then some kind of error has happened.
00061
00062
00063
00070 #define RONEX_02000002_FLAGS_STACKER_0_PRESENT 0x1000
00071 #define RONEX_02000002_FLAGS_STACKER_1_PRESENT 0x2000
00072 #define RONEX_02000002_FLAGS_STACKER_2_PRESENT 0x4000
00073 #define RONEX_02000002_FLAGS_STACKER_3_PRESENT 0x8000
00074 #define RONEX_02000002_FLAGS_STACKER_0_ERROR 0x0100
00075 #define RONEX_02000002_FLAGS_STACKER_1_ERROR 0x0200
00076 #define RONEX_02000002_FLAGS_STACKER_2_ERROR 0x0400
00077 #define RONEX_02000002_FLAGS_STACKER_3_ERROR 0x0800
00078 #define RONEX_02000002_FLAGS_RESERVED_ERRORS 0x00FC
00079 #define RONEX_02000002_FLAGS_OVER_TEMPERATURE_ERROR 0x0002
00080 #define RONEX_02000002_FLAGS_UNKNOWN_ERROR 0x0001
00081
00082
00083
00089 #define SPI_CONFIG_MODE_00 0x0000
00090 #define SPI_CONFIG_MODE_01 0x0001
00091 #define SPI_CONFIG_MODE_10 0x0002
00092 #define SPI_CONFIG_MODE_11 0x0003
00093 #define SPI_CONFIG_INPUT_TRIGGER_NONE 0x0000
00094 #define SPI_CONFIG_INPUT_TRIGGER_D0 0x0004
00095 #define SPI_CONFIG_INPUT_TRIGGER_D1 0x0008
00096 #define SPI_CONFIG_INPUT_TRIGGER_D2 0x000c
00097 #define SPI_CONFIG_INPUT_TRIGGER_D3 0x0010
00098 #define SPI_CONFIG_INPUT_TRIGGER_D4 0x0014
00099 #define SPI_CONFIG_INPUT_TRIGGER_D5 0x0018
00100 #define SPI_CONFIG_MOSI_SOMI_DIFFERENT_PIN 0x0000
00101 #define SPI_CONFIG_MOSI_SOMI_SAME_PIN 0x0020
00102
00103
00104
00116 #define IMPLEMENTED_FEATURE_TRANSACTION_SIZE 0x0001
00117 #define IMPLEMENTED_FEATURE_CLOCK_DIVIDER 0x0002
00118 #define IMPLEMENTED_FEATURE_PIN_OUTPUTS 0x0004
00119
00120 #define IMPLEMENTED_FEATURE_SPI_MODE_00 0x0008
00121 #define IMPLEMENTED_FEATURE_SPI_MODE_01 0x0010
00122 #define IMPLEMENTED_FEATURE_SPI_MODE_10 0x0020
00123 #define IMPLEMENTED_FEATURE_SPI_MODE_11 0x0040
00124 #define IMPLEMENTED_FEATURE_INTER_BYTE_DELAY 0x0080
00125
00126 #define IMPLEMENTED_FEATURE_INPUT_TRIGGERING 0x0100
00127 #define IMPLEMENTED_FEATURE_MOSI_SOMI_SAME_PIN 0x0200
00128
00129 #define IMPLEMENTED_FEATURE_ANALOGUE_INPUTS 0x0400
00130
00131
00132
00140 #define PIN_OUTPUT_STATE_DIO_0 0x0001
00141 #define PIN_OUTPUT_DIRECTION_DIO_0 0x0002
00142 #define PIN_OUTPUT_STATE_DIO_1 0x0004
00143 #define PIN_OUTPUT_DIRECTION_DIO_1 0x0008
00144 #define PIN_OUTPUT_STATE_DIO_2 0x0010
00145 #define PIN_OUTPUT_DIRECTION_DIO_2 0x0020
00146 #define PIN_OUTPUT_STATE_DIO_3 0x0040
00147 #define PIN_OUTPUT_DIRECTION_DIO_3 0x0080
00148 #define PIN_OUTPUT_STATE_DIO_4 0x0100
00149 #define PIN_OUTPUT_DIRECTION_DIO_4 0x0200
00150 #define PIN_OUTPUT_STATE_DIO_5 0x0400
00151 #define PIN_OUTPUT_DIRECTION_DIO_5 0x0800
00152 #define PIN_OUTPUT_STATE_CS_0 0x1000
00153 #define PIN_OUTPUT_STATE_CS_1 0x2000
00154 #define PIN_OUTPUT_STATE_CS_2 0x4000
00155 #define PIN_OUTPUT_STATE_CS_3 0x8000
00156
00157
00158
00166 #define PIN_INPUT_STATE_DIO_0 0x0001
00167 #define PIN_INPUT_STATE_DIO_1 0x0002
00168 #define PIN_INPUT_STATE_DIO_2 0x0004
00169 #define PIN_INPUT_STATE_DIO_3 0x0008
00170 #define PIN_INPUT_STATE_DIO_4 0x0010
00171 #define PIN_INPUT_STATE_DIO_5 0x0020
00172 #define PIN_INPUT_STATE_MOSI_0 0x0001
00173 #define PIN_INPUT_STATE_MOSI_1 0x0002
00174 #define PIN_INPUT_STATE_MOSI_2 0x0004
00175 #define PIN_INPUT_STATE_MOSI_3 0x0008
00176
00177
00178 typedef struct
00179 {
00180 int16u clock_divider;
00181 int16u SPI_config;
00182 int8u inter_byte_gap;
00183 int8u num_bytes;
00184 int8u data_bytes[SPI_TRANSACTION_MAX_SIZE];
00185 }__attribute__((packed)) SPI_PACKET_OUT;
00186
00187
00188 typedef struct
00189 {
00190 int16u command_type;
00191
00192 int16u pin_output_states_pre;
00193 int16u pin_output_states_post;
00194
00195 SPI_PACKET_OUT spi_out[NUM_SPI_OUTPUTS];
00196
00197 }__attribute__((packed)) RONEX_COMMAND_02000002;
00198
00199
00200
00201
00202
00203 typedef struct
00204 {
00205 int8u data_bytes[SPI_TRANSACTION_MAX_SIZE];
00206 }__attribute__((packed)) SPI_PACKET_IN;
00207
00208 typedef struct
00209 {
00210 int8u pin_input_states_DIO[NUM_DIO_SAMPLES];
00211 int8u pin_input_states_SOMI[NUM_DIO_SAMPLES];
00212
00213 SPI_PACKET_IN spi_in[NUM_SPI_OUTPUTS];
00214
00215 int16u analogue_in[6];
00216 }STATUS_DATA_02000002;
00217
00218 typedef struct
00219 {
00220 int32u implemented_features;
00221 int16u flags;
00222 int8u padding[sizeof(STATUS_DATA_02000002)-6];
00223 }CONFIG_INFO_02000002;
00224
00225 typedef struct
00226 {
00227 int16u command_type;
00228
00229 union
00230 {
00231 STATUS_DATA_02000002 status_data;
00232 CONFIG_INFO_02000002 config_info;
00233 }info_type;
00234
00235 }__attribute__((packed)) RONEX_STATUS_02000002;
00236
00237
00238 #define COMMAND_ARRAY_SIZE_BYTES (sizeof(RONEX_COMMAND_02000002))
00239 #define COMMAND_ARRAY_SIZE_WORDS (sizeof(RONEX_COMMAND_02000002)/2)
00240 #define STATUS_ARRAY_SIZE_BYTES (sizeof(RONEX_STATUS_02000002))
00241 #define STATUS_ARRAY_SIZE_WORDS (sizeof(RONEX_STATUS_02000002)/2)
00242
00243
00244
00245
00246
00247 #define PROTOCOL_TYPE EC_QUEUED // Synchronous communication
00248 #define COMMAND_ADDRESS 0x1000 //!< ET1200 address containing the Command Structure
00249 #define STATUS_ADDRESS (COMMAND_ADDRESS+sizeof(RONEX_COMMAND_02000002) *4) //!< ET1200 address containing the Status Structure
00250
00251 #define RONEX_COMMAND_STRUCT RONEX_COMMAND_02000002 //!< Required for et1200_interface.h to be generic
00252 #define RONEX_STATUS_STRUCT RONEX_STATUS_02000002 //!< Required for et1200_interface.h to be generic
00253
00254 #endif