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00040 #include "../../rtt-config.h"
00041 #ifndef __ORO_ARCH_x86_64__
00042 #define __ORO_ARCH_x86_64__
00043
00044 #ifndef CONFIG_FORCE_UP
00045 #define ORO_LOCK "lock ; "
00046 #else
00047 #define ORO_LOCK ""
00048 #endif
00049
00050 typedef struct { volatile int counter; } oro_atomic_t;
00051
00052 #define ORO_ATOMIC_SETUP oro_atomic_set
00053 #define ORO_ATOMIC_CLEANUP(v)
00054
00055 #define oro_atomic_read(v) ((v)->counter)
00056
00057 #define oro_atomic_set(v,i) (((v)->counter) = (i))
00058
00059 static __inline__ void oro_atomic_add(oro_atomic_t *v, int i)
00060 {
00061 __asm__ __volatile__(
00062 ORO_LOCK "addl %1,%0"
00063 :"=m" (v->counter)
00064 :"ir" (i), "m" (v->counter));
00065 }
00066
00067 static __inline__ void oro_atomic_sub(oro_atomic_t *v, int i)
00068 {
00069 __asm__ __volatile__(
00070 ORO_LOCK "subl %1,%0"
00071 :"=m" (v->counter)
00072 :"ir" (i), "m" (v->counter));
00073 }
00074
00075 static __inline__ int oro_atomic_sub_and_test(oro_atomic_t *v, int i)
00076 {
00077 unsigned char c;
00078
00079 __asm__ __volatile__(
00080 ORO_LOCK "subl %2,%0; sete %1"
00081 :"=m" (v->counter), "=qm" (c)
00082 :"ir" (i), "m" (v->counter) : "memory");
00083 return c;
00084 }
00085
00086 static __inline__ void oro_atomic_inc(oro_atomic_t *v)
00087 {
00088 __asm__ __volatile__(
00089 ORO_LOCK "incl %0"
00090 :"=m" (v->counter)
00091 :"m" (v->counter));
00092 }
00093
00094 static __inline__ void oro_atomic_dec(oro_atomic_t *v)
00095 {
00096 __asm__ __volatile__(
00097 ORO_LOCK "decl %0"
00098 :"=m" (v->counter)
00099 :"m" (v->counter));
00100 }
00101
00102 static __inline__ int oro_atomic_dec_and_test(oro_atomic_t *v)
00103 {
00104 unsigned char c;
00105
00106 __asm__ __volatile__(
00107 ORO_LOCK "decl %0; sete %1"
00108 :"=m" (v->counter), "=qm" (c)
00109 :"m" (v->counter) : "memory");
00110 return c != 0;
00111 }
00112
00113 static __inline__ int oro_atomic_inc_and_test(oro_atomic_t *v)
00114 {
00115 unsigned char c;
00116
00117 __asm__ __volatile__(
00118 ORO_LOCK "incl %0; sete %1"
00119 :"=m" (v->counter), "=qm" (c)
00120 :"m" (v->counter) : "memory");
00121 return c != 0;
00122 }
00123
00124 static __inline__ int oro_atomic_add_negative(int i, oro_atomic_t *v)
00125 {
00126 unsigned char c;
00127
00128 __asm__ __volatile__(
00129 ORO_LOCK "addl %2,%0; sets %1"
00130 :"=m" (v->counter), "=qm" (c)
00131 :"ir" (i), "m" (v->counter) : "memory");
00132 return c;
00133 }
00134
00135 #ifndef CONFIG_FORCE_UP
00136 #define ORO_LOCK_PREFIX "lock ; "
00137 #else
00138 #define ORO_LOCK_PREFIX ""
00139 #endif
00140
00141 struct oro__xchg_dummy { unsigned long a[100]; };
00142 #define oro__xg(x) ((struct oro__xchg_dummy *)(x))
00143
00144 static inline unsigned long __oro_cmpxchg(volatile void *ptr, unsigned long old,
00145 unsigned long _new, int size)
00146 {
00147 unsigned long prev;
00148 switch (size) {
00149 case 1:
00150 __asm__ __volatile__(ORO_LOCK_PREFIX "cmpxchgb %b1,%2"
00151 : "=a"(prev)
00152 : "q"(_new), "m"(*oro__xg(ptr)), "0"(old)
00153 : "memory");
00154 return prev;
00155 case 2:
00156 __asm__ __volatile__(ORO_LOCK_PREFIX "cmpxchgw %w1,%2"
00157 : "=a"(prev)
00158 : "q"(_new), "m"(*oro__xg(ptr)), "0"(old)
00159 : "memory");
00160 return prev;
00161 case 4:
00162 __asm__ __volatile__(ORO_LOCK_PREFIX "cmpxchgl %k1,%2"
00163 : "=a"(prev)
00164 : "q"(_new), "m"(*oro__xg(ptr)), "0"(old)
00165 : "memory");
00166 return prev;
00167 case 8:
00168 __asm__ __volatile__(ORO_LOCK_PREFIX "cmpxchgq %1,%2"
00169 : "=a"(prev)
00170 : "q"(_new), "m"(*oro__xg(ptr)), "0"(old)
00171 : "memory");
00172 return prev;
00173
00174 }
00175 return old;
00176 }
00177
00178 #define oro_cmpxchg(ptr,o,n)\
00179 ((__typeof__(*(ptr)))__oro_cmpxchg((ptr),(unsigned long)(o),\
00180 (unsigned long)(n),sizeof(*(ptr))))
00181
00182 #undef ORO_LOCK_PREFIX
00183 #undef ORO_LOCK
00184 #endif