initvals.c
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00001 /*
00002  * Initial register settings functions
00003  *
00004  * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
00005  * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
00006  * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
00007  *
00008  * Permission to use, copy, modify, and distribute this software for any
00009  * purpose with or without fee is hereby granted, provided that the above
00010  * copyright notice and this permission notice appear in all copies.
00011  *
00012  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00013  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00014  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00015  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00016  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00017  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00018  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00019  *
00020  */
00021 
00022 #include "ath5k.h"
00023 #include "reg.h"
00024 #include "debug.h"
00025 #include "base.h"
00026 
00027 /*
00028  * Mode-independent initial register writes
00029  */
00030 
00031 struct ath5k_ini {
00032         u16     ini_register;
00033         u32     ini_value;
00034 
00035         enum {
00036                 AR5K_INI_WRITE = 0,     /* Default */
00037                 AR5K_INI_READ = 1,      /* Cleared on read */
00038         } ini_mode;
00039 };
00040 
00041 /*
00042  * Mode specific initial register values
00043  */
00044 
00045 struct ath5k_ini_mode {
00046         u16     mode_register;
00047         u32     mode_value[5];
00048 };
00049 
00050 /* Initial register settings for AR5210 */
00051 static const struct ath5k_ini ar5210_ini[] = {
00052         /* PCU and MAC registers */
00053         { AR5K_NOQCU_TXDP0,     0 },
00054         { AR5K_NOQCU_TXDP1,     0 },
00055         { AR5K_RXDP,            0 },
00056         { AR5K_CR,              0 },
00057         { AR5K_ISR,             0, AR5K_INI_READ },
00058         { AR5K_IMR,             0 },
00059         { AR5K_IER,             AR5K_IER_DISABLE },
00060         { AR5K_BSR,             0, AR5K_INI_READ },
00061         { AR5K_TXCFG,           AR5K_DMASIZE_128B },
00062         { AR5K_RXCFG,           AR5K_DMASIZE_128B },
00063         { AR5K_CFG,             AR5K_INIT_CFG },
00064         { AR5K_TOPS,            8 },
00065         { AR5K_RXNOFRM,         8 },
00066         { AR5K_RPGTO,           0 },
00067         { AR5K_TXNOFRM,         0 },
00068         { AR5K_SFR,             0 },
00069         { AR5K_MIBC,            0 },
00070         { AR5K_MISC,            0 },
00071         { AR5K_RX_FILTER_5210,  0 },
00072         { AR5K_MCAST_FILTER0_5210, 0 },
00073         { AR5K_MCAST_FILTER1_5210, 0 },
00074         { AR5K_TX_MASK0,        0 },
00075         { AR5K_TX_MASK1,        0 },
00076         { AR5K_CLR_TMASK,       0 },
00077         { AR5K_TRIG_LVL,        AR5K_TUNE_MIN_TX_FIFO_THRES },
00078         { AR5K_DIAG_SW_5210,    0 },
00079         { AR5K_RSSI_THR,        AR5K_TUNE_RSSI_THRES },
00080         { AR5K_TSF_L32_5210,    0 },
00081         { AR5K_TIMER0_5210,     0 },
00082         { AR5K_TIMER1_5210,     0xffffffff },
00083         { AR5K_TIMER2_5210,     0xffffffff },
00084         { AR5K_TIMER3_5210,     1 },
00085         { AR5K_CFP_DUR_5210,    0 },
00086         { AR5K_CFP_PERIOD_5210, 0 },
00087         /* PHY registers */
00088         { AR5K_PHY(0),  0x00000047 },
00089         { AR5K_PHY_AGC, 0x00000000 },
00090         { AR5K_PHY(3),  0x09848ea6 },
00091         { AR5K_PHY(4),  0x3d32e000 },
00092         { AR5K_PHY(5),  0x0000076b },
00093         { AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE },
00094         { AR5K_PHY(8),  0x02020200 },
00095         { AR5K_PHY(9),  0x00000e0e },
00096         { AR5K_PHY(10), 0x0a020201 },
00097         { AR5K_PHY(11), 0x00036ffc },
00098         { AR5K_PHY(12), 0x00000000 },
00099         { AR5K_PHY(13), 0x00000e0e },
00100         { AR5K_PHY(14), 0x00000007 },
00101         { AR5K_PHY(15), 0x00020100 },
00102         { AR5K_PHY(16), 0x89630000 },
00103         { AR5K_PHY(17), 0x1372169c },
00104         { AR5K_PHY(18), 0x0018b633 },
00105         { AR5K_PHY(19), 0x1284613c },
00106         { AR5K_PHY(20), 0x0de8b8e0 },
00107         { AR5K_PHY(21), 0x00074859 },
00108         { AR5K_PHY(22), 0x7e80beba },
00109         { AR5K_PHY(23), 0x313a665e },
00110         { AR5K_PHY_AGCCTL, 0x00001d08 },
00111         { AR5K_PHY(25), 0x0001ce00 },
00112         { AR5K_PHY(26), 0x409a4190 },
00113         { AR5K_PHY(28), 0x0000000f },
00114         { AR5K_PHY(29), 0x00000080 },
00115         { AR5K_PHY(30), 0x00000004 },
00116         { AR5K_PHY(31), 0x00000018 },   /* 0x987c */
00117         { AR5K_PHY(64), 0x00000000 },   /* 0x9900 */
00118         { AR5K_PHY(65), 0x00000000 },
00119         { AR5K_PHY(66), 0x00000000 },
00120         { AR5K_PHY(67), 0x00800000 },
00121         { AR5K_PHY(68), 0x00000003 },
00122         /* BB gain table (64bytes) */
00123         { AR5K_BB_GAIN(0), 0x00000000 },
00124         { AR5K_BB_GAIN(1), 0x00000020 },
00125         { AR5K_BB_GAIN(2), 0x00000010 },
00126         { AR5K_BB_GAIN(3), 0x00000030 },
00127         { AR5K_BB_GAIN(4), 0x00000008 },
00128         { AR5K_BB_GAIN(5), 0x00000028 },
00129         { AR5K_BB_GAIN(6), 0x00000028 },
00130         { AR5K_BB_GAIN(7), 0x00000004 },
00131         { AR5K_BB_GAIN(8), 0x00000024 },
00132         { AR5K_BB_GAIN(9), 0x00000014 },
00133         { AR5K_BB_GAIN(10), 0x00000034 },
00134         { AR5K_BB_GAIN(11), 0x0000000c },
00135         { AR5K_BB_GAIN(12), 0x0000002c },
00136         { AR5K_BB_GAIN(13), 0x00000002 },
00137         { AR5K_BB_GAIN(14), 0x00000022 },
00138         { AR5K_BB_GAIN(15), 0x00000012 },
00139         { AR5K_BB_GAIN(16), 0x00000032 },
00140         { AR5K_BB_GAIN(17), 0x0000000a },
00141         { AR5K_BB_GAIN(18), 0x0000002a },
00142         { AR5K_BB_GAIN(19), 0x00000001 },
00143         { AR5K_BB_GAIN(20), 0x00000021 },
00144         { AR5K_BB_GAIN(21), 0x00000011 },
00145         { AR5K_BB_GAIN(22), 0x00000031 },
00146         { AR5K_BB_GAIN(23), 0x00000009 },
00147         { AR5K_BB_GAIN(24), 0x00000029 },
00148         { AR5K_BB_GAIN(25), 0x00000005 },
00149         { AR5K_BB_GAIN(26), 0x00000025 },
00150         { AR5K_BB_GAIN(27), 0x00000015 },
00151         { AR5K_BB_GAIN(28), 0x00000035 },
00152         { AR5K_BB_GAIN(29), 0x0000000d },
00153         { AR5K_BB_GAIN(30), 0x0000002d },
00154         { AR5K_BB_GAIN(31), 0x00000003 },
00155         { AR5K_BB_GAIN(32), 0x00000023 },
00156         { AR5K_BB_GAIN(33), 0x00000013 },
00157         { AR5K_BB_GAIN(34), 0x00000033 },
00158         { AR5K_BB_GAIN(35), 0x0000000b },
00159         { AR5K_BB_GAIN(36), 0x0000002b },
00160         { AR5K_BB_GAIN(37), 0x00000007 },
00161         { AR5K_BB_GAIN(38), 0x00000027 },
00162         { AR5K_BB_GAIN(39), 0x00000017 },
00163         { AR5K_BB_GAIN(40), 0x00000037 },
00164         { AR5K_BB_GAIN(41), 0x0000000f },
00165         { AR5K_BB_GAIN(42), 0x0000002f },
00166         { AR5K_BB_GAIN(43), 0x0000002f },
00167         { AR5K_BB_GAIN(44), 0x0000002f },
00168         { AR5K_BB_GAIN(45), 0x0000002f },
00169         { AR5K_BB_GAIN(46), 0x0000002f },
00170         { AR5K_BB_GAIN(47), 0x0000002f },
00171         { AR5K_BB_GAIN(48), 0x0000002f },
00172         { AR5K_BB_GAIN(49), 0x0000002f },
00173         { AR5K_BB_GAIN(50), 0x0000002f },
00174         { AR5K_BB_GAIN(51), 0x0000002f },
00175         { AR5K_BB_GAIN(52), 0x0000002f },
00176         { AR5K_BB_GAIN(53), 0x0000002f },
00177         { AR5K_BB_GAIN(54), 0x0000002f },
00178         { AR5K_BB_GAIN(55), 0x0000002f },
00179         { AR5K_BB_GAIN(56), 0x0000002f },
00180         { AR5K_BB_GAIN(57), 0x0000002f },
00181         { AR5K_BB_GAIN(58), 0x0000002f },
00182         { AR5K_BB_GAIN(59), 0x0000002f },
00183         { AR5K_BB_GAIN(60), 0x0000002f },
00184         { AR5K_BB_GAIN(61), 0x0000002f },
00185         { AR5K_BB_GAIN(62), 0x0000002f },
00186         { AR5K_BB_GAIN(63), 0x0000002f },
00187         /* 5110 RF gain table (64btes) */
00188         { AR5K_RF_GAIN(0), 0x0000001d },
00189         { AR5K_RF_GAIN(1), 0x0000005d },
00190         { AR5K_RF_GAIN(2), 0x0000009d },
00191         { AR5K_RF_GAIN(3), 0x000000dd },
00192         { AR5K_RF_GAIN(4), 0x0000011d },
00193         { AR5K_RF_GAIN(5), 0x00000021 },
00194         { AR5K_RF_GAIN(6), 0x00000061 },
00195         { AR5K_RF_GAIN(7), 0x000000a1 },
00196         { AR5K_RF_GAIN(8), 0x000000e1 },
00197         { AR5K_RF_GAIN(9), 0x00000031 },
00198         { AR5K_RF_GAIN(10), 0x00000071 },
00199         { AR5K_RF_GAIN(11), 0x000000b1 },
00200         { AR5K_RF_GAIN(12), 0x0000001c },
00201         { AR5K_RF_GAIN(13), 0x0000005c },
00202         { AR5K_RF_GAIN(14), 0x00000029 },
00203         { AR5K_RF_GAIN(15), 0x00000069 },
00204         { AR5K_RF_GAIN(16), 0x000000a9 },
00205         { AR5K_RF_GAIN(17), 0x00000020 },
00206         { AR5K_RF_GAIN(18), 0x00000019 },
00207         { AR5K_RF_GAIN(19), 0x00000059 },
00208         { AR5K_RF_GAIN(20), 0x00000099 },
00209         { AR5K_RF_GAIN(21), 0x00000030 },
00210         { AR5K_RF_GAIN(22), 0x00000005 },
00211         { AR5K_RF_GAIN(23), 0x00000025 },
00212         { AR5K_RF_GAIN(24), 0x00000065 },
00213         { AR5K_RF_GAIN(25), 0x000000a5 },
00214         { AR5K_RF_GAIN(26), 0x00000028 },
00215         { AR5K_RF_GAIN(27), 0x00000068 },
00216         { AR5K_RF_GAIN(28), 0x0000001f },
00217         { AR5K_RF_GAIN(29), 0x0000001e },
00218         { AR5K_RF_GAIN(30), 0x00000018 },
00219         { AR5K_RF_GAIN(31), 0x00000058 },
00220         { AR5K_RF_GAIN(32), 0x00000098 },
00221         { AR5K_RF_GAIN(33), 0x00000003 },
00222         { AR5K_RF_GAIN(34), 0x00000004 },
00223         { AR5K_RF_GAIN(35), 0x00000044 },
00224         { AR5K_RF_GAIN(36), 0x00000084 },
00225         { AR5K_RF_GAIN(37), 0x00000013 },
00226         { AR5K_RF_GAIN(38), 0x00000012 },
00227         { AR5K_RF_GAIN(39), 0x00000052 },
00228         { AR5K_RF_GAIN(40), 0x00000092 },
00229         { AR5K_RF_GAIN(41), 0x000000d2 },
00230         { AR5K_RF_GAIN(42), 0x0000002b },
00231         { AR5K_RF_GAIN(43), 0x0000002a },
00232         { AR5K_RF_GAIN(44), 0x0000006a },
00233         { AR5K_RF_GAIN(45), 0x000000aa },
00234         { AR5K_RF_GAIN(46), 0x0000001b },
00235         { AR5K_RF_GAIN(47), 0x0000001a },
00236         { AR5K_RF_GAIN(48), 0x0000005a },
00237         { AR5K_RF_GAIN(49), 0x0000009a },
00238         { AR5K_RF_GAIN(50), 0x000000da },
00239         { AR5K_RF_GAIN(51), 0x00000006 },
00240         { AR5K_RF_GAIN(52), 0x00000006 },
00241         { AR5K_RF_GAIN(53), 0x00000006 },
00242         { AR5K_RF_GAIN(54), 0x00000006 },
00243         { AR5K_RF_GAIN(55), 0x00000006 },
00244         { AR5K_RF_GAIN(56), 0x00000006 },
00245         { AR5K_RF_GAIN(57), 0x00000006 },
00246         { AR5K_RF_GAIN(58), 0x00000006 },
00247         { AR5K_RF_GAIN(59), 0x00000006 },
00248         { AR5K_RF_GAIN(60), 0x00000006 },
00249         { AR5K_RF_GAIN(61), 0x00000006 },
00250         { AR5K_RF_GAIN(62), 0x00000006 },
00251         { AR5K_RF_GAIN(63), 0x00000006 },
00252         /* PHY activation */
00253         { AR5K_PHY(53), 0x00000020 },
00254         { AR5K_PHY(51), 0x00000004 },
00255         { AR5K_PHY(50), 0x00060106 },
00256         { AR5K_PHY(39), 0x0000006d },
00257         { AR5K_PHY(48), 0x00000000 },
00258         { AR5K_PHY(52), 0x00000014 },
00259         { AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE },
00260 };
00261 
00262 /* Initial register settings for AR5211 */
00263 static const struct ath5k_ini ar5211_ini[] = {
00264         { AR5K_RXDP,            0x00000000 },
00265         { AR5K_RTSD0,           0x84849c9c },
00266         { AR5K_RTSD1,           0x7c7c7c7c },
00267         { AR5K_RXCFG,           0x00000005 },
00268         { AR5K_MIBC,            0x00000000 },
00269         { AR5K_TOPS,            0x00000008 },
00270         { AR5K_RXNOFRM,         0x00000008 },
00271         { AR5K_TXNOFRM,         0x00000010 },
00272         { AR5K_RPGTO,           0x00000000 },
00273         { AR5K_RFCNT,           0x0000001f },
00274         { AR5K_QUEUE_TXDP(0),   0x00000000 },
00275         { AR5K_QUEUE_TXDP(1),   0x00000000 },
00276         { AR5K_QUEUE_TXDP(2),   0x00000000 },
00277         { AR5K_QUEUE_TXDP(3),   0x00000000 },
00278         { AR5K_QUEUE_TXDP(4),   0x00000000 },
00279         { AR5K_QUEUE_TXDP(5),   0x00000000 },
00280         { AR5K_QUEUE_TXDP(6),   0x00000000 },
00281         { AR5K_QUEUE_TXDP(7),   0x00000000 },
00282         { AR5K_QUEUE_TXDP(8),   0x00000000 },
00283         { AR5K_QUEUE_TXDP(9),   0x00000000 },
00284         { AR5K_DCU_FP,          0x00000000 },
00285         { AR5K_STA_ID1,         0x00000000 },
00286         { AR5K_BSS_ID0,         0x00000000 },
00287         { AR5K_BSS_ID1,         0x00000000 },
00288         { AR5K_RSSI_THR,        0x00000000 },
00289         { AR5K_CFP_PERIOD_5211, 0x00000000 },
00290         { AR5K_TIMER0_5211,     0x00000030 },
00291         { AR5K_TIMER1_5211,     0x0007ffff },
00292         { AR5K_TIMER2_5211,     0x01ffffff },
00293         { AR5K_TIMER3_5211,     0x00000031 },
00294         { AR5K_CFP_DUR_5211,    0x00000000 },
00295         { AR5K_RX_FILTER_5211,  0x00000000 },
00296         { AR5K_MCAST_FILTER0_5211, 0x00000000 },
00297         { AR5K_MCAST_FILTER1_5211, 0x00000002 },
00298         { AR5K_DIAG_SW_5211,    0x00000000 },
00299         { AR5K_ADDAC_TEST,      0x00000000 },
00300         { AR5K_DEFAULT_ANTENNA, 0x00000000 },
00301         /* PHY registers */
00302         { AR5K_PHY_AGC, 0x00000000 },
00303         { AR5K_PHY(3),  0x2d849093 },
00304         { AR5K_PHY(4),  0x7d32e000 },
00305         { AR5K_PHY(5),  0x00000f6b },
00306         { AR5K_PHY_ACT, 0x00000000 },
00307         { AR5K_PHY(11), 0x00026ffe },
00308         { AR5K_PHY(12), 0x00000000 },
00309         { AR5K_PHY(15), 0x00020100 },
00310         { AR5K_PHY(16), 0x206a017a },
00311         { AR5K_PHY(19), 0x1284613c },
00312         { AR5K_PHY(21), 0x00000859 },
00313         { AR5K_PHY(26), 0x409a4190 },   /* 0x9868 */
00314         { AR5K_PHY(27), 0x050cb081 },
00315         { AR5K_PHY(28), 0x0000000f },
00316         { AR5K_PHY(29), 0x00000080 },
00317         { AR5K_PHY(30), 0x0000000c },
00318         { AR5K_PHY(64), 0x00000000 },
00319         { AR5K_PHY(65), 0x00000000 },
00320         { AR5K_PHY(66), 0x00000000 },
00321         { AR5K_PHY(67), 0x00800000 },
00322         { AR5K_PHY(68), 0x00000001 },
00323         { AR5K_PHY(71), 0x0000092a },
00324         { AR5K_PHY_IQ,  0x00000000 },
00325         { AR5K_PHY(73), 0x00058a05 },
00326         { AR5K_PHY(74), 0x00000001 },
00327         { AR5K_PHY(75), 0x00000000 },
00328         { AR5K_PHY_PAPD_PROBE, 0x00000000 },
00329         { AR5K_PHY(77), 0x00000000 },   /* 0x9934 */
00330         { AR5K_PHY(78), 0x00000000 },   /* 0x9938 */
00331         { AR5K_PHY(79), 0x0000003f },   /* 0x993c */
00332         { AR5K_PHY(80), 0x00000004 },
00333         { AR5K_PHY(82), 0x00000000 },
00334         { AR5K_PHY(83), 0x00000000 },
00335         { AR5K_PHY(84), 0x00000000 },
00336         { AR5K_PHY_RADAR, 0x5d50f14c },
00337         { AR5K_PHY(86), 0x00000018 },
00338         { AR5K_PHY(87), 0x004b6a8e },
00339         /* Initial Power table (32bytes)
00340          * common on all cards/modes.
00341          * Note: Table is rewritten during
00342          * txpower setup later using calibration
00343          * data etc. so next write is non-common */
00344         { AR5K_PHY_PCDAC_TXPOWER(1), 0x06ff05ff },
00345         { AR5K_PHY_PCDAC_TXPOWER(2), 0x07ff07ff },
00346         { AR5K_PHY_PCDAC_TXPOWER(3), 0x08ff08ff },
00347         { AR5K_PHY_PCDAC_TXPOWER(4), 0x09ff09ff },
00348         { AR5K_PHY_PCDAC_TXPOWER(5), 0x0aff0aff },
00349         { AR5K_PHY_PCDAC_TXPOWER(6), 0x0bff0bff },
00350         { AR5K_PHY_PCDAC_TXPOWER(7), 0x0cff0cff },
00351         { AR5K_PHY_PCDAC_TXPOWER(8), 0x0dff0dff },
00352         { AR5K_PHY_PCDAC_TXPOWER(9), 0x0fff0eff },
00353         { AR5K_PHY_PCDAC_TXPOWER(10), 0x12ff12ff },
00354         { AR5K_PHY_PCDAC_TXPOWER(11), 0x14ff13ff },
00355         { AR5K_PHY_PCDAC_TXPOWER(12), 0x16ff15ff },
00356         { AR5K_PHY_PCDAC_TXPOWER(13), 0x19ff17ff },
00357         { AR5K_PHY_PCDAC_TXPOWER(14), 0x1bff1aff },
00358         { AR5K_PHY_PCDAC_TXPOWER(15), 0x1eff1dff },
00359         { AR5K_PHY_PCDAC_TXPOWER(16), 0x23ff20ff },
00360         { AR5K_PHY_PCDAC_TXPOWER(17), 0x27ff25ff },
00361         { AR5K_PHY_PCDAC_TXPOWER(18), 0x2cff29ff },
00362         { AR5K_PHY_PCDAC_TXPOWER(19), 0x31ff2fff },
00363         { AR5K_PHY_PCDAC_TXPOWER(20), 0x37ff34ff },
00364         { AR5K_PHY_PCDAC_TXPOWER(21), 0x3aff3aff },
00365         { AR5K_PHY_PCDAC_TXPOWER(22), 0x3aff3aff },
00366         { AR5K_PHY_PCDAC_TXPOWER(23), 0x3aff3aff },
00367         { AR5K_PHY_PCDAC_TXPOWER(24), 0x3aff3aff },
00368         { AR5K_PHY_PCDAC_TXPOWER(25), 0x3aff3aff },
00369         { AR5K_PHY_PCDAC_TXPOWER(26), 0x3aff3aff },
00370         { AR5K_PHY_PCDAC_TXPOWER(27), 0x3aff3aff },
00371         { AR5K_PHY_PCDAC_TXPOWER(28), 0x3aff3aff },
00372         { AR5K_PHY_PCDAC_TXPOWER(29), 0x3aff3aff },
00373         { AR5K_PHY_PCDAC_TXPOWER(30), 0x3aff3aff },
00374         { AR5K_PHY_PCDAC_TXPOWER(31), 0x3aff3aff },
00375         { AR5K_PHY_CCKTXCTL, 0x00000000 },
00376         { AR5K_PHY(642), 0x503e4646 },
00377         { AR5K_PHY_GAIN_2GHZ, 0x6480416c },
00378         { AR5K_PHY(644), 0x0199a003 },
00379         { AR5K_PHY(645), 0x044cd610 },
00380         { AR5K_PHY(646), 0x13800040 },
00381         { AR5K_PHY(647), 0x1be00060 },
00382         { AR5K_PHY(648), 0x0c53800a },
00383         { AR5K_PHY(649), 0x0014df3b },
00384         { AR5K_PHY(650), 0x000001b5 },
00385         { AR5K_PHY(651), 0x00000020 },
00386 };
00387 
00388 /* Initial mode-specific settings for AR5211
00389  * 5211 supports OFDM-only g (draft g) but we
00390  * need to test it !
00391  */
00392 static const struct ath5k_ini_mode ar5211_ini_mode[] = {
00393         { AR5K_TXCFG,
00394         /*        a         aTurbo        b       g (OFDM)    */
00395            { 0x00000015, 0x00000015, 0x0000001d, 0x00000015 } },
00396         { AR5K_QUEUE_DFS_LOCAL_IFS(0),
00397            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00398         { AR5K_QUEUE_DFS_LOCAL_IFS(1),
00399            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00400         { AR5K_QUEUE_DFS_LOCAL_IFS(2),
00401            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00402         { AR5K_QUEUE_DFS_LOCAL_IFS(3),
00403            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00404         { AR5K_QUEUE_DFS_LOCAL_IFS(4),
00405            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00406         { AR5K_QUEUE_DFS_LOCAL_IFS(5),
00407            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00408         { AR5K_QUEUE_DFS_LOCAL_IFS(6),
00409            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00410         { AR5K_QUEUE_DFS_LOCAL_IFS(7),
00411            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00412         { AR5K_QUEUE_DFS_LOCAL_IFS(8),
00413            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00414         { AR5K_QUEUE_DFS_LOCAL_IFS(9),
00415            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00416         { AR5K_DCU_GBL_IFS_SLOT,
00417            { 0x00000168, 0x000001e0, 0x000001b8, 0x00000168 } },
00418         { AR5K_DCU_GBL_IFS_SIFS,
00419            { 0x00000230, 0x000001e0, 0x000000b0, 0x00000230 } },
00420         { AR5K_DCU_GBL_IFS_EIFS,
00421            { 0x00000d98, 0x00001180, 0x00001f48, 0x00000d98 } },
00422         { AR5K_DCU_GBL_IFS_MISC,
00423            { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000a0e0 } },
00424         { AR5K_TIME_OUT,
00425            { 0x04000400, 0x08000800, 0x20003000, 0x04000400 } },
00426         { AR5K_USEC_5211,
00427            { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95, 0x0e8d8fa7 } },
00428         { AR5K_PHY_TURBO,
00429            { 0x00000000, 0x00000003, 0x00000000, 0x00000000 } },
00430         { AR5K_PHY(8),
00431            { 0x02020200, 0x02020200, 0x02010200, 0x02020200 } },
00432         { AR5K_PHY(9),
00433            { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e } },
00434         { AR5K_PHY(10),
00435            { 0x0a020001, 0x0a020001, 0x05010000, 0x0a020001 } },
00436         { AR5K_PHY(13),
00437            { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
00438         { AR5K_PHY(14),
00439            { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b } },
00440         { AR5K_PHY(17),
00441            { 0x1372169c, 0x137216a5, 0x137216a8, 0x1372169c } },
00442         { AR5K_PHY(18),
00443            { 0x0018ba67, 0x0018ba67, 0x0018ba69, 0x0018ba69 } },
00444         { AR5K_PHY(20),
00445            { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } },
00446         { AR5K_PHY_SIG,
00447            { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } },
00448         { AR5K_PHY_AGCCOARSE,
00449            { 0x31375d5e, 0x31375d5e, 0x313a5d5e, 0x31375d5e } },
00450         { AR5K_PHY_AGCCTL,
00451            { 0x0000bd10, 0x0000bd10, 0x0000bd38, 0x0000bd10 } },
00452         { AR5K_PHY_NF,
00453            { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
00454         { AR5K_PHY_RX_DELAY,
00455            { 0x00002710, 0x00002710, 0x0000157c, 0x00002710 } },
00456         { AR5K_PHY(70),
00457            { 0x00000190, 0x00000190, 0x00000084, 0x00000190 } },
00458         { AR5K_PHY_FRAME_CTL_5211,
00459            { 0x6fe01020, 0x6fe01020, 0x6fe00920, 0x6fe01020 } },
00460         { AR5K_PHY_PCDAC_TXPOWER_BASE,
00461            { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } },
00462         { AR5K_RF_BUFFER_CONTROL_4,
00463            { 0x00000010, 0x00000014, 0x00000010, 0x00000010 } },
00464 };
00465 
00466 /* Initial register settings for AR5212 */
00467 static const struct ath5k_ini ar5212_ini_common_start[] = {
00468         { AR5K_RXDP,            0x00000000 },
00469         { AR5K_RXCFG,           0x00000005 },
00470         { AR5K_MIBC,            0x00000000 },
00471         { AR5K_TOPS,            0x00000008 },
00472         { AR5K_RXNOFRM,         0x00000008 },
00473         { AR5K_TXNOFRM,         0x00000010 },
00474         { AR5K_RPGTO,           0x00000000 },
00475         { AR5K_RFCNT,           0x0000001f },
00476         { AR5K_QUEUE_TXDP(0),   0x00000000 },
00477         { AR5K_QUEUE_TXDP(1),   0x00000000 },
00478         { AR5K_QUEUE_TXDP(2),   0x00000000 },
00479         { AR5K_QUEUE_TXDP(3),   0x00000000 },
00480         { AR5K_QUEUE_TXDP(4),   0x00000000 },
00481         { AR5K_QUEUE_TXDP(5),   0x00000000 },
00482         { AR5K_QUEUE_TXDP(6),   0x00000000 },
00483         { AR5K_QUEUE_TXDP(7),   0x00000000 },
00484         { AR5K_QUEUE_TXDP(8),   0x00000000 },
00485         { AR5K_QUEUE_TXDP(9),   0x00000000 },
00486         { AR5K_DCU_FP,          0x00000000 },
00487         { AR5K_DCU_TXP,         0x00000000 },
00488         /* Tx filter table 0 (32 entries) */
00489         { AR5K_DCU_TX_FILTER_0(0),  0x00000000 }, /* DCU 0 */
00490         { AR5K_DCU_TX_FILTER_0(1),  0x00000000 },
00491         { AR5K_DCU_TX_FILTER_0(2),  0x00000000 },
00492         { AR5K_DCU_TX_FILTER_0(3),  0x00000000 },
00493         { AR5K_DCU_TX_FILTER_0(4),  0x00000000 }, /* DCU 1 */
00494         { AR5K_DCU_TX_FILTER_0(5),  0x00000000 },
00495         { AR5K_DCU_TX_FILTER_0(6),  0x00000000 },
00496         { AR5K_DCU_TX_FILTER_0(7),  0x00000000 },
00497         { AR5K_DCU_TX_FILTER_0(8),  0x00000000 }, /* DCU 2 */
00498         { AR5K_DCU_TX_FILTER_0(9),  0x00000000 },
00499         { AR5K_DCU_TX_FILTER_0(10), 0x00000000 },
00500         { AR5K_DCU_TX_FILTER_0(11), 0x00000000 },
00501         { AR5K_DCU_TX_FILTER_0(12), 0x00000000 }, /* DCU 3 */
00502         { AR5K_DCU_TX_FILTER_0(13), 0x00000000 },
00503         { AR5K_DCU_TX_FILTER_0(14), 0x00000000 },
00504         { AR5K_DCU_TX_FILTER_0(15), 0x00000000 },
00505         { AR5K_DCU_TX_FILTER_0(16), 0x00000000 }, /* DCU 4 */
00506         { AR5K_DCU_TX_FILTER_0(17), 0x00000000 },
00507         { AR5K_DCU_TX_FILTER_0(18), 0x00000000 },
00508         { AR5K_DCU_TX_FILTER_0(19), 0x00000000 },
00509         { AR5K_DCU_TX_FILTER_0(20), 0x00000000 }, /* DCU 5 */
00510         { AR5K_DCU_TX_FILTER_0(21), 0x00000000 },
00511         { AR5K_DCU_TX_FILTER_0(22), 0x00000000 },
00512         { AR5K_DCU_TX_FILTER_0(23), 0x00000000 },
00513         { AR5K_DCU_TX_FILTER_0(24), 0x00000000 }, /* DCU 6 */
00514         { AR5K_DCU_TX_FILTER_0(25), 0x00000000 },
00515         { AR5K_DCU_TX_FILTER_0(26), 0x00000000 },
00516         { AR5K_DCU_TX_FILTER_0(27), 0x00000000 },
00517         { AR5K_DCU_TX_FILTER_0(28), 0x00000000 }, /* DCU 7 */
00518         { AR5K_DCU_TX_FILTER_0(29), 0x00000000 },
00519         { AR5K_DCU_TX_FILTER_0(30), 0x00000000 },
00520         { AR5K_DCU_TX_FILTER_0(31), 0x00000000 },
00521         /* Tx filter table 1 (16 entries) */
00522         { AR5K_DCU_TX_FILTER_1(0),  0x00000000 },
00523         { AR5K_DCU_TX_FILTER_1(1),  0x00000000 },
00524         { AR5K_DCU_TX_FILTER_1(2),  0x00000000 },
00525         { AR5K_DCU_TX_FILTER_1(3),  0x00000000 },
00526         { AR5K_DCU_TX_FILTER_1(4),  0x00000000 },
00527         { AR5K_DCU_TX_FILTER_1(5),  0x00000000 },
00528         { AR5K_DCU_TX_FILTER_1(6),  0x00000000 },
00529         { AR5K_DCU_TX_FILTER_1(7),  0x00000000 },
00530         { AR5K_DCU_TX_FILTER_1(8),  0x00000000 },
00531         { AR5K_DCU_TX_FILTER_1(9),  0x00000000 },
00532         { AR5K_DCU_TX_FILTER_1(10), 0x00000000 },
00533         { AR5K_DCU_TX_FILTER_1(11), 0x00000000 },
00534         { AR5K_DCU_TX_FILTER_1(12), 0x00000000 },
00535         { AR5K_DCU_TX_FILTER_1(13), 0x00000000 },
00536         { AR5K_DCU_TX_FILTER_1(14), 0x00000000 },
00537         { AR5K_DCU_TX_FILTER_1(15), 0x00000000 },
00538         { AR5K_DCU_TX_FILTER_CLR, 0x00000000 },
00539         { AR5K_DCU_TX_FILTER_SET, 0x00000000 },
00540         { AR5K_STA_ID1,         0x00000000 },
00541         { AR5K_BSS_ID0,         0x00000000 },
00542         { AR5K_BSS_ID1,         0x00000000 },
00543         { AR5K_BEACON_5211,     0x00000000 },
00544         { AR5K_CFP_PERIOD_5211, 0x00000000 },
00545         { AR5K_TIMER0_5211,     0x00000030 },
00546         { AR5K_TIMER1_5211,     0x0007ffff },
00547         { AR5K_TIMER2_5211,     0x01ffffff },
00548         { AR5K_TIMER3_5211,     0x00000031 },
00549         { AR5K_CFP_DUR_5211,    0x00000000 },
00550         { AR5K_RX_FILTER_5211,  0x00000000 },
00551         { AR5K_DIAG_SW_5211,    0x00000000 },
00552         { AR5K_ADDAC_TEST,      0x00000000 },
00553         { AR5K_DEFAULT_ANTENNA, 0x00000000 },
00554         { AR5K_FRAME_CTL_QOSM,  0x000fc78f },
00555         { AR5K_XRMODE,          0x2a82301a },
00556         { AR5K_XRDELAY,         0x05dc01e0 },
00557         { AR5K_XRTIMEOUT,       0x1f402710 },
00558         { AR5K_XRCHIRP,         0x01f40000 },
00559         { AR5K_XRSTOMP,         0x00001e1c },
00560         { AR5K_SLEEP0,          0x0002aaaa },
00561         { AR5K_SLEEP1,          0x02005555 },
00562         { AR5K_SLEEP2,          0x00000000 },
00563         { AR5K_BSS_IDM0,        0xffffffff },
00564         { AR5K_BSS_IDM1,        0x0000ffff },
00565         { AR5K_TXPC,            0x00000000 },
00566         { AR5K_PROFCNT_TX,      0x00000000 },
00567         { AR5K_PROFCNT_RX,      0x00000000 },
00568         { AR5K_PROFCNT_RXCLR,   0x00000000 },
00569         { AR5K_PROFCNT_CYCLE,   0x00000000 },
00570         { AR5K_QUIET_CTL1,      0x00000088 },
00571         /* Initial rate duration table (32 entries )*/
00572         { AR5K_RATE_DUR(0),     0x00000000 },
00573         { AR5K_RATE_DUR(1),     0x0000008c },
00574         { AR5K_RATE_DUR(2),     0x000000e4 },
00575         { AR5K_RATE_DUR(3),     0x000002d5 },
00576         { AR5K_RATE_DUR(4),     0x00000000 },
00577         { AR5K_RATE_DUR(5),     0x00000000 },
00578         { AR5K_RATE_DUR(6),     0x000000a0 },
00579         { AR5K_RATE_DUR(7),     0x000001c9 },
00580         { AR5K_RATE_DUR(8),     0x0000002c },
00581         { AR5K_RATE_DUR(9),     0x0000002c },
00582         { AR5K_RATE_DUR(10),    0x00000030 },
00583         { AR5K_RATE_DUR(11),    0x0000003c },
00584         { AR5K_RATE_DUR(12),    0x0000002c },
00585         { AR5K_RATE_DUR(13),    0x0000002c },
00586         { AR5K_RATE_DUR(14),    0x00000030 },
00587         { AR5K_RATE_DUR(15),    0x0000003c },
00588         { AR5K_RATE_DUR(16),    0x00000000 },
00589         { AR5K_RATE_DUR(17),    0x00000000 },
00590         { AR5K_RATE_DUR(18),    0x00000000 },
00591         { AR5K_RATE_DUR(19),    0x00000000 },
00592         { AR5K_RATE_DUR(20),    0x00000000 },
00593         { AR5K_RATE_DUR(21),    0x00000000 },
00594         { AR5K_RATE_DUR(22),    0x00000000 },
00595         { AR5K_RATE_DUR(23),    0x00000000 },
00596         { AR5K_RATE_DUR(24),    0x000000d5 },
00597         { AR5K_RATE_DUR(25),    0x000000df },
00598         { AR5K_RATE_DUR(26),    0x00000102 },
00599         { AR5K_RATE_DUR(27),    0x0000013a },
00600         { AR5K_RATE_DUR(28),    0x00000075 },
00601         { AR5K_RATE_DUR(29),    0x0000007f },
00602         { AR5K_RATE_DUR(30),    0x000000a2 },
00603         { AR5K_RATE_DUR(31),    0x00000000 },
00604         { AR5K_QUIET_CTL2,      0x00010002 },
00605         { AR5K_TSF_PARM,        0x00000001 },
00606         { AR5K_QOS_NOACK,       0x000000c0 },
00607         { AR5K_PHY_ERR_FIL,     0x00000000 },
00608         { AR5K_XRLAT_TX,        0x00000168 },
00609         { AR5K_ACKSIFS,         0x00000000 },
00610         /* Rate -> db table
00611          * notice ...03<-02<-01<-00 ! */
00612         { AR5K_RATE2DB(0),      0x03020100 },
00613         { AR5K_RATE2DB(1),      0x07060504 },
00614         { AR5K_RATE2DB(2),      0x0b0a0908 },
00615         { AR5K_RATE2DB(3),      0x0f0e0d0c },
00616         { AR5K_RATE2DB(4),      0x13121110 },
00617         { AR5K_RATE2DB(5),      0x17161514 },
00618         { AR5K_RATE2DB(6),      0x1b1a1918 },
00619         { AR5K_RATE2DB(7),      0x1f1e1d1c },
00620         /* Db -> Rate table */
00621         { AR5K_DB2RATE(0),      0x03020100 },
00622         { AR5K_DB2RATE(1),      0x07060504 },
00623         { AR5K_DB2RATE(2),      0x0b0a0908 },
00624         { AR5K_DB2RATE(3),      0x0f0e0d0c },
00625         { AR5K_DB2RATE(4),      0x13121110 },
00626         { AR5K_DB2RATE(5),      0x17161514 },
00627         { AR5K_DB2RATE(6),      0x1b1a1918 },
00628         { AR5K_DB2RATE(7),      0x1f1e1d1c },
00629         /* PHY registers (Common settings
00630          * for all chips/modes) */
00631         { AR5K_PHY(3),          0xad848e19 },
00632         { AR5K_PHY(4),          0x7d28e000 },
00633         { AR5K_PHY_TIMING_3,    0x9c0a9f6b },
00634         { AR5K_PHY_ACT,         0x00000000 },
00635         { AR5K_PHY(16),         0x206a017a },
00636         { AR5K_PHY(21),         0x00000859 },
00637         { AR5K_PHY_BIN_MASK_1,  0x00000000 },
00638         { AR5K_PHY_BIN_MASK_2,  0x00000000 },
00639         { AR5K_PHY_BIN_MASK_3,  0x00000000 },
00640         { AR5K_PHY_BIN_MASK_CTL, 0x00800000 },
00641         { AR5K_PHY_ANT_CTL,     0x00000001 },
00642         /*{ AR5K_PHY(71), 0x0000092a },*/ /* Old value */
00643         { AR5K_PHY_MAX_RX_LEN,  0x00000c80 },
00644         { AR5K_PHY_IQ,          0x05100000 },
00645         { AR5K_PHY_WARM_RESET,  0x00000001 },
00646         { AR5K_PHY_CTL,         0x00000004 },
00647         { AR5K_PHY_TXPOWER_RATE1, 0x1e1f2022 },
00648         { AR5K_PHY_TXPOWER_RATE2, 0x0a0b0c0d },
00649         { AR5K_PHY_TXPOWER_RATE_MAX, 0x0000003f },
00650         { AR5K_PHY(82),         0x9280b212 },
00651         { AR5K_PHY_RADAR,       0x5d50e188 },
00652         /*{ AR5K_PHY(86), 0x000000ff },*/
00653         { AR5K_PHY(87),         0x004b6a8e },
00654         { AR5K_PHY_NFTHRES,     0x000003ce },
00655         { AR5K_PHY_RESTART,     0x192fb515 },
00656         { AR5K_PHY(94),         0x00000001 },
00657         { AR5K_PHY_RFBUS_REQ,   0x00000000 },
00658         /*{ AR5K_PHY(644), 0x0080a333 },*/ /* Old value */
00659         /*{ AR5K_PHY(645), 0x00206c10 },*/ /* Old value */
00660         { AR5K_PHY(644),        0x00806333 },
00661         { AR5K_PHY(645),        0x00106c10 },
00662         { AR5K_PHY(646),        0x009c4060 },
00663         /* { AR5K_PHY(647), 0x1483800a }, */
00664         /* { AR5K_PHY(648), 0x01831061 }, */ /* Old value */
00665         { AR5K_PHY(648),        0x018830c6 },
00666         { AR5K_PHY(649),        0x00000400 },
00667         /*{ AR5K_PHY(650), 0x000001b5 },*/
00668         { AR5K_PHY(651),        0x00000000 },
00669         { AR5K_PHY_TXPOWER_RATE3, 0x20202020 },
00670         { AR5K_PHY_TXPOWER_RATE4, 0x20202020 },
00671         /*{ AR5K_PHY(655), 0x13c889af },*/
00672         { AR5K_PHY(656),        0x38490a20 },
00673         { AR5K_PHY(657),        0x00007bb6 },
00674         { AR5K_PHY(658),        0x0fff3ffc },
00675 };
00676 
00677 /* Initial mode-specific settings for AR5212 (Written before ar5212_ini) */
00678 static const struct ath5k_ini_mode ar5212_ini_mode_start[] = {
00679         { AR5K_QUEUE_DFS_LOCAL_IFS(0),
00680         /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
00681            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00682         { AR5K_QUEUE_DFS_LOCAL_IFS(1),
00683            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00684         { AR5K_QUEUE_DFS_LOCAL_IFS(2),
00685            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00686         { AR5K_QUEUE_DFS_LOCAL_IFS(3),
00687            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00688         { AR5K_QUEUE_DFS_LOCAL_IFS(4),
00689            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00690         { AR5K_QUEUE_DFS_LOCAL_IFS(5),
00691            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00692         { AR5K_QUEUE_DFS_LOCAL_IFS(6),
00693            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00694         { AR5K_QUEUE_DFS_LOCAL_IFS(7),
00695            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00696         { AR5K_QUEUE_DFS_LOCAL_IFS(8),
00697            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00698         { AR5K_QUEUE_DFS_LOCAL_IFS(9),
00699            { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00700         { AR5K_DCU_GBL_IFS_SIFS,
00701            { 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 } },
00702         { AR5K_DCU_GBL_IFS_SLOT,
00703            { 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } },
00704         { AR5K_DCU_GBL_IFS_EIFS,
00705            { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 } },
00706         { AR5K_DCU_GBL_IFS_MISC,
00707            { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 } },
00708         { AR5K_TIME_OUT,
00709            { 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 } },
00710         { AR5K_PHY_TURBO,
00711            { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } },
00712         { AR5K_PHY(8),
00713            { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } },
00714         { AR5K_PHY_RF_CTL2,
00715            { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e } },
00716         { AR5K_PHY_SETTLING,
00717            { 0x1372161c, 0x13721c25, 0x13721722, 0x137216a2, 0x13721c25 } },
00718         { AR5K_PHY_AGCCTL,
00719            { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d18, 0x00009d10 } },
00720         { AR5K_PHY_NF,
00721            { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
00722         { AR5K_PHY_WEAK_OFDM_HIGH_THR,
00723            { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } },
00724         { AR5K_PHY(70),
00725            { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } },
00726         { AR5K_PHY_OFDM_SELFCORR,
00727            { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } },
00728         { 0xa230,
00729            { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } },
00730 };
00731 
00732 /* Initial mode-specific settings for AR5212 + RF5111 (Written after ar5212_ini) */
00733 static const struct ath5k_ini_mode rf5111_ini_mode_end[] = {
00734         { AR5K_TXCFG,
00735         /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
00736            { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
00737         { AR5K_USEC_5211,
00738            { 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x12e00fab, 0x09880fcf } },
00739         { AR5K_PHY_RF_CTL3,
00740            { 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 } },
00741         { AR5K_PHY_RF_CTL4,
00742            { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
00743         { AR5K_PHY_PA_CTL,
00744            { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
00745         { AR5K_PHY_GAIN,
00746            { 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 } },
00747         { AR5K_PHY_DESIRED_SIZE,
00748            { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
00749         { AR5K_PHY_SIG,
00750            { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } },
00751         { AR5K_PHY_AGCCOARSE,
00752            { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e } },
00753         { AR5K_PHY_WEAK_OFDM_LOW_THR,
00754            { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 } },
00755         { AR5K_PHY_RX_DELAY,
00756            { 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 } },
00757         { AR5K_PHY_FRAME_CTL_5211,
00758            { 0xf7b81020, 0xf7b81020, 0xf7b80d20, 0xf7b81020, 0xf7b81020 } },
00759         { AR5K_PHY_GAIN_2GHZ,
00760            { 0x642c416a, 0x642c416a, 0x6440416a, 0x6440416a, 0x6440416a } },
00761         { AR5K_PHY_CCK_RX_CTL_4,
00762            { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
00763 };
00764 
00765 static const struct ath5k_ini rf5111_ini_common_end[] = {
00766         { AR5K_DCU_FP,          0x00000000 },
00767         { AR5K_PHY_AGC,         0x00000000 },
00768         { AR5K_PHY_ADC_CTL,     0x00022ffe },
00769         { 0x983c,               0x00020100 },
00770         { AR5K_PHY_GAIN_OFFSET, 0x1284613c },
00771         { AR5K_PHY_PAPD_PROBE,  0x00004883 },
00772         { 0x9940,               0x00000004 },
00773         { 0x9958,               0x000000ff },
00774         { 0x9974,               0x00000000 },
00775         { AR5K_PHY_SPENDING,    0x00000018 },
00776         { AR5K_PHY_CCKTXCTL,    0x00000000 },
00777         { AR5K_PHY_CCK_CROSSCORR, 0xd03e6788 },
00778         { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 },
00779         { 0xa23c,               0x13c889af },
00780 };
00781 
00782 /* Initial mode-specific settings for AR5212 + RF5112 (Written after ar5212_ini) */
00783 static const struct ath5k_ini_mode rf5112_ini_mode_end[] = {
00784         { AR5K_TXCFG,
00785         /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
00786            { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
00787         { AR5K_USEC_5211,
00788            { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
00789         { AR5K_PHY_RF_CTL3,
00790            { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
00791         { AR5K_PHY_RF_CTL4,
00792            { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
00793         { AR5K_PHY_PA_CTL,
00794            { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
00795         { AR5K_PHY_GAIN,
00796            { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 } },
00797         { AR5K_PHY_DESIRED_SIZE,
00798            { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
00799         { AR5K_PHY_SIG,
00800            { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e, 0x7e800d2e } },
00801         { AR5K_PHY_AGCCOARSE,
00802            { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } },
00803         { AR5K_PHY_WEAK_OFDM_LOW_THR,
00804            { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
00805         { AR5K_PHY_RX_DELAY,
00806            { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
00807         { AR5K_PHY_FRAME_CTL_5211,
00808            { 0xf7b81020, 0xf7b81020, 0xf7b80d10, 0xf7b81010, 0xf7b81010 } },
00809         { AR5K_PHY_CCKTXCTL,
00810            { 0x00000000, 0x00000000, 0x00000008, 0x00000008, 0x00000008 } },
00811         { AR5K_PHY_CCK_CROSSCORR,
00812            { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
00813         { AR5K_PHY_GAIN_2GHZ,
00814            { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 } },
00815         { AR5K_PHY_CCK_RX_CTL_4,
00816            { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
00817 };
00818 
00819 static const struct ath5k_ini rf5112_ini_common_end[] = {
00820         { AR5K_DCU_FP,          0x00000000 },
00821         { AR5K_PHY_AGC,         0x00000000 },
00822         { AR5K_PHY_ADC_CTL,     0x00022ffe },
00823         { 0x983c,               0x00020100 },
00824         { AR5K_PHY_GAIN_OFFSET, 0x1284613c },
00825         { AR5K_PHY_PAPD_PROBE,  0x00004882 },
00826         { 0x9940,               0x00000004 },
00827         { 0x9958,               0x000000ff },
00828         { 0x9974,               0x00000000 },
00829         { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 },
00830         { 0xa23c,               0x13c889af },
00831 };
00832 
00833 /* Initial mode-specific settings for RF5413/5414 (Written after ar5212_ini) */
00834 static const struct ath5k_ini_mode rf5413_ini_mode_end[] = {
00835         { AR5K_TXCFG,
00836         /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
00837            { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
00838         { AR5K_USEC_5211,
00839            { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
00840         { AR5K_PHY_RF_CTL3,
00841            { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
00842         { AR5K_PHY_RF_CTL4,
00843            { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
00844         { AR5K_PHY_PA_CTL,
00845            { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
00846         { AR5K_PHY_GAIN,
00847            { 0x0018fa61, 0x0018fa61, 0x001a1a63, 0x001a1a63, 0x001a1a63 } },
00848         { AR5K_PHY_DESIRED_SIZE,
00849            { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
00850         { AR5K_PHY_SIG,
00851            { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
00852         { AR5K_PHY_AGCCOARSE,
00853            { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
00854         { AR5K_PHY_WEAK_OFDM_LOW_THR,
00855            { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
00856         { AR5K_PHY_RX_DELAY,
00857            { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
00858         { AR5K_PHY_FRAME_CTL_5211,
00859            { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
00860         { AR5K_PHY_CCKTXCTL,
00861            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
00862         { AR5K_PHY_CCK_CROSSCORR,
00863            { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
00864         { AR5K_PHY_GAIN_2GHZ,
00865            { 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 } },
00866         { AR5K_PHY_CCK_RX_CTL_4,
00867            { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
00868         { 0xa300,
00869            { 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 } },
00870         { 0xa304,
00871            { 0x30032602, 0x30032602, 0x30032602, 0x30032602, 0x30032602 } },
00872         { 0xa308,
00873            { 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06 } },
00874         { 0xa30c,
00875            { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } },
00876         { 0xa310,
00877            { 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f } },
00878         { 0xa314,
00879            { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } },
00880         { 0xa318,
00881            { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } },
00882         { 0xa31c,
00883            { 0x90cf865b, 0x90cf865b, 0x8ecf865b, 0x8ecf865b, 0x8ecf865b } },
00884         { 0xa320,
00885            { 0x9d4f970f, 0x9d4f970f, 0x9b4f970f, 0x9b4f970f, 0x9b4f970f } },
00886         { 0xa324,
00887            { 0xa7cfa38f, 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f, 0xa3cf9f8f } },
00888         { 0xa328,
00889            { 0xb55faf1f, 0xb55faf1f, 0xb35faf1f, 0xb35faf1f, 0xb35faf1f } },
00890         { 0xa32c,
00891            { 0xbddfb99f, 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f, 0xbbdfb99f } },
00892         { 0xa330,
00893            { 0xcb7fc53f, 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f, 0xcb7fc73f } },
00894         { 0xa334,
00895            { 0xd5ffd1bf, 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf } },
00896 };
00897 
00898 static const struct ath5k_ini rf5413_ini_common_end[] = {
00899         { AR5K_DCU_FP,          0x000003e0 },
00900         { AR5K_5414_CBCFG,      0x00000010 },
00901         { AR5K_SEQ_MASK,        0x0000000f },
00902         { 0x809c,               0x00000000 },
00903         { 0x80a0,               0x00000000 },
00904         { AR5K_MIC_QOS_CTL,     0x00000000 },
00905         { AR5K_MIC_QOS_SEL,     0x00000000 },
00906         { AR5K_MISC_MODE,       0x00000000 },
00907         { AR5K_OFDM_FIL_CNT,    0x00000000 },
00908         { AR5K_CCK_FIL_CNT,     0x00000000 },
00909         { AR5K_PHYERR_CNT1,     0x00000000 },
00910         { AR5K_PHYERR_CNT1_MASK, 0x00000000 },
00911         { AR5K_PHYERR_CNT2,     0x00000000 },
00912         { AR5K_PHYERR_CNT2_MASK, 0x00000000 },
00913         { AR5K_TSF_THRES,       0x00000000 },
00914         { 0x8140,               0x800003f9 },
00915         { 0x8144,               0x00000000 },
00916         { AR5K_PHY_AGC,         0x00000000 },
00917         { AR5K_PHY_ADC_CTL,     0x0000a000 },
00918         { 0x983c,               0x00200400 },
00919         { AR5K_PHY_GAIN_OFFSET, 0x1284233c },
00920         { AR5K_PHY_SCR,         0x0000001f },
00921         { AR5K_PHY_SLMT,        0x00000080 },
00922         { AR5K_PHY_SCAL,        0x0000000e },
00923         { 0x9958,               0x00081fff },
00924         { AR5K_PHY_TIMING_7,    0x00000000 },
00925         { AR5K_PHY_TIMING_8,    0x02800000 },
00926         { AR5K_PHY_TIMING_11,   0x00000000 },
00927         { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 },
00928         { 0x99e4,               0xaaaaaaaa },
00929         { 0x99e8,               0x3c466478 },
00930         { 0x99ec,               0x000000aa },
00931         { AR5K_PHY_SCLOCK,      0x0000000c },
00932         { AR5K_PHY_SDELAY,      0x000000ff },
00933         { AR5K_PHY_SPENDING,    0x00000014 },
00934         { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 },
00935         { 0xa23c,               0x93c889af },
00936         { AR5K_PHY_FAST_ADC,    0x00000001 },
00937         { 0xa250,               0x0000a000 },
00938         { AR5K_PHY_BLUETOOTH,   0x00000000 },
00939         { AR5K_PHY_TPC_RG1,     0x0cc75380 },
00940         { 0xa25c,               0x0f0f0f01 },
00941         { 0xa260,               0x5f690f01 },
00942         { 0xa264,               0x00418a11 },
00943         { 0xa268,               0x00000000 },
00944         { AR5K_PHY_TPC_RG5,     0x0c30c16a },
00945         { 0xa270, 0x00820820 },
00946         { 0xa274, 0x081b7caa },
00947         { 0xa278, 0x1ce739ce },
00948         { 0xa27c, 0x051701ce },
00949         { 0xa338, 0x00000000 },
00950         { 0xa33c, 0x00000000 },
00951         { 0xa340, 0x00000000 },
00952         { 0xa344, 0x00000000 },
00953         { 0xa348, 0x3fffffff },
00954         { 0xa34c, 0x3fffffff },
00955         { 0xa350, 0x3fffffff },
00956         { 0xa354, 0x0003ffff },
00957         { 0xa358, 0x79a8aa1f },
00958         { 0xa35c, 0x066c420f },
00959         { 0xa360, 0x0f282207 },
00960         { 0xa364, 0x17601685 },
00961         { 0xa368, 0x1f801104 },
00962         { 0xa36c, 0x37a00c03 },
00963         { 0xa370, 0x3fc40883 },
00964         { 0xa374, 0x57c00803 },
00965         { 0xa378, 0x5fd80682 },
00966         { 0xa37c, 0x7fe00482 },
00967         { 0xa380, 0x7f3c7bba },
00968         { 0xa384, 0xf3307ff0 },
00969 };
00970 
00971 /* Initial mode-specific settings for RF2413/2414 (Written after ar5212_ini) */
00972 /* XXX: a mode ? */
00973 static const struct ath5k_ini_mode rf2413_ini_mode_end[] = {
00974         { AR5K_TXCFG,
00975         /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
00976            { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
00977         { AR5K_USEC_5211,
00978            { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
00979         { AR5K_PHY_RF_CTL3,
00980            { 0x0a020001, 0x0a020001, 0x05020000, 0x0a020001, 0x0a020001 } },
00981         { AR5K_PHY_RF_CTL4,
00982            { 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00 } },
00983         { AR5K_PHY_PA_CTL,
00984            { 0x00000002, 0x00000002, 0x0000000a, 0x0000000a, 0x0000000a } },
00985         { AR5K_PHY_GAIN,
00986            { 0x0018da6d, 0x0018da6d, 0x001a6a64, 0x001a6a64, 0x001a6a64 } },
00987         { AR5K_PHY_DESIRED_SIZE,
00988            { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b0da, 0x0c98b0da, 0x0de8b0da } },
00989         { AR5K_PHY_SIG,
00990            { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ec80d2e, 0x7e800d2e } },
00991         { AR5K_PHY_AGCCOARSE,
00992            { 0x3137665e, 0x3137665e, 0x3137665e, 0x3139605e, 0x3137665e } },
00993         { AR5K_PHY_WEAK_OFDM_LOW_THR,
00994            { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
00995         { AR5K_PHY_RX_DELAY,
00996            { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
00997         { AR5K_PHY_FRAME_CTL_5211,
00998            { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
00999         { AR5K_PHY_CCKTXCTL,
01000            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
01001         { AR5K_PHY_CCK_CROSSCORR,
01002            { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
01003         { AR5K_PHY_GAIN_2GHZ,
01004            { 0x002c0140, 0x002c0140, 0x0042c140, 0x0042c140, 0x0042c140 } },
01005         { AR5K_PHY_CCK_RX_CTL_4,
01006            { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
01007 };
01008 
01009 static const struct ath5k_ini rf2413_ini_common_end[] = {
01010         { AR5K_DCU_FP,          0x000003e0 },
01011         { AR5K_SEQ_MASK,        0x0000000f },
01012         { AR5K_MIC_QOS_CTL,     0x00000000 },
01013         { AR5K_MIC_QOS_SEL,     0x00000000 },
01014         { AR5K_MISC_MODE,       0x00000000 },
01015         { AR5K_OFDM_FIL_CNT,    0x00000000 },
01016         { AR5K_CCK_FIL_CNT,     0x00000000 },
01017         { AR5K_PHYERR_CNT1,     0x00000000 },
01018         { AR5K_PHYERR_CNT1_MASK, 0x00000000 },
01019         { AR5K_PHYERR_CNT2,     0x00000000 },
01020         { AR5K_PHYERR_CNT2_MASK, 0x00000000 },
01021         { AR5K_TSF_THRES,       0x00000000 },
01022         { 0x8140,               0x800000a8 },
01023         { 0x8144,               0x00000000 },
01024         { AR5K_PHY_AGC,         0x00000000 },
01025         { AR5K_PHY_ADC_CTL,     0x0000a000 },
01026         { 0x983c,               0x00200400 },
01027         { AR5K_PHY_GAIN_OFFSET, 0x1284233c },
01028         { AR5K_PHY_SCR,         0x0000001f },
01029         { AR5K_PHY_SLMT,        0x00000080 },
01030         { AR5K_PHY_SCAL,        0x0000000e },
01031         { 0x9958,               0x000000ff },
01032         { AR5K_PHY_TIMING_7,    0x00000000 },
01033         { AR5K_PHY_TIMING_8,    0x02800000 },
01034         { AR5K_PHY_TIMING_11,   0x00000000 },
01035         { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 },
01036         { 0x99e4,               0xaaaaaaaa },
01037         { 0x99e8,               0x3c466478 },
01038         { 0x99ec,               0x000000aa },
01039         { AR5K_PHY_SCLOCK,      0x0000000c },
01040         { AR5K_PHY_SDELAY,      0x000000ff },
01041         { AR5K_PHY_SPENDING,    0x00000014 },
01042         { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 },
01043         { 0xa23c,               0x93c889af },
01044         { AR5K_PHY_FAST_ADC,    0x00000001 },
01045         { 0xa250,               0x0000a000 },
01046         { AR5K_PHY_BLUETOOTH,   0x00000000 },
01047         { AR5K_PHY_TPC_RG1,     0x0cc75380 },
01048         { 0xa25c,               0x0f0f0f01 },
01049         { 0xa260,               0x5f690f01 },
01050         { 0xa264,               0x00418a11 },
01051         { 0xa268,               0x00000000 },
01052         { AR5K_PHY_TPC_RG5,     0x0c30c16a },
01053         { 0xa270, 0x00820820 },
01054         { 0xa274, 0x001b7caa },
01055         { 0xa278, 0x1ce739ce },
01056         { 0xa27c, 0x051701ce },
01057         { 0xa300, 0x18010000 },
01058         { 0xa304, 0x30032602 },
01059         { 0xa308, 0x48073e06 },
01060         { 0xa30c, 0x560b4c0a },
01061         { 0xa310, 0x641a600f },
01062         { 0xa314, 0x784f6e1b },
01063         { 0xa318, 0x868f7c5a },
01064         { 0xa31c, 0x8ecf865b },
01065         { 0xa320, 0x9d4f970f },
01066         { 0xa324, 0xa5cfa18f },
01067         { 0xa328, 0xb55faf1f },
01068         { 0xa32c, 0xbddfb99f },
01069         { 0xa330, 0xcd7fc73f },
01070         { 0xa334, 0xd5ffd1bf },
01071         { 0xa338, 0x00000000 },
01072         { 0xa33c, 0x00000000 },
01073         { 0xa340, 0x00000000 },
01074         { 0xa344, 0x00000000 },
01075         { 0xa348, 0x3fffffff },
01076         { 0xa34c, 0x3fffffff },
01077         { 0xa350, 0x3fffffff },
01078         { 0xa354, 0x0003ffff },
01079         { 0xa358, 0x79a8aa1f },
01080         { 0xa35c, 0x066c420f },
01081         { 0xa360, 0x0f282207 },
01082         { 0xa364, 0x17601685 },
01083         { 0xa368, 0x1f801104 },
01084         { 0xa36c, 0x37a00c03 },
01085         { 0xa370, 0x3fc40883 },
01086         { 0xa374, 0x57c00803 },
01087         { 0xa378, 0x5fd80682 },
01088         { 0xa37c, 0x7fe00482 },
01089         { 0xa380, 0x7f3c7bba },
01090         { 0xa384, 0xf3307ff0 },
01091 };
01092 
01093 /* Initial mode-specific settings for RF2425 (Written after ar5212_ini) */
01094 /* XXX: a mode ? */
01095 static const struct ath5k_ini_mode rf2425_ini_mode_end[] = {
01096         { AR5K_TXCFG,
01097         /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
01098            { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
01099         { AR5K_USEC_5211,
01100            { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
01101         { AR5K_PHY_TURBO,
01102            { 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000001 } },
01103         { AR5K_PHY_RF_CTL3,
01104            { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
01105         { AR5K_PHY_RF_CTL4,
01106            { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
01107         { AR5K_PHY_PA_CTL,
01108            { 0x00000003, 0x00000003, 0x0000000b, 0x0000000b, 0x0000000b } },
01109         { AR5K_PHY_SETTLING,
01110            { 0x1372161c, 0x13721c25, 0x13721722, 0x13721422, 0x13721c25 } },
01111         { AR5K_PHY_GAIN,
01112            { 0x0018fa61, 0x0018fa61, 0x00199a65, 0x00199a65, 0x00199a65 } },
01113         { AR5K_PHY_DESIRED_SIZE,
01114            { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
01115         { AR5K_PHY_SIG,
01116            { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
01117         { AR5K_PHY_AGCCOARSE,
01118            { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
01119         { AR5K_PHY_WEAK_OFDM_LOW_THR,
01120            { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
01121         { AR5K_PHY_RX_DELAY,
01122            { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
01123         { AR5K_PHY_FRAME_CTL_5211,
01124            { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
01125         { AR5K_PHY_CCKTXCTL,
01126            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
01127         { AR5K_PHY_CCK_CROSSCORR,
01128            { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
01129         { AR5K_PHY_GAIN_2GHZ,
01130            { 0x00000140, 0x00000140, 0x0052c140, 0x0052c140, 0x0052c140 } },
01131         { AR5K_PHY_CCK_RX_CTL_4,
01132            { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
01133         { 0xa324,
01134            { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
01135         { 0xa328,
01136            { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
01137         { 0xa32c,
01138            { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
01139         { 0xa330,
01140            { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
01141         { 0xa334,
01142            { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
01143 };
01144 
01145 static const struct ath5k_ini rf2425_ini_common_end[] = {
01146         { AR5K_DCU_FP,          0x000003e0 },
01147         { AR5K_SEQ_MASK,        0x0000000f },
01148         { 0x809c,               0x00000000 },
01149         { 0x80a0,               0x00000000 },
01150         { AR5K_MIC_QOS_CTL,     0x00000000 },
01151         { AR5K_MIC_QOS_SEL,     0x00000000 },
01152         { AR5K_MISC_MODE,       0x00000000 },
01153         { AR5K_OFDM_FIL_CNT,    0x00000000 },
01154         { AR5K_CCK_FIL_CNT,     0x00000000 },
01155         { AR5K_PHYERR_CNT1,     0x00000000 },
01156         { AR5K_PHYERR_CNT1_MASK, 0x00000000 },
01157         { AR5K_PHYERR_CNT2,     0x00000000 },
01158         { AR5K_PHYERR_CNT2_MASK, 0x00000000 },
01159         { AR5K_TSF_THRES,       0x00000000 },
01160         { 0x8140,               0x800003f9 },
01161         { 0x8144,               0x00000000 },
01162         { AR5K_PHY_AGC,         0x00000000 },
01163         { AR5K_PHY_ADC_CTL,     0x0000a000 },
01164         { 0x983c,               0x00200400 },
01165         { AR5K_PHY_GAIN_OFFSET, 0x1284233c },
01166         { AR5K_PHY_SCR,         0x0000001f },
01167         { AR5K_PHY_SLMT,        0x00000080 },
01168         { AR5K_PHY_SCAL,        0x0000000e },
01169         { 0x9958,               0x00081fff },
01170         { AR5K_PHY_TIMING_7,    0x00000000 },
01171         { AR5K_PHY_TIMING_8,    0x02800000 },
01172         { AR5K_PHY_TIMING_11,   0x00000000 },
01173         { 0x99dc,               0xfebadbe8 },
01174         { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 },
01175         { 0x99e4,               0xaaaaaaaa },
01176         { 0x99e8,               0x3c466478 },
01177         { 0x99ec,               0x000000aa },
01178         { AR5K_PHY_SCLOCK,      0x0000000c },
01179         { AR5K_PHY_SDELAY,      0x000000ff },
01180         { AR5K_PHY_SPENDING,    0x00000014 },
01181         { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 },
01182         { AR5K_PHY_TXPOWER_RATE3, 0x20202020 },
01183         { AR5K_PHY_TXPOWER_RATE4, 0x20202020 },
01184         { 0xa23c,               0x93c889af },
01185         { AR5K_PHY_FAST_ADC,    0x00000001 },
01186         { 0xa250,               0x0000a000 },
01187         { AR5K_PHY_BLUETOOTH,   0x00000000 },
01188         { AR5K_PHY_TPC_RG1,     0x0cc75380 },
01189         { 0xa25c,               0x0f0f0f01 },
01190         { 0xa260,               0x5f690f01 },
01191         { 0xa264,               0x00418a11 },
01192         { 0xa268,               0x00000000 },
01193         { AR5K_PHY_TPC_RG5,     0x0c30c166 },
01194         { 0xa270, 0x00820820 },
01195         { 0xa274, 0x081a3caa },
01196         { 0xa278, 0x1ce739ce },
01197         { 0xa27c, 0x051701ce },
01198         { 0xa300, 0x16010000 },
01199         { 0xa304, 0x2c032402 },
01200         { 0xa308, 0x48433e42 },
01201         { 0xa30c, 0x5a0f500b },
01202         { 0xa310, 0x6c4b624a },
01203         { 0xa314, 0x7e8b748a },
01204         { 0xa318, 0x96cf8ccb },
01205         { 0xa31c, 0xa34f9d0f },
01206         { 0xa320, 0xa7cfa58f },
01207         { 0xa348, 0x3fffffff },
01208         { 0xa34c, 0x3fffffff },
01209         { 0xa350, 0x3fffffff },
01210         { 0xa354, 0x0003ffff },
01211         { 0xa358, 0x79a8aa1f },
01212         { 0xa35c, 0x066c420f },
01213         { 0xa360, 0x0f282207 },
01214         { 0xa364, 0x17601685 },
01215         { 0xa368, 0x1f801104 },
01216         { 0xa36c, 0x37a00c03 },
01217         { 0xa370, 0x3fc40883 },
01218         { 0xa374, 0x57c00803 },
01219         { 0xa378, 0x5fd80682 },
01220         { 0xa37c, 0x7fe00482 },
01221         { 0xa380, 0x7f3c7bba },
01222         { 0xa384, 0xf3307ff0 },
01223 };
01224 
01225 /*
01226  * Initial BaseBand Gain settings for RF5111/5112 (AR5210 comes with
01227  * RF5110 only so initial BB Gain settings are included in AR5K_AR5210_INI)
01228  */
01229 
01230 /* RF5111 Initial BaseBand Gain settings */
01231 static const struct ath5k_ini rf5111_ini_bbgain[] = {
01232         { AR5K_BB_GAIN(0), 0x00000000 },
01233         { AR5K_BB_GAIN(1), 0x00000020 },
01234         { AR5K_BB_GAIN(2), 0x00000010 },
01235         { AR5K_BB_GAIN(3), 0x00000030 },
01236         { AR5K_BB_GAIN(4), 0x00000008 },
01237         { AR5K_BB_GAIN(5), 0x00000028 },
01238         { AR5K_BB_GAIN(6), 0x00000004 },
01239         { AR5K_BB_GAIN(7), 0x00000024 },
01240         { AR5K_BB_GAIN(8), 0x00000014 },
01241         { AR5K_BB_GAIN(9), 0x00000034 },
01242         { AR5K_BB_GAIN(10), 0x0000000c },
01243         { AR5K_BB_GAIN(11), 0x0000002c },
01244         { AR5K_BB_GAIN(12), 0x00000002 },
01245         { AR5K_BB_GAIN(13), 0x00000022 },
01246         { AR5K_BB_GAIN(14), 0x00000012 },
01247         { AR5K_BB_GAIN(15), 0x00000032 },
01248         { AR5K_BB_GAIN(16), 0x0000000a },
01249         { AR5K_BB_GAIN(17), 0x0000002a },
01250         { AR5K_BB_GAIN(18), 0x00000006 },
01251         { AR5K_BB_GAIN(19), 0x00000026 },
01252         { AR5K_BB_GAIN(20), 0x00000016 },
01253         { AR5K_BB_GAIN(21), 0x00000036 },
01254         { AR5K_BB_GAIN(22), 0x0000000e },
01255         { AR5K_BB_GAIN(23), 0x0000002e },
01256         { AR5K_BB_GAIN(24), 0x00000001 },
01257         { AR5K_BB_GAIN(25), 0x00000021 },
01258         { AR5K_BB_GAIN(26), 0x00000011 },
01259         { AR5K_BB_GAIN(27), 0x00000031 },
01260         { AR5K_BB_GAIN(28), 0x00000009 },
01261         { AR5K_BB_GAIN(29), 0x00000029 },
01262         { AR5K_BB_GAIN(30), 0x00000005 },
01263         { AR5K_BB_GAIN(31), 0x00000025 },
01264         { AR5K_BB_GAIN(32), 0x00000015 },
01265         { AR5K_BB_GAIN(33), 0x00000035 },
01266         { AR5K_BB_GAIN(34), 0x0000000d },
01267         { AR5K_BB_GAIN(35), 0x0000002d },
01268         { AR5K_BB_GAIN(36), 0x00000003 },
01269         { AR5K_BB_GAIN(37), 0x00000023 },
01270         { AR5K_BB_GAIN(38), 0x00000013 },
01271         { AR5K_BB_GAIN(39), 0x00000033 },
01272         { AR5K_BB_GAIN(40), 0x0000000b },
01273         { AR5K_BB_GAIN(41), 0x0000002b },
01274         { AR5K_BB_GAIN(42), 0x0000002b },
01275         { AR5K_BB_GAIN(43), 0x0000002b },
01276         { AR5K_BB_GAIN(44), 0x0000002b },
01277         { AR5K_BB_GAIN(45), 0x0000002b },
01278         { AR5K_BB_GAIN(46), 0x0000002b },
01279         { AR5K_BB_GAIN(47), 0x0000002b },
01280         { AR5K_BB_GAIN(48), 0x0000002b },
01281         { AR5K_BB_GAIN(49), 0x0000002b },
01282         { AR5K_BB_GAIN(50), 0x0000002b },
01283         { AR5K_BB_GAIN(51), 0x0000002b },
01284         { AR5K_BB_GAIN(52), 0x0000002b },
01285         { AR5K_BB_GAIN(53), 0x0000002b },
01286         { AR5K_BB_GAIN(54), 0x0000002b },
01287         { AR5K_BB_GAIN(55), 0x0000002b },
01288         { AR5K_BB_GAIN(56), 0x0000002b },
01289         { AR5K_BB_GAIN(57), 0x0000002b },
01290         { AR5K_BB_GAIN(58), 0x0000002b },
01291         { AR5K_BB_GAIN(59), 0x0000002b },
01292         { AR5K_BB_GAIN(60), 0x0000002b },
01293         { AR5K_BB_GAIN(61), 0x0000002b },
01294         { AR5K_BB_GAIN(62), 0x00000002 },
01295         { AR5K_BB_GAIN(63), 0x00000016 },
01296 };
01297 
01298 /* RF5112 Initial BaseBand Gain settings (Same for RF5413/5414+) */
01299 static const struct ath5k_ini rf5112_ini_bbgain[] = {
01300         { AR5K_BB_GAIN(0), 0x00000000 },
01301         { AR5K_BB_GAIN(1), 0x00000001 },
01302         { AR5K_BB_GAIN(2), 0x00000002 },
01303         { AR5K_BB_GAIN(3), 0x00000003 },
01304         { AR5K_BB_GAIN(4), 0x00000004 },
01305         { AR5K_BB_GAIN(5), 0x00000005 },
01306         { AR5K_BB_GAIN(6), 0x00000008 },
01307         { AR5K_BB_GAIN(7), 0x00000009 },
01308         { AR5K_BB_GAIN(8), 0x0000000a },
01309         { AR5K_BB_GAIN(9), 0x0000000b },
01310         { AR5K_BB_GAIN(10), 0x0000000c },
01311         { AR5K_BB_GAIN(11), 0x0000000d },
01312         { AR5K_BB_GAIN(12), 0x00000010 },
01313         { AR5K_BB_GAIN(13), 0x00000011 },
01314         { AR5K_BB_GAIN(14), 0x00000012 },
01315         { AR5K_BB_GAIN(15), 0x00000013 },
01316         { AR5K_BB_GAIN(16), 0x00000014 },
01317         { AR5K_BB_GAIN(17), 0x00000015 },
01318         { AR5K_BB_GAIN(18), 0x00000018 },
01319         { AR5K_BB_GAIN(19), 0x00000019 },
01320         { AR5K_BB_GAIN(20), 0x0000001a },
01321         { AR5K_BB_GAIN(21), 0x0000001b },
01322         { AR5K_BB_GAIN(22), 0x0000001c },
01323         { AR5K_BB_GAIN(23), 0x0000001d },
01324         { AR5K_BB_GAIN(24), 0x00000020 },
01325         { AR5K_BB_GAIN(25), 0x00000021 },
01326         { AR5K_BB_GAIN(26), 0x00000022 },
01327         { AR5K_BB_GAIN(27), 0x00000023 },
01328         { AR5K_BB_GAIN(28), 0x00000024 },
01329         { AR5K_BB_GAIN(29), 0x00000025 },
01330         { AR5K_BB_GAIN(30), 0x00000028 },
01331         { AR5K_BB_GAIN(31), 0x00000029 },
01332         { AR5K_BB_GAIN(32), 0x0000002a },
01333         { AR5K_BB_GAIN(33), 0x0000002b },
01334         { AR5K_BB_GAIN(34), 0x0000002c },
01335         { AR5K_BB_GAIN(35), 0x0000002d },
01336         { AR5K_BB_GAIN(36), 0x00000030 },
01337         { AR5K_BB_GAIN(37), 0x00000031 },
01338         { AR5K_BB_GAIN(38), 0x00000032 },
01339         { AR5K_BB_GAIN(39), 0x00000033 },
01340         { AR5K_BB_GAIN(40), 0x00000034 },
01341         { AR5K_BB_GAIN(41), 0x00000035 },
01342         { AR5K_BB_GAIN(42), 0x00000035 },
01343         { AR5K_BB_GAIN(43), 0x00000035 },
01344         { AR5K_BB_GAIN(44), 0x00000035 },
01345         { AR5K_BB_GAIN(45), 0x00000035 },
01346         { AR5K_BB_GAIN(46), 0x00000035 },
01347         { AR5K_BB_GAIN(47), 0x00000035 },
01348         { AR5K_BB_GAIN(48), 0x00000035 },
01349         { AR5K_BB_GAIN(49), 0x00000035 },
01350         { AR5K_BB_GAIN(50), 0x00000035 },
01351         { AR5K_BB_GAIN(51), 0x00000035 },
01352         { AR5K_BB_GAIN(52), 0x00000035 },
01353         { AR5K_BB_GAIN(53), 0x00000035 },
01354         { AR5K_BB_GAIN(54), 0x00000035 },
01355         { AR5K_BB_GAIN(55), 0x00000035 },
01356         { AR5K_BB_GAIN(56), 0x00000035 },
01357         { AR5K_BB_GAIN(57), 0x00000035 },
01358         { AR5K_BB_GAIN(58), 0x00000035 },
01359         { AR5K_BB_GAIN(59), 0x00000035 },
01360         { AR5K_BB_GAIN(60), 0x00000035 },
01361         { AR5K_BB_GAIN(61), 0x00000035 },
01362         { AR5K_BB_GAIN(62), 0x00000010 },
01363         { AR5K_BB_GAIN(63), 0x0000001a },
01364 };
01365 
01366 
01367 /*
01368  * Write initial register dump
01369  */
01370 static void ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size,
01371                 const struct ath5k_ini *ini_regs, bool change_channel)
01372 {
01373         unsigned int i;
01374 
01375         /* Write initial registers */
01376         for (i = 0; i < size; i++) {
01377                 /* On channel change there is
01378                  * no need to mess with PCU */
01379                 if (change_channel &&
01380                                 ini_regs[i].ini_register >= AR5K_PCU_MIN &&
01381                                 ini_regs[i].ini_register <= AR5K_PCU_MAX)
01382                         continue;
01383 
01384                 switch (ini_regs[i].ini_mode) {
01385                 case AR5K_INI_READ:
01386                         /* Cleared on read */
01387                         ath5k_hw_reg_read(ah, ini_regs[i].ini_register);
01388                         break;
01389                 case AR5K_INI_WRITE:
01390                 default:
01391                         AR5K_REG_WAIT(i);
01392                         ath5k_hw_reg_write(ah, ini_regs[i].ini_value,
01393                                         ini_regs[i].ini_register);
01394                 }
01395         }
01396 }
01397 
01398 static void ath5k_hw_ini_mode_registers(struct ath5k_hw *ah,
01399                 unsigned int size, const struct ath5k_ini_mode *ini_mode,
01400                 u8 mode)
01401 {
01402         unsigned int i;
01403 
01404         for (i = 0; i < size; i++) {
01405                 AR5K_REG_WAIT(i);
01406                 ath5k_hw_reg_write(ah, ini_mode[i].mode_value[mode],
01407                         (u32)ini_mode[i].mode_register);
01408         }
01409 
01410 }
01411 
01412 int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
01413 {
01414         /*
01415          * Write initial register settings
01416          */
01417 
01418         /* For AR5212 and combatible */
01419         if (ah->ah_version == AR5K_AR5212) {
01420 
01421                 /* First set of mode-specific settings */
01422                 ath5k_hw_ini_mode_registers(ah,
01423                         ARRAY_SIZE(ar5212_ini_mode_start),
01424                         ar5212_ini_mode_start, mode);
01425 
01426                 /*
01427                  * Write initial settings common for all modes
01428                  */
01429                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini_common_start),
01430                                 ar5212_ini_common_start, change_channel);
01431 
01432                 /* Second set of mode-specific settings */
01433                 switch (ah->ah_radio) {
01434                 case AR5K_RF5111:
01435 
01436                         ath5k_hw_ini_mode_registers(ah,
01437                                         ARRAY_SIZE(rf5111_ini_mode_end),
01438                                         rf5111_ini_mode_end, mode);
01439 
01440                         ath5k_hw_ini_registers(ah,
01441                                         ARRAY_SIZE(rf5111_ini_common_end),
01442                                         rf5111_ini_common_end, change_channel);
01443 
01444                         /* Baseband gain table */
01445                         ath5k_hw_ini_registers(ah,
01446                                         ARRAY_SIZE(rf5111_ini_bbgain),
01447                                         rf5111_ini_bbgain, change_channel);
01448 
01449                         break;
01450                 case AR5K_RF5112:
01451 
01452                         ath5k_hw_ini_mode_registers(ah,
01453                                         ARRAY_SIZE(rf5112_ini_mode_end),
01454                                         rf5112_ini_mode_end, mode);
01455 
01456                         ath5k_hw_ini_registers(ah,
01457                                         ARRAY_SIZE(rf5112_ini_common_end),
01458                                         rf5112_ini_common_end, change_channel);
01459 
01460                         ath5k_hw_ini_registers(ah,
01461                                         ARRAY_SIZE(rf5112_ini_bbgain),
01462                                         rf5112_ini_bbgain, change_channel);
01463 
01464                         break;
01465                 case AR5K_RF5413:
01466 
01467                         ath5k_hw_ini_mode_registers(ah,
01468                                         ARRAY_SIZE(rf5413_ini_mode_end),
01469                                         rf5413_ini_mode_end, mode);
01470 
01471                         ath5k_hw_ini_registers(ah,
01472                                         ARRAY_SIZE(rf5413_ini_common_end),
01473                                         rf5413_ini_common_end, change_channel);
01474 
01475                         ath5k_hw_ini_registers(ah,
01476                                         ARRAY_SIZE(rf5112_ini_bbgain),
01477                                         rf5112_ini_bbgain, change_channel);
01478 
01479                         break;
01480                 case AR5K_RF2316:
01481                 case AR5K_RF2413:
01482 
01483                         ath5k_hw_ini_mode_registers(ah,
01484                                         ARRAY_SIZE(rf2413_ini_mode_end),
01485                                         rf2413_ini_mode_end, mode);
01486 
01487                         ath5k_hw_ini_registers(ah,
01488                                         ARRAY_SIZE(rf2413_ini_common_end),
01489                                         rf2413_ini_common_end, change_channel);
01490 
01491                         /* Override settings from rf2413_ini_common_end */
01492                         if (ah->ah_radio == AR5K_RF2316) {
01493                                 ath5k_hw_reg_write(ah, 0x00004000,
01494                                                         AR5K_PHY_AGC);
01495                                 ath5k_hw_reg_write(ah, 0x081b7caa,
01496                                                         0xa274);
01497                         }
01498 
01499                         ath5k_hw_ini_registers(ah,
01500                                         ARRAY_SIZE(rf5112_ini_bbgain),
01501                                         rf5112_ini_bbgain, change_channel);
01502                         break;
01503                 case AR5K_RF2317:
01504                 case AR5K_RF2425:
01505 
01506                         ath5k_hw_ini_mode_registers(ah,
01507                                         ARRAY_SIZE(rf2425_ini_mode_end),
01508                                         rf2425_ini_mode_end, mode);
01509 
01510                         ath5k_hw_ini_registers(ah,
01511                                         ARRAY_SIZE(rf2425_ini_common_end),
01512                                         rf2425_ini_common_end, change_channel);
01513 
01514                         ath5k_hw_ini_registers(ah,
01515                                         ARRAY_SIZE(rf5112_ini_bbgain),
01516                                         rf5112_ini_bbgain, change_channel);
01517                         break;
01518                 default:
01519                         return -EINVAL;
01520 
01521                 }
01522 
01523         /* For AR5211 */
01524         } else if (ah->ah_version == AR5K_AR5211) {
01525 
01526                 /* AR5K_MODE_11B */
01527                 if (mode > 2) {
01528                         ATH5K_ERR(ah->ah_sc,
01529                                 "unsupported channel mode: %d\n", mode);
01530                         return -EINVAL;
01531                 }
01532 
01533                 /* Mode-specific settings */
01534                 ath5k_hw_ini_mode_registers(ah, ARRAY_SIZE(ar5211_ini_mode),
01535                                 ar5211_ini_mode, mode);
01536 
01537                 /*
01538                  * Write initial settings common for all modes
01539                  */
01540                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5211_ini),
01541                                 ar5211_ini, change_channel);
01542 
01543                 /* AR5211 only comes with 5111 */
01544 
01545                 /* Baseband gain table */
01546                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(rf5111_ini_bbgain),
01547                                 rf5111_ini_bbgain, change_channel);
01548         /* For AR5210 (for mode settings check out ath5k_hw_reset_tx_queue) */
01549         } else if (ah->ah_version == AR5K_AR5210) {
01550                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5210_ini),
01551                                 ar5210_ini, change_channel);
01552         }
01553 
01554         return 0;
01555 }

ros_rt_wmp
Author(s): Danilo Tardioli, dantard@unizar.es
autogenerated on Fri Jan 3 2014 12:07:54