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00024 #include "ath5k.h"
00025 #include "reg.h"
00026 #include "debug.h"
00027 #include "base.h"
00028
00029
00030
00031
00032
00033 int ath5k_hw_set_capabilities(struct ath5k_hw *ah)
00034 {
00035 u16 ee_header;
00036
00037 ATH5K_TRACE(ah->ah_sc);
00038
00039 ee_header = ah->ah_capabilities.cap_eeprom.ee_header;
00040
00041 if (ah->ah_version == AR5K_AR5210) {
00042
00043
00044
00045
00046 ah->ah_capabilities.cap_range.range_5ghz_min = 5120;
00047 ah->ah_capabilities.cap_range.range_5ghz_max = 5430;
00048 ah->ah_capabilities.cap_range.range_2ghz_min = 0;
00049 ah->ah_capabilities.cap_range.range_2ghz_max = 0;
00050
00051
00052 __set_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode);
00053 __set_bit(AR5K_MODE_11A_TURBO, ah->ah_capabilities.cap_mode);
00054 } else {
00055
00056
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070 if (AR5K_EEPROM_HDR_11A(ee_header)) {
00071
00072 ah->ah_capabilities.cap_range.range_5ghz_min = 5005;
00073 ah->ah_capabilities.cap_range.range_5ghz_max = 6100;
00074
00075
00076 __set_bit(AR5K_MODE_11A,
00077 ah->ah_capabilities.cap_mode);
00078 __set_bit(AR5K_MODE_11A_TURBO,
00079 ah->ah_capabilities.cap_mode);
00080 if (ah->ah_version == AR5K_AR5212)
00081 __set_bit(AR5K_MODE_11G_TURBO,
00082 ah->ah_capabilities.cap_mode);
00083 }
00084
00085
00086
00087 if (AR5K_EEPROM_HDR_11B(ee_header) ||
00088 (AR5K_EEPROM_HDR_11G(ee_header) &&
00089 ah->ah_version != AR5K_AR5211)) {
00090
00091 ah->ah_capabilities.cap_range.range_2ghz_min = 2412;
00092 ah->ah_capabilities.cap_range.range_2ghz_max = 2732;
00093
00094 if (AR5K_EEPROM_HDR_11B(ee_header))
00095 __set_bit(AR5K_MODE_11B,
00096 ah->ah_capabilities.cap_mode);
00097
00098 if (AR5K_EEPROM_HDR_11G(ee_header) &&
00099 ah->ah_version != AR5K_AR5211)
00100 __set_bit(AR5K_MODE_11G,
00101 ah->ah_capabilities.cap_mode);
00102 }
00103 }
00104
00105
00106 if (ah->ah_version == AR5K_AR5210)
00107 ah->ah_capabilities.cap_queues.q_tx_num =
00108 AR5K_NUM_TX_QUEUES_NOQCU;
00109 else
00110 ah->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES;
00111
00112 return 0;
00113 }
00114
00115
00116 int ath5k_hw_get_capability(struct ath5k_hw *ah,
00117 enum ath5k_capability_type cap_type,
00118 u32 capability, u32 *result)
00119 {
00120 ATH5K_TRACE(ah->ah_sc);
00121
00122 switch (cap_type) {
00123 case AR5K_CAP_NUM_TXQUEUES:
00124 if (result) {
00125 if (ah->ah_version == AR5K_AR5210)
00126 *result = AR5K_NUM_TX_QUEUES_NOQCU;
00127 else
00128 *result = AR5K_NUM_TX_QUEUES;
00129 goto yes;
00130 }
00131 case AR5K_CAP_VEOL:
00132 goto yes;
00133 case AR5K_CAP_COMPRESSION:
00134 if (ah->ah_version == AR5K_AR5212)
00135 goto yes;
00136 else
00137 goto no;
00138 case AR5K_CAP_BURST:
00139 goto yes;
00140 case AR5K_CAP_TPC:
00141 goto yes;
00142 case AR5K_CAP_BSSIDMASK:
00143 if (ah->ah_version == AR5K_AR5212)
00144 goto yes;
00145 else
00146 goto no;
00147 case AR5K_CAP_XR:
00148 if (ah->ah_version == AR5K_AR5212)
00149 goto yes;
00150 else
00151 goto no;
00152 default:
00153 goto no;
00154 }
00155
00156 no:
00157 return -EINVAL;
00158 yes:
00159 return 0;
00160 }
00161
00162
00163
00164
00165
00166
00167 int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid,
00168 u16 assoc_id)
00169 {
00170 ATH5K_TRACE(ah->ah_sc);
00171
00172 if (ah->ah_version == AR5K_AR5210) {
00173 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
00174 AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
00175 return 0;
00176 }
00177
00178 return -EIO;
00179 }
00180
00181 int ath5k_hw_disable_pspoll(struct ath5k_hw *ah)
00182 {
00183 ATH5K_TRACE(ah->ah_sc);
00184
00185 if (ah->ah_version == AR5K_AR5210) {
00186 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
00187 AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
00188 return 0;
00189 }
00190
00191 return -EIO;
00192 }