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00046
00047 #define AR5K_NOQCU_TXDP0 0x0000
00048 #define AR5K_NOQCU_TXDP1 0x0004
00049
00050
00051
00052
00053 #define AR5K_CR 0x0008
00054 #define AR5K_CR_TXE0 0x00000001
00055 #define AR5K_CR_TXE1 0x00000002
00056 #define AR5K_CR_RXE 0x00000004
00057 #define AR5K_CR_TXD0 0x00000008
00058 #define AR5K_CR_TXD1 0x00000010
00059 #define AR5K_CR_RXD 0x00000020
00060 #define AR5K_CR_SWI 0x00000040
00061
00062
00063
00064
00065 #define AR5K_RXDP 0x000c
00066
00067
00068
00069
00070 #define AR5K_CFG 0x0014
00071 #define AR5K_CFG_SWTD 0x00000001
00072 #define AR5K_CFG_SWTB 0x00000002
00073 #define AR5K_CFG_SWRD 0x00000004
00074 #define AR5K_CFG_SWRB 0x00000008
00075 #define AR5K_CFG_SWRG 0x00000010
00076 #define AR5K_CFG_IBSS 0x00000020
00077 #define AR5K_CFG_PHY_OK 0x00000100
00078 #define AR5K_CFG_EEBS 0x00000200
00079 #define AR5K_CFG_CLKGD 0x00000400
00080 #define AR5K_CFG_TXCNT 0x00007800
00081 #define AR5K_CFG_TXCNT_S 11
00082 #define AR5K_CFG_TXFSTAT 0x00008000
00083 #define AR5K_CFG_TXFSTRT 0x00010000
00084 #define AR5K_CFG_PCI_THRES 0x00060000
00085 #define AR5K_CFG_PCI_THRES_S 17
00086
00087
00088
00089
00090 #define AR5K_IER 0x0024
00091 #define AR5K_IER_DISABLE 0x00000000
00092 #define AR5K_IER_ENABLE 0x00000001
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103 #define AR5K_BCR 0x0028
00104 #define AR5K_BCR_AP 0x00000000
00105 #define AR5K_BCR_ADHOC 0x00000001
00106 #define AR5K_BCR_BDMAE 0x00000002
00107 #define AR5K_BCR_TQ1FV 0x00000004
00108 #define AR5K_BCR_TQ1V 0x00000008
00109 #define AR5K_BCR_BCGET 0x00000010
00110
00111
00112
00113
00114 #define AR5K_RTSD0 0x0028
00115 #define AR5K_RTSD0_6 0x000000ff
00116 #define AR5K_RTSD0_6_S 0
00117 #define AR5K_RTSD0_9 0x0000ff00
00118 #define AR5K_RTSD0_9_S 8
00119 #define AR5K_RTSD0_12 0x00ff0000
00120 #define AR5K_RTSD0_12_S 16
00121 #define AR5K_RTSD0_18 0xff000000
00122 #define AR5K_RTSD0_18_S 24
00123
00124
00125
00126
00127
00128
00129
00130
00131
00132
00133
00134
00135
00136
00137
00138
00139
00140 #define AR5K_BSR 0x002c
00141 #define AR5K_BSR_BDLYSW 0x00000001
00142 #define AR5K_BSR_BDLYDMA 0x00000002
00143 #define AR5K_BSR_TXQ1F 0x00000004
00144 #define AR5K_BSR_ATIMDLY 0x00000008
00145 #define AR5K_BSR_SNPADHOC 0x00000100
00146 #define AR5K_BSR_SNPBDMAE 0x00000200
00147 #define AR5K_BSR_SNPTQ1FV 0x00000400
00148 #define AR5K_BSR_SNPTQ1V 0x00000800
00149 #define AR5K_BSR_SNAPSHOTSVALID 0x00001000
00150 #define AR5K_BSR_SWBA_CNT 0x00ff0000
00151
00152
00153
00154
00155 #define AR5K_RTSD1 0x002c
00156 #define AR5K_RTSD1_24 0x000000ff
00157 #define AR5K_RTSD1_24_S 0
00158 #define AR5K_RTSD1_36 0x0000ff00
00159 #define AR5K_RTSD1_36_S 8
00160 #define AR5K_RTSD1_48 0x00ff0000
00161 #define AR5K_RTSD1_48_S 16
00162 #define AR5K_RTSD1_54 0xff000000
00163 #define AR5K_RTSD1_54_S 24
00164
00165
00166
00167
00168
00169 #define AR5K_TXCFG 0x0030
00170 #define AR5K_TXCFG_SDMAMR 0x00000007
00171 #define AR5K_TXCFG_SDMAMR_S 0
00172 #define AR5K_TXCFG_B_MODE 0x00000008
00173 #define AR5K_TXCFG_TXFSTP 0x00000008
00174 #define AR5K_TXCFG_TXFULL 0x000003f0
00175 #define AR5K_TXCFG_TXFULL_S 4
00176 #define AR5K_TXCFG_TXFULL_0B 0x00000000
00177 #define AR5K_TXCFG_TXFULL_64B 0x00000010
00178 #define AR5K_TXCFG_TXFULL_128B 0x00000020
00179 #define AR5K_TXCFG_TXFULL_192B 0x00000030
00180 #define AR5K_TXCFG_TXFULL_256B 0x00000040
00181 #define AR5K_TXCFG_TXCONT_EN 0x00000080
00182 #define AR5K_TXCFG_DMASIZE 0x00000100
00183 #define AR5K_TXCFG_JUMBO_DESC_EN 0x00000400
00184 #define AR5K_TXCFG_ADHOC_BCN_ATIM 0x00000800
00185 #define AR5K_TXCFG_ATIM_WINDOW_DEF_DIS 0x00001000
00186 #define AR5K_TXCFG_RTSRND 0x00001000
00187 #define AR5K_TXCFG_FRMPAD_DIS 0x00002000
00188 #define AR5K_TXCFG_RDY_CBR_DIS 0x00004000
00189 #define AR5K_TXCFG_JUMBO_FRM_MODE 0x00008000
00190 #define AR5K_TXCFG_DCU_DBL_BUF_DIS 0x00008000
00191 #define AR5K_TXCFG_DCU_CACHING_DIS 0x00010000
00192
00193
00194
00195
00196 #define AR5K_RXCFG 0x0034
00197 #define AR5K_RXCFG_SDMAMW 0x00000007
00198 #define AR5K_RXCFG_SDMAMW_S 0
00199 #define AR5K_RXCFG_ZLFDMA 0x00000008
00200 #define AR5K_RXCFG_DEF_ANTENNA 0x00000010
00201 #define AR5K_RXCFG_JUMBO_RXE 0x00000020
00202 #define AR5K_RXCFG_JUMBO_WRAP 0x00000040
00203 #define AR5K_RXCFG_SLE_ENTRY 0x00000080
00204
00205
00206
00207
00208
00209 #define AR5K_RXJLA 0x0038
00210
00211
00212
00213
00214 #define AR5K_MIBC 0x0040
00215 #define AR5K_MIBC_COW 0x00000001
00216 #define AR5K_MIBC_FMC 0x00000002
00217 #define AR5K_MIBC_CMC 0x00000004
00218 #define AR5K_MIBC_MCS 0x00000008
00219
00220
00221
00222
00223 #define AR5K_TOPS 0x0044
00224 #define AR5K_TOPS_M 0x0000ffff
00225
00226
00227
00228
00229 #define AR5K_RXNOFRM 0x0048
00230 #define AR5K_RXNOFRM_M 0x000003ff
00231
00232
00233
00234
00235 #define AR5K_TXNOFRM 0x004c
00236 #define AR5K_TXNOFRM_M 0x000003ff
00237 #define AR5K_TXNOFRM_QCU 0x000ffc00
00238 #define AR5K_TXNOFRM_QCU_S 10
00239
00240
00241
00242
00243 #define AR5K_RPGTO 0x0050
00244 #define AR5K_RPGTO_M 0x000003ff
00245
00246
00247
00248
00249 #define AR5K_RFCNT 0x0054
00250 #define AR5K_RFCNT_M 0x0000001f
00251 #define AR5K_RFCNT_RFCL 0x0000000f
00252
00253
00254
00255
00256
00257 #define AR5K_MISC 0x0058
00258 #define AR5K_MISC_DMA_OBS_M 0x000001e0
00259 #define AR5K_MISC_DMA_OBS_S 5
00260 #define AR5K_MISC_MISC_OBS_M 0x00000e00
00261 #define AR5K_MISC_MISC_OBS_S 9
00262 #define AR5K_MISC_MAC_OBS_LSB_M 0x00007000
00263 #define AR5K_MISC_MAC_OBS_LSB_S 12
00264 #define AR5K_MISC_MAC_OBS_MSB_M 0x00038000
00265 #define AR5K_MISC_MAC_OBS_MSB_S 15
00266 #define AR5K_MISC_LED_DECAY 0x001c0000
00267 #define AR5K_MISC_LED_BLINK 0x00e00000
00268
00269
00270
00271
00272
00273 #define AR5K_QCUDCU_CLKGT 0x005c
00274 #define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff
00275 #define AR5K_QCUDCU_CLKGT_DCU 0x07ff0000
00276
00277
00278
00279
00280
00281
00282
00283
00284
00285 #define AR5K_ISR 0x001c
00286 #define AR5K_PISR 0x0080
00287 #define AR5K_ISR_RXOK 0x00000001
00288 #define AR5K_ISR_RXDESC 0x00000002
00289 #define AR5K_ISR_RXERR 0x00000004
00290 #define AR5K_ISR_RXNOFRM 0x00000008
00291 #define AR5K_ISR_RXEOL 0x00000010
00292 #define AR5K_ISR_RXORN 0x00000020
00293 #define AR5K_ISR_TXOK 0x00000040
00294 #define AR5K_ISR_TXDESC 0x00000080
00295 #define AR5K_ISR_TXERR 0x00000100
00296 #define AR5K_ISR_TXNOFRM 0x00000200
00297 #define AR5K_ISR_TXEOL 0x00000400
00298 #define AR5K_ISR_TXURN 0x00000800
00299 #define AR5K_ISR_MIB 0x00001000
00300 #define AR5K_ISR_SWI 0x00002000
00301 #define AR5K_ISR_RXPHY 0x00004000
00302 #define AR5K_ISR_RXKCM 0x00008000
00303 #define AR5K_ISR_SWBA 0x00010000
00304 #define AR5K_ISR_BRSSI 0x00020000
00305 #define AR5K_ISR_BMISS 0x00040000
00306 #define AR5K_ISR_HIUERR 0x00080000
00307 #define AR5K_ISR_BNR 0x00100000
00308 #define AR5K_ISR_MCABT 0x00100000
00309 #define AR5K_ISR_RXCHIRP 0x00200000
00310 #define AR5K_ISR_SSERR 0x00200000
00311 #define AR5K_ISR_DPERR 0x00400000
00312 #define AR5K_ISR_RXDOPPLER 0x00400000
00313 #define AR5K_ISR_TIM 0x00800000
00314 #define AR5K_ISR_BCNMISC 0x00800000
00315
00316 #define AR5K_ISR_GPIO 0x01000000
00317 #define AR5K_ISR_QCBRORN 0x02000000
00318 #define AR5K_ISR_QCBRURN 0x04000000
00319 #define AR5K_ISR_QTRIG 0x08000000
00320
00321
00322
00323
00324
00325
00326
00327 #define AR5K_SISR0 0x0084
00328 #define AR5K_SISR0_QCU_TXOK 0x000003ff
00329 #define AR5K_SISR0_QCU_TXOK_S 0
00330 #define AR5K_SISR0_QCU_TXDESC 0x03ff0000
00331 #define AR5K_SISR0_QCU_TXDESC_S 16
00332
00333 #define AR5K_SISR1 0x0088
00334 #define AR5K_SISR1_QCU_TXERR 0x000003ff
00335 #define AR5K_SISR1_QCU_TXERR_S 0
00336 #define AR5K_SISR1_QCU_TXEOL 0x03ff0000
00337 #define AR5K_SISR1_QCU_TXEOL_S 16
00338
00339 #define AR5K_SISR2 0x008c
00340 #define AR5K_SISR2_QCU_TXURN 0x000003ff
00341 #define AR5K_SISR2_QCU_TXURN_S 0
00342 #define AR5K_SISR2_MCABT 0x00010000
00343 #define AR5K_SISR2_SSERR 0x00020000
00344 #define AR5K_SISR2_DPERR 0x00040000
00345 #define AR5K_SISR2_TIM 0x01000000
00346 #define AR5K_SISR2_CAB_END 0x02000000
00347 #define AR5K_SISR2_DTIM_SYNC 0x04000000
00348 #define AR5K_SISR2_BCN_TIMEOUT 0x08000000
00349 #define AR5K_SISR2_CAB_TIMEOUT 0x10000000
00350 #define AR5K_SISR2_DTIM 0x20000000
00351 #define AR5K_SISR2_TSFOOR 0x80000000
00352
00353 #define AR5K_SISR3 0x0090
00354 #define AR5K_SISR3_QCBRORN 0x000003ff
00355 #define AR5K_SISR3_QCBRORN_S 0
00356 #define AR5K_SISR3_QCBRURN 0x03ff0000
00357 #define AR5K_SISR3_QCBRURN_S 16
00358
00359 #define AR5K_SISR4 0x0094
00360 #define AR5K_SISR4_QTRIG 0x000003ff
00361 #define AR5K_SISR4_QTRIG_S 0
00362
00363
00364
00365
00366 #define AR5K_RAC_PISR 0x00c0
00367 #define AR5K_RAC_SISR0 0x00c4
00368 #define AR5K_RAC_SISR1 0x00c8
00369 #define AR5K_RAC_SISR2 0x00cc
00370 #define AR5K_RAC_SISR3 0x00d0
00371 #define AR5K_RAC_SISR4 0x00d4
00372
00373
00374
00375
00376
00377
00378
00379 #define AR5K_IMR 0x0020
00380 #define AR5K_PIMR 0x00a0
00381 #define AR5K_IMR_RXOK 0x00000001
00382 #define AR5K_IMR_RXDESC 0x00000002
00383 #define AR5K_IMR_RXERR 0x00000004
00384 #define AR5K_IMR_RXNOFRM 0x00000008
00385 #define AR5K_IMR_RXEOL 0x00000010
00386 #define AR5K_IMR_RXORN 0x00000020
00387 #define AR5K_IMR_TXOK 0x00000040
00388 #define AR5K_IMR_TXDESC 0x00000080
00389 #define AR5K_IMR_TXERR 0x00000100
00390 #define AR5K_IMR_TXNOFRM 0x00000200
00391 #define AR5K_IMR_TXEOL 0x00000400
00392 #define AR5K_IMR_TXURN 0x00000800
00393 #define AR5K_IMR_MIB 0x00001000
00394 #define AR5K_IMR_SWI 0x00002000
00395 #define AR5K_IMR_RXPHY 0x00004000
00396 #define AR5K_IMR_RXKCM 0x00008000
00397 #define AR5K_IMR_SWBA 0x00010000
00398 #define AR5K_IMR_BRSSI 0x00020000
00399 #define AR5K_IMR_BMISS 0x00040000
00400 #define AR5K_IMR_HIUERR 0x00080000
00401 #define AR5K_IMR_BNR 0x00100000
00402 #define AR5K_IMR_MCABT 0x00100000
00403 #define AR5K_IMR_RXCHIRP 0x00200000
00404 #define AR5K_IMR_SSERR 0x00200000
00405 #define AR5K_IMR_DPERR 0x00400000
00406 #define AR5K_IMR_RXDOPPLER 0x00400000
00407 #define AR5K_IMR_TIM 0x00800000
00408 #define AR5K_IMR_BCNMISC 0x00800000
00409
00410 #define AR5K_IMR_GPIO 0x01000000
00411 #define AR5K_IMR_QCBRORN 0x02000000
00412 #define AR5K_IMR_QCBRURN 0x04000000
00413 #define AR5K_IMR_QTRIG 0x08000000
00414
00415
00416
00417
00418 #define AR5K_SIMR0 0x00a4
00419 #define AR5K_SIMR0_QCU_TXOK 0x000003ff
00420 #define AR5K_SIMR0_QCU_TXOK_S 0
00421 #define AR5K_SIMR0_QCU_TXDESC 0x03ff0000
00422 #define AR5K_SIMR0_QCU_TXDESC_S 16
00423
00424 #define AR5K_SIMR1 0x00a8
00425 #define AR5K_SIMR1_QCU_TXERR 0x000003ff
00426 #define AR5K_SIMR1_QCU_TXERR_S 0
00427 #define AR5K_SIMR1_QCU_TXEOL 0x03ff0000
00428 #define AR5K_SIMR1_QCU_TXEOL_S 16
00429
00430 #define AR5K_SIMR2 0x00ac
00431 #define AR5K_SIMR2_QCU_TXURN 0x000003ff
00432 #define AR5K_SIMR2_QCU_TXURN_S 0
00433 #define AR5K_SIMR2_MCABT 0x00010000
00434 #define AR5K_SIMR2_SSERR 0x00020000
00435 #define AR5K_SIMR2_DPERR 0x00040000
00436 #define AR5K_SIMR2_TIM 0x01000000
00437 #define AR5K_SIMR2_CAB_END 0x02000000
00438 #define AR5K_SIMR2_DTIM_SYNC 0x04000000
00439 #define AR5K_SIMR2_BCN_TIMEOUT 0x08000000
00440 #define AR5K_SIMR2_CAB_TIMEOUT 0x10000000
00441 #define AR5K_SIMR2_DTIM 0x20000000
00442 #define AR5K_SIMR2_TSFOOR 0x80000000
00443
00444 #define AR5K_SIMR3 0x00b0
00445 #define AR5K_SIMR3_QCBRORN 0x000003ff
00446 #define AR5K_SIMR3_QCBRORN_S 0
00447 #define AR5K_SIMR3_QCBRURN 0x03ff0000
00448 #define AR5K_SIMR3_QCBRURN_S 16
00449
00450 #define AR5K_SIMR4 0x00b4
00451 #define AR5K_SIMR4_QTRIG 0x000003ff
00452 #define AR5K_SIMR4_QTRIG_S 0
00453
00454
00455
00456
00457
00458
00459
00460
00461
00462 #define AR5K_DCM_ADDR 0x0400
00463 #define AR5K_DCM_DATA 0x0404
00464
00465
00466
00467
00468 #define AR5K_WOW_PCFG 0x0410
00469 #define AR5K_WOW_PCFG_PAT_MATCH_EN 0x00000001
00470 #define AR5K_WOW_PCFG_LONG_FRAME_POL 0x00000002
00471 #define AR5K_WOW_PCFG_WOBMISS 0x00000004
00472 #define AR5K_WOW_PCFG_PAT_0_EN 0x00000100
00473 #define AR5K_WOW_PCFG_PAT_1_EN 0x00000200
00474 #define AR5K_WOW_PCFG_PAT_2_EN 0x00000400
00475 #define AR5K_WOW_PCFG_PAT_3_EN 0x00000800
00476 #define AR5K_WOW_PCFG_PAT_4_EN 0x00001000
00477 #define AR5K_WOW_PCFG_PAT_5_EN 0x00002000
00478
00479
00480
00481
00482 #define AR5K_WOW_PAT_IDX 0x0414
00483
00484
00485
00486
00487 #define AR5K_WOW_PAT_DATA 0x0418
00488 #define AR5K_WOW_PAT_DATA_0_3_V 0x00000001
00489 #define AR5K_WOW_PAT_DATA_1_4_V 0x00000100
00490 #define AR5K_WOW_PAT_DATA_2_5_V 0x00010000
00491 #define AR5K_WOW_PAT_DATA_0_3_M 0x01000000
00492 #define AR5K_WOW_PAT_DATA_1_4_M 0x04000000
00493 #define AR5K_WOW_PAT_DATA_2_5_M 0x10000000
00494
00495
00496
00497
00498 #define AR5K_DCCFG 0x0420
00499 #define AR5K_DCCFG_GLOBAL_EN 0x00000001
00500 #define AR5K_DCCFG_BYPASS_EN 0x00000002
00501 #define AR5K_DCCFG_BCAST_EN 0x00000004
00502 #define AR5K_DCCFG_MCAST_EN 0x00000008
00503
00504
00505
00506
00507 #define AR5K_CCFG 0x0600
00508 #define AR5K_CCFG_WINDOW_SIZE 0x00000007
00509 #define AR5K_CCFG_CPC_EN 0x00000008
00510
00511 #define AR5K_CCFG_CCU 0x0604
00512 #define AR5K_CCFG_CCU_CUP_EN 0x00000001
00513 #define AR5K_CCFG_CCU_CREDIT 0x00000002
00514 #define AR5K_CCFG_CCU_CD_THRES 0x00000080
00515 #define AR5K_CCFG_CCU_CUP_LCNT 0x00010000
00516 #define AR5K_CCFG_CCU_INIT 0x00100200
00517
00518
00519
00520
00521 #define AR5K_CPC0 0x0610
00522 #define AR5K_CPC1 0x0614
00523 #define AR5K_CPC2 0x0618
00524 #define AR5K_CPC3 0x061c
00525 #define AR5K_CPCOVF 0x0620
00526
00527
00528
00529
00530
00531
00532
00533
00534
00535
00536
00537
00538
00539
00540
00541
00542
00543
00544
00545
00546 #define AR5K_QUEUE_REG(_r, _q) (((_q) << 2) + _r)
00547 #define AR5K_QCU_GLOBAL_READ(_r, _q) (AR5K_REG_READ(_r) & (1 << _q))
00548 #define AR5K_QCU_GLOBAL_WRITE(_r, _q) AR5K_REG_WRITE(_r, (1 << _q))
00549
00550
00551
00552
00553 #define AR5K_QCU_TXDP_BASE 0x0800
00554 #define AR5K_QUEUE_TXDP(_q) AR5K_QUEUE_REG(AR5K_QCU_TXDP_BASE, _q)
00555
00556
00557
00558
00559 #define AR5K_QCU_TXE 0x0840
00560 #define AR5K_ENABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXE, _q)
00561 #define AR5K_QUEUE_ENABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXE, _q)
00562
00563
00564
00565
00566 #define AR5K_QCU_TXD 0x0880
00567 #define AR5K_DISABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXD, _q)
00568 #define AR5K_QUEUE_DISABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXD, _q)
00569
00570
00571
00572
00573 #define AR5K_QCU_CBRCFG_BASE 0x08c0
00574 #define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff
00575 #define AR5K_QCU_CBRCFG_INTVAL_S 0
00576 #define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000
00577 #define AR5K_QCU_CBRCFG_ORN_THRES_S 24
00578 #define AR5K_QUEUE_CBRCFG(_q) AR5K_QUEUE_REG(AR5K_QCU_CBRCFG_BASE, _q)
00579
00580
00581
00582
00583 #define AR5K_QCU_RDYTIMECFG_BASE 0x0900
00584 #define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff
00585 #define AR5K_QCU_RDYTIMECFG_INTVAL_S 0
00586 #define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000
00587 #define AR5K_QUEUE_RDYTIMECFG(_q) AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q)
00588
00589
00590
00591
00592 #define AR5K_QCU_ONESHOTARM_SET 0x0940
00593 #define AR5K_QCU_ONESHOTARM_SET_M 0x0000ffff
00594
00595
00596
00597
00598 #define AR5K_QCU_ONESHOTARM_CLEAR 0x0980
00599 #define AR5K_QCU_ONESHOTARM_CLEAR_M 0x0000ffff
00600
00601
00602
00603
00604 #define AR5K_QCU_MISC_BASE 0x09c0
00605 #define AR5K_QCU_MISC_FRSHED_M 0x0000000f
00606 #define AR5K_QCU_MISC_FRSHED_ASAP 0
00607 #define AR5K_QCU_MISC_FRSHED_CBR 1
00608 #define AR5K_QCU_MISC_FRSHED_DBA_GT 2
00609 #define AR5K_QCU_MISC_FRSHED_TIM_GT 3
00610 #define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4
00611 #define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010
00612 #define AR5K_QCU_MISC_CBREXP_DIS 0x00000020
00613 #define AR5K_QCU_MISC_CBREXP_BCN_DIS 0x00000040
00614 #define AR5K_QCU_MISC_BCN_ENABLE 0x00000080
00615 #define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100
00616 #define AR5K_QCU_MISC_RDY_VEOL_POLICY 0x00000200
00617 #define AR5K_QCU_MISC_CBR_RESET_CNT 0x00000400
00618 #define AR5K_QCU_MISC_DCU_EARLY 0x00000800
00619 #define AR5K_QCU_MISC_DCU_CMP_EN 0x00001000
00620 #define AR5K_QUEUE_MISC(_q) AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q)
00621
00622
00623
00624
00625
00626 #define AR5K_QCU_STS_BASE 0x0a00
00627 #define AR5K_QCU_STS_FRMPENDCNT 0x00000003
00628 #define AR5K_QCU_STS_CBREXPCNT 0x0000ff00
00629 #define AR5K_QUEUE_STATUS(_q) AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q)
00630
00631
00632
00633
00634 #define AR5K_QCU_RDYTIMESHDN 0x0a40
00635 #define AR5K_QCU_RDYTIMESHDN_M 0x000003ff
00636
00637
00638
00639
00640 #define AR5K_QCU_CBB_SELECT 0x0b00
00641 #define AR5K_QCU_CBB_ADDR 0x0b04
00642 #define AR5K_QCU_CBB_ADDR_S 9
00643
00644
00645
00646
00647
00648 #define AR5K_QCU_CBCFG 0x0b08
00649
00650
00651
00652
00653
00654
00655
00656
00657
00658
00659
00660
00661
00662
00663
00664
00665
00666
00667
00668
00669
00670
00671 #define AR5K_DCU_QCUMASK_BASE 0x1000
00672 #define AR5K_DCU_QCUMASK_M 0x000003ff
00673 #define AR5K_QUEUE_QCUMASK(_q) AR5K_QUEUE_REG(AR5K_DCU_QCUMASK_BASE, _q)
00674
00675
00676
00677
00678 #define AR5K_DCU_LCL_IFS_BASE 0x1040
00679 #define AR5K_DCU_LCL_IFS_CW_MIN 0x000003ff
00680 #define AR5K_DCU_LCL_IFS_CW_MIN_S 0
00681 #define AR5K_DCU_LCL_IFS_CW_MAX 0x000ffc00
00682 #define AR5K_DCU_LCL_IFS_CW_MAX_S 10
00683 #define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000
00684 #define AR5K_DCU_LCL_IFS_AIFS_S 20
00685 #define AR5K_DCU_LCL_IFS_AIFS_MAX 0xfc
00686 #define AR5K_QUEUE_DFS_LOCAL_IFS(_q) AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q)
00687
00688
00689
00690
00691 #define AR5K_DCU_RETRY_LMT_BASE 0x1080
00692 #define AR5K_DCU_RETRY_LMT_SH_RETRY 0x0000000f
00693 #define AR5K_DCU_RETRY_LMT_SH_RETRY_S 0
00694 #define AR5K_DCU_RETRY_LMT_LG_RETRY 0x000000f0
00695 #define AR5K_DCU_RETRY_LMT_LG_RETRY_S 4
00696 #define AR5K_DCU_RETRY_LMT_SSH_RETRY 0x00003f00
00697 #define AR5K_DCU_RETRY_LMT_SSH_RETRY_S 8
00698 #define AR5K_DCU_RETRY_LMT_SLG_RETRY 0x000fc000
00699 #define AR5K_DCU_RETRY_LMT_SLG_RETRY_S 14
00700 #define AR5K_QUEUE_DFS_RETRY_LIMIT(_q) AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q)
00701
00702
00703
00704
00705 #define AR5K_DCU_CHAN_TIME_BASE 0x10c0
00706 #define AR5K_DCU_CHAN_TIME_DUR 0x000fffff
00707 #define AR5K_DCU_CHAN_TIME_DUR_S 0
00708 #define AR5K_DCU_CHAN_TIME_ENABLE 0x00100000
00709 #define AR5K_QUEUE_DFS_CHANNEL_TIME(_q) AR5K_QUEUE_REG(AR5K_DCU_CHAN_TIME_BASE, _q)
00710
00711
00712
00713
00714
00715
00716
00717
00718
00719
00720
00721
00722
00723 #define AR5K_DCU_MISC_BASE 0x1100
00724 #define AR5K_DCU_MISC_BACKOFF 0x0000003f
00725 #define AR5K_DCU_MISC_ETS_RTS_POL 0x00000040
00726
00727
00728 #define AR5K_DCU_MISC_ETS_CW_POL 0x00000080
00729
00730 #define AR5K_DCU_MISC_FRAG_WAIT 0x00000100
00731 #define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200
00732 #define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800
00733 #define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000
00734 #define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000
00735 #define AR5K_DCU_MISC_VIRTCOL 0x0000c000
00736 #define AR5K_DCU_MISC_VIRTCOL_NORMAL 0
00737 #define AR5K_DCU_MISC_VIRTCOL_IGNORE 1
00738 #define AR5K_DCU_MISC_BCN_ENABLE 0x00010000
00739 #define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000
00740 #define AR5K_DCU_MISC_ARBLOCK_CTL_S 17
00741 #define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0
00742 #define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1
00743 #define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2
00744 #define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000
00745 #define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000
00746 #define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000
00747 #define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000
00748 #define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000
00749 #define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000
00750 #define AR5K_QUEUE_DFS_MISC(_q) AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q)
00751
00752
00753
00754
00755 #define AR5K_DCU_SEQNUM_BASE 0x1140
00756 #define AR5K_DCU_SEQNUM_M 0x00000fff
00757 #define AR5K_QUEUE_DCU_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q)
00758
00759
00760
00761
00762 #define AR5K_DCU_GBL_IFS_SIFS 0x1030
00763 #define AR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff
00764
00765
00766
00767
00768 #define AR5K_DCU_GBL_IFS_SLOT 0x1070
00769 #define AR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff
00770
00771
00772
00773
00774 #define AR5K_DCU_GBL_IFS_EIFS 0x10b0
00775 #define AR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff
00776
00777
00778
00779
00780
00781
00782
00783
00784
00785
00786
00787 #define AR5K_DCU_GBL_IFS_MISC 0x10f0
00788 #define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007
00789 #define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008
00790 #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0
00791 #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00
00792 #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR_S 10
00793 #define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000
00794 #define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST 0x00400000
00795 #define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST 0x00800000
00796 #define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS 0x01000000
00797
00798
00799
00800
00801 #define AR5K_DCU_FP 0x1230
00802 #define AR5K_DCU_FP_NOBURST_DCU_EN 0x00000001
00803 #define AR5K_DCU_FP_NOBURST_EN 0x00000010
00804 #define AR5K_DCU_FP_BURST_DCU_EN 0x00000020
00805
00806
00807
00808
00809 #define AR5K_DCU_TXP 0x1270
00810 #define AR5K_DCU_TXP_M 0x000003ff
00811 #define AR5K_DCU_TXP_STATUS 0x00010000
00812
00813
00814
00815
00816
00817
00818 #define AR5K_DCU_TX_FILTER_0_BASE 0x1038
00819 #define AR5K_DCU_TX_FILTER_0(_n) (AR5K_DCU_TX_FILTER_0_BASE + (_n * 64))
00820
00821
00822
00823
00824 #define AR5K_DCU_TX_FILTER_1_BASE 0x103c
00825 #define AR5K_DCU_TX_FILTER_1(_n) (AR5K_DCU_TX_FILTER_1_BASE + (_n * 64))
00826
00827
00828
00829
00830 #define AR5K_DCU_TX_FILTER_CLR 0x143c
00831
00832
00833
00834
00835 #define AR5K_DCU_TX_FILTER_SET 0x147c
00836
00837
00838
00839
00840 #define AR5K_RESET_CTL 0x4000
00841 #define AR5K_RESET_CTL_PCU 0x00000001
00842 #define AR5K_RESET_CTL_DMA 0x00000002
00843 #define AR5K_RESET_CTL_BASEBAND 0x00000002
00844 #define AR5K_RESET_CTL_MAC 0x00000004
00845 #define AR5K_RESET_CTL_PHY 0x00000008
00846 #define AR5K_RESET_CTL_PCI 0x00000010
00847
00848
00849
00850
00851 #define AR5K_SLEEP_CTL 0x4004
00852 #define AR5K_SLEEP_CTL_SLDUR 0x0000ffff
00853 #define AR5K_SLEEP_CTL_SLDUR_S 0
00854 #define AR5K_SLEEP_CTL_SLE 0x00030000
00855 #define AR5K_SLEEP_CTL_SLE_S 16
00856 #define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000
00857 #define AR5K_SLEEP_CTL_SLE_SLP 0x00010000
00858 #define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000
00859 #define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008
00860 #define AR5K_SLEEP_CTL_DUR_TIM_POL 0x00040000
00861 #define AR5K_SLEEP_CTL_DUR_WRITE_POL 0x00080000
00862 #define AR5K_SLEEP_CTL_SLE_POL 0x00100000
00863
00864
00865
00866
00867 #define AR5K_INTPEND 0x4008
00868 #define AR5K_INTPEND_M 0x00000001
00869
00870
00871
00872
00873 #define AR5K_SFR 0x400c
00874 #define AR5K_SFR_EN 0x00000001
00875
00876
00877
00878
00879
00880 #define AR5K_PCICFG 0x4010
00881 #define AR5K_PCICFG_EEAE 0x00000001
00882 #define AR5K_PCICFG_SLEEP_CLOCK_EN 0x00000002
00883 #define AR5K_PCICFG_CLKRUNEN 0x00000004
00884 #define AR5K_PCICFG_EESIZE 0x00000018
00885 #define AR5K_PCICFG_EESIZE_S 3
00886 #define AR5K_PCICFG_EESIZE_4K 0
00887 #define AR5K_PCICFG_EESIZE_8K 1
00888 #define AR5K_PCICFG_EESIZE_16K 2
00889 #define AR5K_PCICFG_EESIZE_FAIL 3
00890 #define AR5K_PCICFG_LED 0x00000060
00891 #define AR5K_PCICFG_LED_NONE 0x00000000
00892 #define AR5K_PCICFG_LED_PEND 0x00000020
00893 #define AR5K_PCICFG_LED_ASSOC 0x00000040
00894 #define AR5K_PCICFG_BUS_SEL 0x00000380
00895 #define AR5K_PCICFG_CBEFIX_DIS 0x00000400
00896 #define AR5K_PCICFG_SL_INTEN 0x00000800
00897 #define AR5K_PCICFG_LED_BCTL 0x00001000
00898 #define AR5K_PCICFG_RETRY_FIX 0x00001000
00899 #define AR5K_PCICFG_SL_INPEN 0x00002000
00900 #define AR5K_PCICFG_SPWR_DN 0x00010000
00901 #define AR5K_PCICFG_LEDMODE 0x000e0000
00902 #define AR5K_PCICFG_LEDMODE_PROP 0x00000000
00903 #define AR5K_PCICFG_LEDMODE_PROM 0x00020000
00904 #define AR5K_PCICFG_LEDMODE_PWR 0x00040000
00905 #define AR5K_PCICFG_LEDMODE_RAND 0x00060000
00906 #define AR5K_PCICFG_LEDBLINK 0x00700000
00907 #define AR5K_PCICFG_LEDBLINK_S 20
00908 #define AR5K_PCICFG_LEDSLOW 0x00800000
00909 #define AR5K_PCICFG_LEDSTATE \
00910 (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \
00911 AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW)
00912 #define AR5K_PCICFG_SLEEP_CLOCK_RATE 0x03000000
00913 #define AR5K_PCICFG_SLEEP_CLOCK_RATE_S 24
00914
00915
00916
00917
00918
00919
00920
00921
00922
00923
00924
00925
00926
00927
00928
00929
00930
00931 #define AR5K_NUM_GPIO 6
00932
00933 #define AR5K_GPIOCR 0x4014
00934 #define AR5K_GPIOCR_INT_ENA 0x00008000
00935 #define AR5K_GPIOCR_INT_SELL 0x00000000
00936 #define AR5K_GPIOCR_INT_SELH 0x00010000
00937 #define AR5K_GPIOCR_IN(n) (0 << ((n) * 2))
00938 #define AR5K_GPIOCR_OUT0(n) (1 << ((n) * 2))
00939 #define AR5K_GPIOCR_OUT1(n) (2 << ((n) * 2))
00940 #define AR5K_GPIOCR_OUT(n) (3 << ((n) * 2))
00941 #define AR5K_GPIOCR_INT_SEL(n) ((n) << 12)
00942
00943
00944
00945
00946 #define AR5K_GPIODO 0x4018
00947
00948
00949
00950
00951 #define AR5K_GPIODI 0x401c
00952 #define AR5K_GPIODI_M 0x0000002f
00953
00954
00955
00956
00957 #define AR5K_SREV 0x4020
00958 #define AR5K_SREV_REV 0x0000000f
00959 #define AR5K_SREV_REV_S 0
00960 #define AR5K_SREV_VER 0x000000ff
00961 #define AR5K_SREV_VER_S 4
00962
00963
00964
00965
00966 #define AR5K_TXEPOST 0x4028
00967
00968
00969
00970
00971 #define AR5K_QCU_SLEEP_MASK 0x402c
00972
00973
00974
00975
00976
00977
00978
00979
00980
00981 #define AR5K_5414_CBCFG 0x4068
00982 #define AR5K_5414_CBCFG_BUF_DIS 0x10
00983
00984
00985
00986
00987
00988 #define AR5K_PCIE_PM_CTL 0x4068
00989
00990 #define AR5K_PCIE_PM_CTL_L1_WHEN_D2 0x00000001
00991
00992 #define AR5K_PCIE_PM_CTL_L0_L0S_CLEAR 0x00000002
00993 #define AR5K_PCIE_PM_CTL_L0_L0S_EN 0x00000004
00994 #define AR5K_PCIE_PM_CTL_LDRESET_EN 0x00000008
00995
00996
00997 #define AR5K_PCIE_PM_CTL_PME_EN 0x00000010
00998 #define AR5K_PCIE_PM_CTL_AUX_PWR_DET 0x00000020
00999 #define AR5K_PCIE_PM_CTL_PME_CLEAR 0x00000040
01000 #define AR5K_PCIE_PM_CTL_PSM_D0 0x00000080
01001 #define AR5K_PCIE_PM_CTL_PSM_D1 0x00000100
01002 #define AR5K_PCIE_PM_CTL_PSM_D2 0x00000200
01003 #define AR5K_PCIE_PM_CTL_PSM_D3 0x00000400
01004
01005
01006
01007
01008 #define AR5K_PCIE_WAEN 0x407c
01009
01010
01011
01012
01013
01014 #define AR5K_PCIE_SERDES 0x4080
01015 #define AR5K_PCIE_SERDES_RESET 0x4084
01016
01017
01018
01019
01020
01021
01022
01023
01024
01025
01026
01027
01028
01029
01030
01031
01032
01033
01034
01035
01036
01037
01038
01039
01040
01041
01042
01043
01044
01045
01046
01047
01048
01049
01050
01051
01052
01053
01054 #define AR5K_EEPROM_BASE 0x6000
01055
01056
01057
01058
01059 #define AR5K_EEPROM_DATA_5211 0x6004
01060 #define AR5K_EEPROM_DATA_5210 0x6800
01061 #define AR5K_EEPROM_DATA (ah->ah_version == AR5K_AR5210 ? \
01062 AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211)
01063
01064
01065
01066
01067 #define AR5K_EEPROM_CMD 0x6008
01068 #define AR5K_EEPROM_CMD_READ 0x00000001
01069 #define AR5K_EEPROM_CMD_WRITE 0x00000002
01070 #define AR5K_EEPROM_CMD_RESET 0x00000004
01071
01072
01073
01074
01075 #define AR5K_EEPROM_STAT_5210 0x6c00
01076 #define AR5K_EEPROM_STAT_5211 0x600c
01077 #define AR5K_EEPROM_STATUS (ah->ah_version == AR5K_AR5210 ? \
01078 AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211)
01079 #define AR5K_EEPROM_STAT_RDERR 0x00000001
01080 #define AR5K_EEPROM_STAT_RDDONE 0x00000002
01081 #define AR5K_EEPROM_STAT_WRERR 0x00000004
01082 #define AR5K_EEPROM_STAT_WRDONE 0x00000008
01083
01084
01085
01086
01087 #define AR5K_EEPROM_CFG 0x6010
01088 #define AR5K_EEPROM_CFG_SIZE 0x00000003
01089 #define AR5K_EEPROM_CFG_SIZE_AUTO 0
01090 #define AR5K_EEPROM_CFG_SIZE_4KBIT 1
01091 #define AR5K_EEPROM_CFG_SIZE_8KBIT 2
01092 #define AR5K_EEPROM_CFG_SIZE_16KBIT 3
01093 #define AR5K_EEPROM_CFG_WR_WAIT_DIS 0x00000004
01094 #define AR5K_EEPROM_CFG_CLK_RATE 0x00000018
01095 #define AR5K_EEPROM_CFG_CLK_RATE_S 3
01096 #define AR5K_EEPROM_CFG_CLK_RATE_156KHZ 0
01097 #define AR5K_EEPROM_CFG_CLK_RATE_312KHZ 1
01098 #define AR5K_EEPROM_CFG_CLK_RATE_625KHZ 2
01099 #define AR5K_EEPROM_CFG_PROT_KEY 0x00ffff00
01100 #define AR5K_EEPROM_CFG_PROT_KEY_S 8
01101 #define AR5K_EEPROM_CFG_LIND_EN 0x01000000
01102
01103
01104
01105
01106
01107
01108
01109
01110
01111
01112
01113
01114
01115
01116 #define AR5K_PCU_MIN 0x8000
01117 #define AR5K_PCU_MAX 0x8fff
01118
01119
01120
01121
01122 #define AR5K_STA_ID0 0x8000
01123 #define AR5K_STA_ID0_ARRD_L32 0xffffffff
01124
01125
01126
01127
01128 #define AR5K_STA_ID1 0x8004
01129 #define AR5K_STA_ID1_ADDR_U16 0x0000ffff
01130 #define AR5K_STA_ID1_AP 0x00010000
01131 #define AR5K_STA_ID1_ADHOC 0x00020000
01132 #define AR5K_STA_ID1_PWR_SV 0x00040000
01133 #define AR5K_STA_ID1_NO_KEYSRCH 0x00080000
01134 #define AR5K_STA_ID1_NO_PSPOLL 0x00100000
01135 #define AR5K_STA_ID1_PCF_5211 0x00100000
01136 #define AR5K_STA_ID1_PCF_5210 0x00200000
01137 #define AR5K_STA_ID1_PCF (ah->ah_version == AR5K_AR5210 ? \
01138 AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211)
01139 #define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000
01140 #define AR5K_STA_ID1_DESC_ANTENNA 0x00400000
01141 #define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000
01142 #define AR5K_STA_ID1_ACKCTS_6MB 0x01000000
01143 #define AR5K_STA_ID1_BASE_RATE_11B 0x02000000
01144 #define AR5K_STA_ID1_SELFGEN_DEF_ANT 0x04000000
01145 #define AR5K_STA_ID1_CRYPT_MIC_EN 0x08000000
01146 #define AR5K_STA_ID1_KEYSRCH_MODE 0x10000000
01147 #define AR5K_STA_ID1_PRESERVE_SEQ_NUM 0x20000000
01148 #define AR5K_STA_ID1_CBCIV_ENDIAN 0x40000000
01149 #define AR5K_STA_ID1_KEYSRCH_MCAST 0x80000000
01150
01151 #define AR5K_STA_ID1_ANTENNA_SETTINGS (AR5K_STA_ID1_DEFAULT_ANTENNA | \
01152 AR5K_STA_ID1_DESC_ANTENNA | \
01153 AR5K_STA_ID1_RTS_DEF_ANTENNA | \
01154 AR5K_STA_ID1_SELFGEN_DEF_ANT)
01155
01156
01157
01158
01159 #define AR5K_BSS_ID0 0x8008
01160
01161
01162
01163
01164
01165
01166 #define AR5K_BSS_ID1 0x800c
01167 #define AR5K_BSS_ID1_AID 0xffff0000
01168 #define AR5K_BSS_ID1_AID_S 16
01169
01170
01171
01172
01173 #define AR5K_SLOT_TIME 0x8010
01174
01175
01176
01177
01178 #define AR5K_TIME_OUT 0x8014
01179 #define AR5K_TIME_OUT_ACK 0x00001fff
01180 #define AR5K_TIME_OUT_ACK_S 0
01181 #define AR5K_TIME_OUT_CTS 0x1fff0000
01182 #define AR5K_TIME_OUT_CTS_S 16
01183
01184
01185
01186
01187 #define AR5K_RSSI_THR 0x8018
01188 #define AR5K_RSSI_THR_M 0x000000ff
01189 #define AR5K_RSSI_THR_BMISS_5210 0x00000700
01190 #define AR5K_RSSI_THR_BMISS_5210_S 8
01191 #define AR5K_RSSI_THR_BMISS_5211 0x0000ff00
01192 #define AR5K_RSSI_THR_BMISS_5211_S 8
01193 #define AR5K_RSSI_THR_BMISS (ah->ah_version == AR5K_AR5210 ? \
01194 AR5K_RSSI_THR_BMISS_5210 : AR5K_RSSI_THR_BMISS_5211)
01195 #define AR5K_RSSI_THR_BMISS_S 8
01196
01197
01198
01199
01200
01201
01202
01203
01204
01205
01206
01207
01208
01209
01210 #define AR5K_NODCU_RETRY_LMT 0x801c
01211 #define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f
01212 #define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 0
01213 #define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0
01214 #define AR5K_NODCU_RETRY_LMT_LG_RETRY_S 4
01215 #define AR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00
01216 #define AR5K_NODCU_RETRY_LMT_SSH_RETRY_S 8
01217 #define AR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000
01218 #define AR5K_NODCU_RETRY_LMT_SLG_RETRY_S 14
01219 #define AR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000
01220 #define AR5K_NODCU_RETRY_LMT_CW_MIN_S 20
01221
01222
01223
01224
01225 #define AR5K_USEC_5210 0x8020
01226 #define AR5K_USEC_5211 0x801c
01227 #define AR5K_USEC (ah->ah_version == AR5K_AR5210 ? \
01228 AR5K_USEC_5210 : AR5K_USEC_5211)
01229 #define AR5K_USEC_1 0x0000007f
01230 #define AR5K_USEC_1_S 0
01231 #define AR5K_USEC_32 0x00003f80
01232 #define AR5K_USEC_32_S 7
01233 #define AR5K_USEC_TX_LATENCY_5211 0x007fc000
01234 #define AR5K_USEC_TX_LATENCY_5211_S 14
01235 #define AR5K_USEC_RX_LATENCY_5211 0x1f800000
01236 #define AR5K_USEC_RX_LATENCY_5211_S 23
01237 #define AR5K_USEC_TX_LATENCY_5210 0x000fc000
01238 #define AR5K_USEC_TX_LATENCY_5210_S 14
01239 #define AR5K_USEC_RX_LATENCY_5210 0x03f00000
01240 #define AR5K_USEC_RX_LATENCY_5210_S 20
01241
01242
01243
01244
01245 #define AR5K_BEACON_5210 0x8024
01246 #define AR5K_BEACON_5211 0x8020
01247 #define AR5K_BEACON (ah->ah_version == AR5K_AR5210 ? \
01248 AR5K_BEACON_5210 : AR5K_BEACON_5211)
01249 #define AR5K_BEACON_PERIOD 0x0000ffff
01250 #define AR5K_BEACON_PERIOD_S 0
01251 #define AR5K_BEACON_TIM 0x007f0000
01252 #define AR5K_BEACON_TIM_S 16
01253 #define AR5K_BEACON_ENABLE 0x00800000
01254 #define AR5K_BEACON_RESET_TSF 0x01000000
01255
01256
01257
01258
01259 #define AR5K_CFP_PERIOD_5210 0x8028
01260 #define AR5K_CFP_PERIOD_5211 0x8024
01261 #define AR5K_CFP_PERIOD (ah->ah_version == AR5K_AR5210 ? \
01262 AR5K_CFP_PERIOD_5210 : AR5K_CFP_PERIOD_5211)
01263
01264
01265
01266
01267 #define AR5K_TIMER0_5210 0x802c
01268 #define AR5K_TIMER0_5211 0x8028
01269 #define AR5K_TIMER0 (ah->ah_version == AR5K_AR5210 ? \
01270 AR5K_TIMER0_5210 : AR5K_TIMER0_5211)
01271
01272
01273
01274
01275 #define AR5K_TIMER1_5210 0x8030
01276 #define AR5K_TIMER1_5211 0x802c
01277 #define AR5K_TIMER1 (ah->ah_version == AR5K_AR5210 ? \
01278 AR5K_TIMER1_5210 : AR5K_TIMER1_5211)
01279
01280
01281
01282
01283 #define AR5K_TIMER2_5210 0x8034
01284 #define AR5K_TIMER2_5211 0x8030
01285 #define AR5K_TIMER2 (ah->ah_version == AR5K_AR5210 ? \
01286 AR5K_TIMER2_5210 : AR5K_TIMER2_5211)
01287
01288
01289
01290
01291 #define AR5K_TIMER3_5210 0x8038
01292 #define AR5K_TIMER3_5211 0x8034
01293 #define AR5K_TIMER3 (ah->ah_version == AR5K_AR5210 ? \
01294 AR5K_TIMER3_5210 : AR5K_TIMER3_5211)
01295
01296
01297
01298
01299
01300 #define AR5K_IFS0 0x8040
01301 #define AR5K_IFS0_SIFS 0x000007ff
01302 #define AR5K_IFS0_SIFS_S 0
01303 #define AR5K_IFS0_DIFS 0x007ff800
01304 #define AR5K_IFS0_DIFS_S 11
01305
01306
01307
01308
01309 #define AR5K_IFS1 0x8044
01310 #define AR5K_IFS1_PIFS 0x00000fff
01311 #define AR5K_IFS1_PIFS_S 0
01312 #define AR5K_IFS1_EIFS 0x03fff000
01313 #define AR5K_IFS1_EIFS_S 12
01314 #define AR5K_IFS1_CS_EN 0x04000000
01315
01316
01317
01318
01319
01320 #define AR5K_CFP_DUR_5210 0x8048
01321 #define AR5K_CFP_DUR_5211 0x8038
01322 #define AR5K_CFP_DUR (ah->ah_version == AR5K_AR5210 ? \
01323 AR5K_CFP_DUR_5210 : AR5K_CFP_DUR_5211)
01324
01325
01326
01327
01328 #define AR5K_RX_FILTER_5210 0x804c
01329 #define AR5K_RX_FILTER_5211 0x803c
01330 #define AR5K_RX_FILTER (ah->ah_version == AR5K_AR5210 ? \
01331 AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211)
01332 #define AR5K_RX_FILTER_UCAST 0x00000001
01333 #define AR5K_RX_FILTER_MCAST 0x00000002
01334 #define AR5K_RX_FILTER_BCAST 0x00000004
01335 #define AR5K_RX_FILTER_CONTROL 0x00000008
01336 #define AR5K_RX_FILTER_BEACON 0x00000010
01337 #define AR5K_RX_FILTER_PROM 0x00000020
01338 #define AR5K_RX_FILTER_XRPOLL 0x00000040
01339 #define AR5K_RX_FILTER_PROBEREQ 0x00000080
01340 #define AR5K_RX_FILTER_PHYERR_5212 0x00000100
01341 #define AR5K_RX_FILTER_RADARERR_5212 0x00000200
01342 #define AR5K_RX_FILTER_PHYERR_5211 0x00000040
01343 #define AR5K_RX_FILTER_RADARERR_5211 0x00000080
01344 #define AR5K_RX_FILTER_PHYERR \
01345 ((ah->ah_version == AR5K_AR5211 ? \
01346 AR5K_RX_FILTER_PHYERR_5211 : AR5K_RX_FILTER_PHYERR_5212))
01347 #define AR5K_RX_FILTER_RADARERR \
01348 ((ah->ah_version == AR5K_AR5211 ? \
01349 AR5K_RX_FILTER_RADARERR_5211 : AR5K_RX_FILTER_RADARERR_5212))
01350
01351
01352
01353
01354 #define AR5K_MCAST_FILTER0_5210 0x8050
01355 #define AR5K_MCAST_FILTER0_5211 0x8040
01356 #define AR5K_MCAST_FILTER0 (ah->ah_version == AR5K_AR5210 ? \
01357 AR5K_MCAST_FILTER0_5210 : AR5K_MCAST_FILTER0_5211)
01358
01359
01360
01361
01362 #define AR5K_MCAST_FILTER1_5210 0x8054
01363 #define AR5K_MCAST_FILTER1_5211 0x8044
01364 #define AR5K_MCAST_FILTER1 (ah->ah_version == AR5K_AR5210 ? \
01365 AR5K_MCAST_FILTER1_5210 : AR5K_MCAST_FILTER1_5211)
01366
01367
01368
01369
01370
01371 #define AR5K_TX_MASK0 0x8058
01372
01373
01374
01375
01376 #define AR5K_TX_MASK1 0x805c
01377
01378
01379
01380
01381 #define AR5K_CLR_TMASK 0x8060
01382
01383
01384
01385
01386 #define AR5K_TRIG_LVL 0x8064
01387
01388
01389
01390
01391
01392
01393
01394
01395 #define AR5K_DIAG_SW_5210 0x8068
01396 #define AR5K_DIAG_SW_5211 0x8048
01397 #define AR5K_DIAG_SW (ah->ah_version == AR5K_AR5210 ? \
01398 AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211)
01399 #define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001
01400 #define AR5K_DIAG_SW_DIS_ACK 0x00000002
01401 #define AR5K_DIAG_SW_DIS_CTS 0x00000004
01402 #define AR5K_DIAG_SW_DIS_ENC 0x00000008
01403 #define AR5K_DIAG_SW_DIS_DEC 0x00000010
01404 #define AR5K_DIAG_SW_DIS_TX 0x00000020
01405 #define AR5K_DIAG_SW_DIS_RX_5210 0x00000040
01406 #define AR5K_DIAG_SW_DIS_RX_5211 0x00000020
01407 #define AR5K_DIAG_SW_DIS_RX (ah->ah_version == AR5K_AR5210 ? \
01408 AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211)
01409 #define AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080
01410 #define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040
01411 #define AR5K_DIAG_SW_LOOP_BACK (ah->ah_version == AR5K_AR5210 ? \
01412 AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211)
01413 #define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100
01414 #define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080
01415 #define AR5K_DIAG_SW_CORR_FCS (ah->ah_version == AR5K_AR5210 ? \
01416 AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211)
01417 #define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200
01418 #define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100
01419 #define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \
01420 AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211)
01421 #define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400
01422 #define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200
01423 #define AR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \
01424 AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211)
01425 #define AR5K_DIAG_SW_ECO_ENABLE 0x00000400
01426 #define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800
01427 #define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00
01428 #define AR5K_DIAG_SW_SCRAM_SEED_S 10
01429 #define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000
01430 #define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000
01431 #define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000
01432 #define AR5K_DIAG_SW_FRAME_NV0 (ah->ah_version == AR5K_AR5210 ? \
01433 AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211)
01434 #define AR5K_DIAG_SW_OBSPT_M 0x000c0000
01435 #define AR5K_DIAG_SW_OBSPT_S 18
01436 #define AR5K_DIAG_SW_RX_CLEAR_HIGH 0x0010000
01437 #define AR5K_DIAG_SW_IGNORE_CARR_SENSE 0x0020000
01438 #define AR5K_DIAG_SW_CHANEL_IDLE_HIGH 0x0040000
01439 #define AR5K_DIAG_SW_PHEAR_ME 0x0080000
01440
01441
01442
01443
01444 #define AR5K_TSF_L32_5210 0x806c
01445 #define AR5K_TSF_L32_5211 0x804c
01446 #define AR5K_TSF_L32 (ah->ah_version == AR5K_AR5210 ? \
01447 AR5K_TSF_L32_5210 : AR5K_TSF_L32_5211)
01448
01449
01450
01451
01452 #define AR5K_TSF_U32_5210 0x8070
01453 #define AR5K_TSF_U32_5211 0x8050
01454 #define AR5K_TSF_U32 (ah->ah_version == AR5K_AR5210 ? \
01455 AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211)
01456
01457
01458
01459
01460 #define AR5K_LAST_TSTP 0x8080
01461
01462
01463
01464
01465 #define AR5K_ADDAC_TEST 0x8054
01466 #define AR5K_ADDAC_TEST_TXCONT 0x00000001
01467 #define AR5K_ADDAC_TEST_TST_MODE 0x00000002
01468 #define AR5K_ADDAC_TEST_LOOP_EN 0x00000004
01469 #define AR5K_ADDAC_TEST_LOOP_LEN 0x00000008
01470 #define AR5K_ADDAC_TEST_USE_U8 0x00004000
01471 #define AR5K_ADDAC_TEST_MSB 0x00008000
01472 #define AR5K_ADDAC_TEST_TRIG_SEL 0x00010000
01473 #define AR5K_ADDAC_TEST_TRIG_PTY 0x00020000
01474 #define AR5K_ADDAC_TEST_RXCONT 0x00040000
01475 #define AR5K_ADDAC_TEST_CAPTURE 0x00080000
01476 #define AR5K_ADDAC_TEST_TST_ARM 0x00100000
01477
01478
01479
01480
01481 #define AR5K_DEFAULT_ANTENNA 0x8058
01482
01483
01484
01485
01486
01487 #define AR5K_FRAME_CTL_QOSM 0x805c
01488
01489
01490
01491
01492 #define AR5K_SEQ_MASK 0x8060
01493
01494
01495
01496
01497 #define AR5K_RETRY_CNT 0x8084
01498 #define AR5K_RETRY_CNT_SSH 0x0000003f
01499 #define AR5K_RETRY_CNT_SLG 0x00000fc0
01500
01501
01502
01503
01504 #define AR5K_BACKOFF 0x8088
01505 #define AR5K_BACKOFF_CW 0x000003ff
01506 #define AR5K_BACKOFF_CNT 0x03ff0000
01507
01508
01509
01510
01511
01512
01513 #define AR5K_NAV_5210 0x808c
01514 #define AR5K_NAV_5211 0x8084
01515 #define AR5K_NAV (ah->ah_version == AR5K_AR5210 ? \
01516 AR5K_NAV_5210 : AR5K_NAV_5211)
01517
01518
01519
01520
01521 #define AR5K_RTS_OK_5210 0x8090
01522 #define AR5K_RTS_OK_5211 0x8088
01523 #define AR5K_RTS_OK (ah->ah_version == AR5K_AR5210 ? \
01524 AR5K_RTS_OK_5210 : AR5K_RTS_OK_5211)
01525
01526
01527
01528
01529 #define AR5K_RTS_FAIL_5210 0x8094
01530 #define AR5K_RTS_FAIL_5211 0x808c
01531 #define AR5K_RTS_FAIL (ah->ah_version == AR5K_AR5210 ? \
01532 AR5K_RTS_FAIL_5210 : AR5K_RTS_FAIL_5211)
01533
01534
01535
01536
01537 #define AR5K_ACK_FAIL_5210 0x8098
01538 #define AR5K_ACK_FAIL_5211 0x8090
01539 #define AR5K_ACK_FAIL (ah->ah_version == AR5K_AR5210 ? \
01540 AR5K_ACK_FAIL_5210 : AR5K_ACK_FAIL_5211)
01541
01542
01543
01544
01545 #define AR5K_FCS_FAIL_5210 0x809c
01546 #define AR5K_FCS_FAIL_5211 0x8094
01547 #define AR5K_FCS_FAIL (ah->ah_version == AR5K_AR5210 ? \
01548 AR5K_FCS_FAIL_5210 : AR5K_FCS_FAIL_5211)
01549
01550
01551
01552
01553 #define AR5K_BEACON_CNT_5210 0x80a0
01554 #define AR5K_BEACON_CNT_5211 0x8098
01555 #define AR5K_BEACON_CNT (ah->ah_version == AR5K_AR5210 ? \
01556 AR5K_BEACON_CNT_5210 : AR5K_BEACON_CNT_5211)
01557
01558
01559
01560
01561
01562
01563
01564 #define AR5K_TPC 0x80e8
01565 #define AR5K_TPC_ACK 0x0000003f
01566 #define AR5K_TPC_ACK_S 0
01567 #define AR5K_TPC_CTS 0x00003f00
01568 #define AR5K_TPC_CTS_S 8
01569 #define AR5K_TPC_CHIRP 0x003f0000
01570 #define AR5K_TPC_CHIRP_S 16
01571 #define AR5K_TPC_DOPPLER 0x0f000000
01572 #define AR5K_TPC_DOPPLER_S 24
01573
01574
01575
01576
01577 #define AR5K_XRMODE 0x80c0
01578 #define AR5K_XRMODE_POLL_TYPE_M 0x0000003f
01579 #define AR5K_XRMODE_POLL_TYPE_S 0
01580 #define AR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c
01581 #define AR5K_XRMODE_POLL_SUBTYPE_S 2
01582 #define AR5K_XRMODE_POLL_WAIT_ALL 0x00000080
01583 #define AR5K_XRMODE_SIFS_DELAY 0x000fff00
01584 #define AR5K_XRMODE_FRAME_HOLD_M 0xfff00000
01585 #define AR5K_XRMODE_FRAME_HOLD_S 20
01586
01587
01588
01589
01590 #define AR5K_XRDELAY 0x80c4
01591 #define AR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff
01592 #define AR5K_XRDELAY_SLOT_DELAY_S 0
01593 #define AR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000
01594 #define AR5K_XRDELAY_CHIRP_DELAY_S 16
01595
01596
01597
01598
01599 #define AR5K_XRTIMEOUT 0x80c8
01600 #define AR5K_XRTIMEOUT_CHIRP_M 0x0000ffff
01601 #define AR5K_XRTIMEOUT_CHIRP_S 0
01602 #define AR5K_XRTIMEOUT_POLL_M 0xffff0000
01603 #define AR5K_XRTIMEOUT_POLL_S 16
01604
01605
01606
01607
01608 #define AR5K_XRCHIRP 0x80cc
01609 #define AR5K_XRCHIRP_SEND 0x00000001
01610 #define AR5K_XRCHIRP_GAP 0xffff0000
01611
01612
01613
01614
01615 #define AR5K_XRSTOMP 0x80d0
01616 #define AR5K_XRSTOMP_TX 0x00000001
01617 #define AR5K_XRSTOMP_RX 0x00000002
01618 #define AR5K_XRSTOMP_TX_RSSI 0x00000004
01619 #define AR5K_XRSTOMP_TX_BSSID 0x00000008
01620 #define AR5K_XRSTOMP_DATA 0x00000010
01621 #define AR5K_XRSTOMP_RSSI_THRES 0x0000ff00
01622
01623
01624
01625
01626 #define AR5K_SLEEP0 0x80d4
01627 #define AR5K_SLEEP0_NEXT_DTIM 0x0007ffff
01628 #define AR5K_SLEEP0_NEXT_DTIM_S 0
01629 #define AR5K_SLEEP0_ASSUME_DTIM 0x00080000
01630 #define AR5K_SLEEP0_ENH_SLEEP_EN 0x00100000
01631 #define AR5K_SLEEP0_CABTO 0xff000000
01632 #define AR5K_SLEEP0_CABTO_S 24
01633
01634
01635
01636
01637 #define AR5K_SLEEP1 0x80d8
01638 #define AR5K_SLEEP1_NEXT_TIM 0x0007ffff
01639 #define AR5K_SLEEP1_NEXT_TIM_S 0
01640 #define AR5K_SLEEP1_BEACON_TO 0xff000000
01641 #define AR5K_SLEEP1_BEACON_TO_S 24
01642
01643
01644
01645
01646 #define AR5K_SLEEP2 0x80dc
01647 #define AR5K_SLEEP2_TIM_PER 0x0000ffff
01648 #define AR5K_SLEEP2_TIM_PER_S 0
01649 #define AR5K_SLEEP2_DTIM_PER 0xffff0000
01650 #define AR5K_SLEEP2_DTIM_PER_S 16
01651
01652
01653
01654
01655 #define AR5K_BSS_IDM0 0x80e0
01656 #define AR5K_BSS_IDM1 0x80e4
01657
01658
01659
01660
01661
01662
01663
01664 #define AR5K_TXPC 0x80e8
01665 #define AR5K_TXPC_ACK_M 0x0000003f
01666 #define AR5K_TXPC_ACK_S 0
01667 #define AR5K_TXPC_CTS_M 0x00003f00
01668 #define AR5K_TXPC_CTS_S 8
01669 #define AR5K_TXPC_CHIRP_M 0x003f0000
01670 #define AR5K_TXPC_CHIRP_S 16
01671 #define AR5K_TXPC_DOPPLER 0x0f000000
01672 #define AR5K_TXPC_DOPPLER_S 24
01673
01674
01675
01676
01677 #define AR5K_PROFCNT_TX 0x80ec
01678 #define AR5K_PROFCNT_RX 0x80f0
01679 #define AR5K_PROFCNT_RXCLR 0x80f4
01680 #define AR5K_PROFCNT_CYCLE 0x80f8
01681
01682
01683
01684
01685 #define AR5K_QUIET_CTL1 0x80fc
01686 #define AR5K_QUIET_CTL1_NEXT_QT_TSF 0x0000ffff
01687 #define AR5K_QUIET_CTL1_NEXT_QT_TSF_S 0
01688 #define AR5K_QUIET_CTL1_QT_EN 0x00010000
01689 #define AR5K_QUIET_CTL1_ACK_CTS_EN 0x00020000
01690
01691 #define AR5K_QUIET_CTL2 0x8100
01692 #define AR5K_QUIET_CTL2_QT_PER 0x0000ffff
01693 #define AR5K_QUIET_CTL2_QT_PER_S 0
01694 #define AR5K_QUIET_CTL2_QT_DUR 0xffff0000
01695 #define AR5K_QUIET_CTL2_QT_DUR_S 16
01696
01697
01698
01699
01700 #define AR5K_TSF_PARM 0x8104
01701 #define AR5K_TSF_PARM_INC 0x000000ff
01702 #define AR5K_TSF_PARM_INC_S 0
01703
01704
01705
01706
01707 #define AR5K_QOS_NOACK 0x8108
01708 #define AR5K_QOS_NOACK_2BIT_VALUES 0x0000000f
01709 #define AR5K_QOS_NOACK_2BIT_VALUES_S 0
01710 #define AR5K_QOS_NOACK_BIT_OFFSET 0x00000070
01711 #define AR5K_QOS_NOACK_BIT_OFFSET_S 4
01712 #define AR5K_QOS_NOACK_BYTE_OFFSET 0x00000180
01713 #define AR5K_QOS_NOACK_BYTE_OFFSET_S 7
01714
01715
01716
01717
01718 #define AR5K_PHY_ERR_FIL 0x810c
01719 #define AR5K_PHY_ERR_FIL_RADAR 0x00000020
01720 #define AR5K_PHY_ERR_FIL_OFDM 0x00020000
01721 #define AR5K_PHY_ERR_FIL_CCK 0x02000000
01722
01723
01724
01725
01726 #define AR5K_XRLAT_TX 0x8110
01727
01728
01729
01730
01731 #define AR5K_ACKSIFS 0x8114
01732 #define AR5K_ACKSIFS_INC 0x00000000
01733
01734
01735
01736
01737 #define AR5K_MIC_QOS_CTL 0x8118
01738 #define AR5K_MIC_QOS_CTL_OFF(_n) (1 << (_n * 2))
01739 #define AR5K_MIC_QOS_CTL_MQ_EN 0x00010000
01740
01741
01742
01743
01744 #define AR5K_MIC_QOS_SEL 0x811c
01745 #define AR5K_MIC_QOS_SEL_OFF(_n) (1 << (_n * 4))
01746
01747
01748
01749
01750 #define AR5K_MISC_MODE 0x8120
01751 #define AR5K_MISC_MODE_FBSSID_MATCH 0x00000001
01752 #define AR5K_MISC_MODE_ACKSIFS_MEM 0x00000002
01753 #define AR5K_MISC_MODE_COMBINED_MIC 0x00000004
01754
01755
01756
01757
01758
01759 #define AR5K_OFDM_FIL_CNT 0x8124
01760
01761
01762
01763
01764 #define AR5K_CCK_FIL_CNT 0x8128
01765
01766
01767
01768
01769 #define AR5K_PHYERR_CNT1 0x812c
01770 #define AR5K_PHYERR_CNT1_MASK 0x8130
01771
01772 #define AR5K_PHYERR_CNT2 0x8134
01773 #define AR5K_PHYERR_CNT2_MASK 0x8138
01774
01775
01776
01777
01778 #define AR5K_TSF_THRES 0x813c
01779
01780
01781
01782
01783
01784
01785
01786
01787
01788 #define AR5K_RATE_ACKSIFS_BASE 0x8680
01789 #define AR5K_RATE_ACKSIFS(_n) (AR5K_RATE_ACKSIFS_BSE + ((_n) << 2))
01790 #define AR5K_RATE_ACKSIFS_NORMAL 0x00000001
01791 #define AR5K_RATE_ACKSIFS_TURBO 0x00000400
01792
01793
01794
01795
01796 #define AR5K_RATE_DUR_BASE 0x8700
01797 #define AR5K_RATE_DUR(_n) (AR5K_RATE_DUR_BASE + ((_n) << 2))
01798
01799
01800
01801
01802
01803 #define AR5K_RATE2DB_BASE 0x87c0
01804 #define AR5K_RATE2DB(_n) (AR5K_RATE2DB_BASE + ((_n) << 2))
01805
01806
01807
01808
01809
01810 #define AR5K_DB2RATE_BASE 0x87e0
01811 #define AR5K_DB2RATE(_n) (AR5K_DB2RATE_BASE + ((_n) << 2))
01812
01813
01814
01815
01816
01817
01818 #define AR5K_KEYTABLE_0_5210 0x9000
01819 #define AR5K_KEYTABLE_0_5211 0x8800
01820 #define AR5K_KEYTABLE_5210(_n) (AR5K_KEYTABLE_0_5210 + ((_n) << 5))
01821 #define AR5K_KEYTABLE_5211(_n) (AR5K_KEYTABLE_0_5211 + ((_n) << 5))
01822 #define AR5K_KEYTABLE(_n) (ah->ah_version == AR5K_AR5210 ? \
01823 AR5K_KEYTABLE_5210(_n) : AR5K_KEYTABLE_5211(_n))
01824 #define AR5K_KEYTABLE_OFF(_n, x) (AR5K_KEYTABLE(_n) + (x << 2))
01825 #define AR5K_KEYTABLE_TYPE(_n) AR5K_KEYTABLE_OFF(_n, 5)
01826 #define AR5K_KEYTABLE_TYPE_40 0x00000000
01827 #define AR5K_KEYTABLE_TYPE_104 0x00000001
01828 #define AR5K_KEYTABLE_TYPE_128 0x00000003
01829 #define AR5K_KEYTABLE_TYPE_TKIP 0x00000004
01830 #define AR5K_KEYTABLE_TYPE_AES 0x00000005
01831 #define AR5K_KEYTABLE_TYPE_CCM 0x00000006
01832 #define AR5K_KEYTABLE_TYPE_NULL 0x00000007
01833 #define AR5K_KEYTABLE_ANTENNA 0x00000008
01834 #define AR5K_KEYTABLE_MAC0(_n) AR5K_KEYTABLE_OFF(_n, 6)
01835 #define AR5K_KEYTABLE_MAC1(_n) AR5K_KEYTABLE_OFF(_n, 7)
01836 #define AR5K_KEYTABLE_VALID 0x00008000
01837
01838
01839
01840 #define AR5K_KEYTABLE_MIC_OFFSET 64
01841
01842
01843
01844
01845
01846
01847
01848
01849
01850
01851
01852
01853
01854 #define AR5K_KEYTABLE_SIZE_5210 64
01855 #define AR5K_KEYTABLE_SIZE_5211 128
01856 #define AR5K_KEYTABLE_SIZE (ah->ah_version == AR5K_AR5210 ? \
01857 AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211)
01858
01859
01860
01861
01862
01863
01864
01865 #define AR5K_PHY_BASE 0x9800
01866 #define AR5K_PHY(_n) (AR5K_PHY_BASE + ((_n) << 2))
01867
01868
01869
01870
01871 #define AR5K_PHY_TST2 0x9800
01872 #define AR5K_PHY_TST2_TRIG_SEL 0x00000007
01873 #define AR5K_PHY_TST2_TRIG 0x00000010
01874 #define AR5K_PHY_TST2_CBUS_MODE 0x00000060
01875 #define AR5K_PHY_TST2_CLK32 0x00000400
01876 #define AR5K_PHY_TST2_CHANCOR_DUMP_EN 0x00000800
01877 #define AR5K_PHY_TST2_EVEN_CHANCOR_DUMP 0x00001000
01878 #define AR5K_PHY_TST2_RFSILENT_EN 0x00002000
01879 #define AR5K_PHY_TST2_ALT_RFDATA 0x00004000
01880 #define AR5K_PHY_TST2_MINI_OBS_EN 0x00008000
01881 #define AR5K_PHY_TST2_RX2_IS_RX5_INV 0x00010000
01882 #define AR5K_PHY_TST2_SLOW_CLK160 0x00020000
01883 #define AR5K_PHY_TST2_AGC_OBS_SEL_3 0x00040000
01884 #define AR5K_PHY_TST2_BBB_OBS_SEL 0x00080000
01885 #define AR5K_PHY_TST2_ADC_OBS_SEL 0x00800000
01886 #define AR5K_PHY_TST2_RX_CLR_SEL 0x08000000
01887 #define AR5K_PHY_TST2_FORCE_AGC_CLR 0x10000000
01888 #define AR5K_PHY_SHIFT_2GHZ 0x00004007
01889 #define AR5K_PHY_SHIFT_5GHZ 0x00000007
01890
01891
01892
01893
01894
01895
01896
01897
01898
01899
01900
01901 #define AR5K_PHY_TURBO 0x9804
01902 #define AR5K_PHY_TURBO_MODE 0x00000001
01903 #define AR5K_PHY_TURBO_SHORT 0x00000002
01904 #define AR5K_PHY_TURBO_MIMO 0x00000004
01905
01906
01907
01908
01909
01910 #define AR5K_PHY_AGC 0x9808
01911 #define AR5K_PHY_TST1 0x9808
01912 #define AR5K_PHY_AGC_DISABLE 0x08000000
01913 #define AR5K_PHY_TST1_TXHOLD 0x00003800
01914 #define AR5K_PHY_TST1_TXSRC_SRC 0x00000002
01915 #define AR5K_PHY_TST1_TXSRC_SRC_S 1
01916 #define AR5K_PHY_TST1_TXSRC_ALT 0x00000080
01917 #define AR5K_PHY_TST1_TXSRC_ALT_S 7
01918
01919
01920
01921
01922
01923 #define AR5K_PHY_TIMING_3 0x9814
01924 #define AR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000
01925 #define AR5K_PHY_TIMING_3_DSC_MAN_S 17
01926 #define AR5K_PHY_TIMING_3_DSC_EXP 0x0001e000
01927 #define AR5K_PHY_TIMING_3_DSC_EXP_S 13
01928
01929
01930
01931
01932 #define AR5K_PHY_CHIP_ID 0x9818
01933
01934
01935
01936
01937 #define AR5K_PHY_ACT 0x981c
01938 #define AR5K_PHY_ACT_ENABLE 0x00000001
01939 #define AR5K_PHY_ACT_DISABLE 0x00000002
01940
01941
01942
01943
01944 #define AR5K_PHY_RF_CTL2 0x9824
01945 #define AR5K_PHY_RF_CTL2_TXF2TXD_START 0x0000000f
01946 #define AR5K_PHY_RF_CTL2_TXF2TXD_START_S 0
01947
01948 #define AR5K_PHY_RF_CTL3 0x9828
01949 #define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000ff00
01950 #define AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S 8
01951
01952 #define AR5K_PHY_ADC_CTL 0x982c
01953 #define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF 0x00000003
01954 #define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_S 0
01955 #define AR5K_PHY_ADC_CTL_PWD_DAC_OFF 0x00002000
01956 #define AR5K_PHY_ADC_CTL_PWD_BAND_GAP_OFF 0x00004000
01957 #define AR5K_PHY_ADC_CTL_PWD_ADC_OFF 0x00008000
01958 #define AR5K_PHY_ADC_CTL_INBUFGAIN_ON 0x00030000
01959 #define AR5K_PHY_ADC_CTL_INBUFGAIN_ON_S 16
01960
01961 #define AR5K_PHY_RF_CTL4 0x9834
01962 #define AR5K_PHY_RF_CTL4_TXF2XPA_A_ON 0x00000001
01963 #define AR5K_PHY_RF_CTL4_TXF2XPA_B_ON 0x00000100
01964 #define AR5K_PHY_RF_CTL4_TXE2XPA_A_OFF 0x00010000
01965 #define AR5K_PHY_RF_CTL4_TXE2XPA_B_OFF 0x01000000
01966
01967
01968
01969
01970
01971 #define AR5K_PHY_PA_CTL 0x9838
01972 #define AR5K_PHY_PA_CTL_XPA_A_HI 0x00000001
01973 #define AR5K_PHY_PA_CTL_XPA_B_HI 0x00000002
01974 #define AR5K_PHY_PA_CTL_XPA_A_EN 0x00000004
01975 #define AR5K_PHY_PA_CTL_XPA_B_EN 0x00000008
01976
01977
01978
01979
01980 #define AR5K_PHY_SETTLING 0x9844
01981 #define AR5K_PHY_SETTLING_AGC 0x0000007f
01982 #define AR5K_PHY_SETTLING_AGC_S 0
01983 #define AR5K_PHY_SETTLING_SWITCH 0x00003f80
01984 #define AR5K_PHY_SETTLING_SWITCH_S 7
01985
01986
01987
01988
01989 #define AR5K_PHY_GAIN 0x9848
01990 #define AR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000
01991 #define AR5K_PHY_GAIN_TXRX_ATTEN_S 12
01992 #define AR5K_PHY_GAIN_TXRX_RF_MAX 0x007c0000
01993 #define AR5K_PHY_GAIN_TXRX_RF_MAX_S 18
01994
01995 #define AR5K_PHY_GAIN_OFFSET 0x984c
01996 #define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000
01997
01998
01999
02000
02001
02002 #define AR5K_PHY_DESIRED_SIZE 0x9850
02003 #define AR5K_PHY_DESIRED_SIZE_ADC 0x000000ff
02004 #define AR5K_PHY_DESIRED_SIZE_ADC_S 0
02005 #define AR5K_PHY_DESIRED_SIZE_PGA 0x0000ff00
02006 #define AR5K_PHY_DESIRED_SIZE_PGA_S 8
02007 #define AR5K_PHY_DESIRED_SIZE_TOT 0x0ff00000
02008 #define AR5K_PHY_DESIRED_SIZE_TOT_S 20
02009
02010
02011
02012
02013
02014 #define AR5K_PHY_SIG 0x9858
02015 #define AR5K_PHY_SIG_FIRSTEP 0x0003f000
02016 #define AR5K_PHY_SIG_FIRSTEP_S 12
02017 #define AR5K_PHY_SIG_FIRPWR 0x03fc0000
02018 #define AR5K_PHY_SIG_FIRPWR_S 18
02019
02020
02021
02022
02023
02024 #define AR5K_PHY_AGCCOARSE 0x985c
02025 #define AR5K_PHY_AGCCOARSE_LO 0x00007f80
02026 #define AR5K_PHY_AGCCOARSE_LO_S 7
02027 #define AR5K_PHY_AGCCOARSE_HI 0x003f8000
02028 #define AR5K_PHY_AGCCOARSE_HI_S 15
02029
02030
02031
02032
02033 #define AR5K_PHY_AGCCTL 0x9860
02034 #define AR5K_PHY_AGCCTL_CAL 0x00000001
02035 #define AR5K_PHY_AGCCTL_NF 0x00000002
02036 #define AR5K_PHY_AGCCTL_OFDM_DIV_DIS 0x00000008
02037 #define AR5K_PHY_AGCCTL_NF_EN 0x00008000
02038 #define AR5K_PHY_AGCTL_FLTR_CAL 0x00010000
02039 #define AR5K_PHY_AGCCTL_NF_NOUPDATE 0x00020000
02040
02041
02042
02043
02044 #define AR5K_PHY_NF 0x9864
02045 #define AR5K_PHY_NF_M 0x000001ff
02046 #define AR5K_PHY_NF_ACTIVE 0x00000100
02047 #define AR5K_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_PHY_NF_M)
02048 #define AR5K_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_PHY_NF_M) + 1)
02049 #define AR5K_PHY_NF_SVAL(_n) (((_n) & AR5K_PHY_NF_M) | (1 << 9))
02050 #define AR5K_PHY_NF_THRESH62 0x0007f000
02051 #define AR5K_PHY_NF_THRESH62_S 12
02052 #define AR5K_PHY_NF_MINCCA_PWR 0x0ff80000
02053 #define AR5K_PHY_NF_MINCCA_PWR_S 19
02054
02055
02056
02057
02058 #define AR5K_PHY_ADCSAT 0x9868
02059 #define AR5K_PHY_ADCSAT_ICNT 0x0001f800
02060 #define AR5K_PHY_ADCSAT_ICNT_S 11
02061 #define AR5K_PHY_ADCSAT_THR 0x000007e0
02062 #define AR5K_PHY_ADCSAT_THR_S 5
02063
02064
02065
02066
02067
02068
02069 #define AR5K_PHY_WEAK_OFDM_HIGH_THR 0x9868
02070 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT 0x0000001f
02071 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT_S 0
02072 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1 0x00fe0000
02073 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_S 17
02074 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2 0x7f000000
02075 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_S 24
02076
02077
02078 #define AR5K_PHY_WEAK_OFDM_LOW_THR 0x986c
02079 #define AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN 0x00000001
02080 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT 0x00003f00
02081 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT_S 8
02082 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M1 0x001fc000
02083 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M1_S 14
02084 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2 0x0fe00000
02085 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_S 21
02086
02087
02088
02089
02090
02091 #define AR5K_PHY_SCR 0x9870
02092
02093 #define AR5K_PHY_SLMT 0x9874
02094 #define AR5K_PHY_SLMT_32MHZ 0x0000007f
02095
02096 #define AR5K_PHY_SCAL 0x9878
02097 #define AR5K_PHY_SCAL_32MHZ 0x0000000e
02098 #define AR5K_PHY_SCAL_32MHZ_2417 0x0000000a
02099 #define AR5K_PHY_SCAL_32MHZ_HB63 0x00000032
02100
02101
02102
02103
02104 #define AR5K_PHY_PLL 0x987c
02105 #define AR5K_PHY_PLL_20MHZ 0x00000013
02106
02107 #define AR5K_PHY_PLL_40MHZ_5211 0x00000018
02108 #define AR5K_PHY_PLL_40MHZ_5212 0x000000aa
02109 #define AR5K_PHY_PLL_40MHZ_5413 0x00000004
02110 #define AR5K_PHY_PLL_40MHZ (ah->ah_version == AR5K_AR5211 ? \
02111 AR5K_PHY_PLL_40MHZ_5211 : AR5K_PHY_PLL_40MHZ_5212)
02112
02113 #define AR5K_PHY_PLL_44MHZ_5211 0x00000019
02114 #define AR5K_PHY_PLL_44MHZ_5212 0x000000ab
02115 #define AR5K_PHY_PLL_44MHZ (ah->ah_version == AR5K_AR5211 ? \
02116 AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212)
02117
02118 #define AR5K_PHY_PLL_RF5111 0x00000000
02119 #define AR5K_PHY_PLL_RF5112 0x00000040
02120 #define AR5K_PHY_PLL_HALF_RATE 0x00000100
02121 #define AR5K_PHY_PLL_QUARTER_RATE 0x00000200
02122
02123
02124
02125
02126
02127
02128
02129
02130
02131
02132 #define AR5K_RF_BUFFER 0x989c
02133 #define AR5K_RF_BUFFER_CONTROL_0 0x98c0
02134 #define AR5K_RF_BUFFER_CONTROL_1 0x98c4
02135 #define AR5K_RF_BUFFER_CONTROL_2 0x98cc
02136
02137 #define AR5K_RF_BUFFER_CONTROL_3 0x98d0
02138
02139
02140
02141 #define AR5K_RF_BUFFER_CONTROL_4 0x98d4
02142
02143
02144
02145
02146 #define AR5K_RF_BUFFER_CONTROL_5 0x98d8
02147
02148
02149
02150
02151 #define AR5K_RF_BUFFER_CONTROL_6 0x98dc
02152
02153
02154
02155
02156 #define AR5K_PHY_RFSTG 0x98d4
02157 #define AR5K_PHY_RFSTG_DISABLE 0x00000021
02158
02159
02160
02161
02162 #define AR5K_PHY_BIN_MASK_1 0x9900
02163 #define AR5K_PHY_BIN_MASK_2 0x9904
02164 #define AR5K_PHY_BIN_MASK_3 0x9908
02165
02166 #define AR5K_PHY_BIN_MASK_CTL 0x990c
02167 #define AR5K_PHY_BIN_MASK_CTL_MASK_4 0x00003fff
02168 #define AR5K_PHY_BIN_MASK_CTL_MASK_4_S 0
02169 #define AR5K_PHY_BIN_MASK_CTL_RATE 0xff000000
02170 #define AR5K_PHY_BIN_MASK_CTL_RATE_S 24
02171
02172
02173
02174
02175 #define AR5K_PHY_ANT_CTL 0x9910
02176 #define AR5K_PHY_ANT_CTL_TXRX_EN 0x00000001
02177 #define AR5K_PHY_ANT_CTL_SECTORED_ANT 0x00000004
02178 #define AR5K_PHY_ANT_CTL_HITUNE5 0x00000008
02179 #define AR5K_PHY_ANT_CTL_SWTABLE_IDLE 0x000003f0
02180 #define AR5K_PHY_ANT_CTL_SWTABLE_IDLE_S 4
02181
02182
02183
02184
02185 #define AR5K_PHY_RX_DELAY 0x9914
02186 #define AR5K_PHY_RX_DELAY_M 0x00003fff
02187
02188
02189
02190
02191 #define AR5K_PHY_MAX_RX_LEN 0x991c
02192
02193
02194
02195
02196
02197 #define AR5K_PHY_IQ 0x9920
02198 #define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f
02199 #define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0
02200 #define AR5K_PHY_IQ_CORR_Q_I_COFF_S 5
02201 #define AR5K_PHY_IQ_CORR_ENABLE 0x00000800
02202 #define AR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000
02203 #define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 12
02204 #define AR5K_PHY_IQ_RUN 0x00010000
02205 #define AR5K_PHY_IQ_USE_PT_DF 0x00020000
02206 #define AR5K_PHY_IQ_EARLY_TRIG_THR 0x00200000
02207 #define AR5K_PHY_IQ_PILOT_MASK_EN 0x10000000
02208 #define AR5K_PHY_IQ_CHAN_MASK_EN 0x20000000
02209 #define AR5K_PHY_IQ_SPUR_FILT_EN 0x40000000
02210 #define AR5K_PHY_IQ_SPUR_RSSI_EN 0x80000000
02211
02212
02213
02214
02215
02216
02217 #define AR5K_PHY_OFDM_SELFCORR 0x9924
02218 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN 0x00000001
02219 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1 0x000000fe
02220 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_S 1
02221 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3 0x00000100
02222 #define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN 0x00008000
02223 #define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR 0x00010000
02224 #define AR5K_PHY_OFDM_SELFCORR_LSCTHR_HIRSSI 0x00800000
02225
02226
02227
02228
02229 #define AR5K_PHY_WARM_RESET 0x9928
02230
02231
02232
02233
02234 #define AR5K_PHY_CTL 0x992c
02235 #define AR5K_PHY_CTL_RX_DRAIN_RATE 0x00000001
02236 #define AR5K_PHY_CTL_LATE_TX_SIG_SYM 0x00000002
02237 #define AR5K_PHY_CTL_GEN_SCRAMBLER 0x00000004
02238 #define AR5K_PHY_CTL_TX_ANT_SEL 0x00000008
02239 #define AR5K_PHY_CTL_TX_ANT_STATIC 0x00000010
02240 #define AR5K_PHY_CTL_RX_ANT_SEL 0x00000020
02241 #define AR5K_PHY_CTL_RX_ANT_STATIC 0x00000040
02242 #define AR5K_PHY_CTL_LOW_FREQ_SLE_EN 0x00000080
02243
02244
02245
02246
02247 #define AR5K_PHY_PAPD_PROBE 0x9930
02248 #define AR5K_PHY_PAPD_PROBE_SH_HI_PAR 0x00000001
02249 #define AR5K_PHY_PAPD_PROBE_PCDAC_BIAS 0x00000002
02250 #define AR5K_PHY_PAPD_PROBE_COMP_GAIN 0x00000040
02251 #define AR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00
02252 #define AR5K_PHY_PAPD_PROBE_TXPOWER_S 9
02253 #define AR5K_PHY_PAPD_PROBE_TX_NEXT 0x00008000
02254 #define AR5K_PHY_PAPD_PROBE_PREDIST_EN 0x00010000
02255 #define AR5K_PHY_PAPD_PROBE_TYPE 0x01800000
02256 #define AR5K_PHY_PAPD_PROBE_TYPE_S 23
02257 #define AR5K_PHY_PAPD_PROBE_TYPE_OFDM 0
02258 #define AR5K_PHY_PAPD_PROBE_TYPE_XR 1
02259 #define AR5K_PHY_PAPD_PROBE_TYPE_CCK 2
02260 #define AR5K_PHY_PAPD_PROBE_GAINF 0xfe000000
02261 #define AR5K_PHY_PAPD_PROBE_GAINF_S 25
02262 #define AR5K_PHY_PAPD_PROBE_INI_5111 0x00004883
02263 #define AR5K_PHY_PAPD_PROBE_INI_5112 0x00004882
02264
02265
02266
02267
02268 #define AR5K_PHY_TXPOWER_RATE1 0x9934
02269 #define AR5K_PHY_TXPOWER_RATE2 0x9938
02270 #define AR5K_PHY_TXPOWER_RATE_MAX 0x993c
02271 #define AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE 0x00000040
02272 #define AR5K_PHY_TXPOWER_RATE3 0xa234
02273 #define AR5K_PHY_TXPOWER_RATE4 0xa238
02274
02275
02276
02277
02278 #define AR5K_PHY_FRAME_CTL_5210 0x9804
02279 #define AR5K_PHY_FRAME_CTL_5211 0x9944
02280 #define AR5K_PHY_FRAME_CTL (ah->ah_version == AR5K_AR5210 ? \
02281 AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211)
02282
02283 #define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038
02284 #define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3
02285 #define AR5K_PHY_FRAME_CTL_PREP_CHINFO 0x00010000
02286 #define AR5K_PHY_FRAME_CTL_EMU 0x80000000
02287 #define AR5K_PHY_FRAME_CTL_EMU_S 31
02288
02289 #define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000
02290 #define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000
02291 #define AR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000
02292 #define AR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000
02293 #define AR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000
02294 #define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000
02295 #define AR5K_PHY_FRAME_CTL_INI AR5K_PHY_FRAME_CTL_SERVICE_ERR | \
02296 AR5K_PHY_FRAME_CTL_TXURN_ERR | \
02297 AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \
02298 AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \
02299 AR5K_PHY_FRAME_CTL_PARITY_ERR | \
02300 AR5K_PHY_FRAME_CTL_TIMING_ERR
02301
02302
02303
02304
02305 #define AR5K_PHY_TX_PWR_ADJ 0x994c
02306 #define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA 0x00000fc0
02307 #define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA_S 6
02308 #define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX 0x00fc0000
02309 #define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX_S 18
02310
02311
02312
02313
02314 #define AR5K_PHY_RADAR 0x9954
02315 #define AR5K_PHY_RADAR_ENABLE 0x00000001
02316 #define AR5K_PHY_RADAR_DISABLE 0x00000000
02317 #define AR5K_PHY_RADAR_INBANDTHR 0x0000003e
02318
02319
02320 #define AR5K_PHY_RADAR_INBANDTHR_S 1
02321
02322 #define AR5K_PHY_RADAR_PRSSI_THR 0x00000fc0
02323
02324
02325 #define AR5K_PHY_RADAR_PRSSI_THR_S 6
02326
02327 #define AR5K_PHY_RADAR_PHEIGHT_THR 0x0003f000
02328
02329
02330 #define AR5K_PHY_RADAR_PHEIGHT_THR_S 12
02331
02332 #define AR5K_PHY_RADAR_RSSI_THR 0x00fc0000
02333
02334
02335 #define AR5K_PHY_RADAR_RSSI_THR_S 18
02336
02337 #define AR5K_PHY_RADAR_FIRPWR_THR 0x7f000000
02338
02339
02340
02341 #define AR5K_PHY_RADAR_FIRPWR_THRS 24
02342
02343
02344
02345
02346 #define AR5K_PHY_ANT_SWITCH_TABLE_0 0x9960
02347 #define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964
02348
02349
02350
02351
02352 #define AR5K_PHY_NFTHRES 0x9968
02353
02354
02355
02356
02357 #define AR5K_PHY_SIGMA_DELTA 0x996C
02358 #define AR5K_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
02359 #define AR5K_PHY_SIGMA_DELTA_ADC_SEL_S 0
02360 #define AR5K_PHY_SIGMA_DELTA_FILT2 0x000000f8
02361 #define AR5K_PHY_SIGMA_DELTA_FILT2_S 3
02362 #define AR5K_PHY_SIGMA_DELTA_FILT1 0x00001f00
02363 #define AR5K_PHY_SIGMA_DELTA_FILT1_S 8
02364 #define AR5K_PHY_SIGMA_DELTA_ADC_CLIP 0x01ffe000
02365 #define AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S 13
02366
02367
02368
02369
02370 #define AR5K_PHY_RESTART 0x9970
02371 #define AR5K_PHY_RESTART_DIV_GC 0x001c0000
02372 #define AR5K_PHY_RESTART_DIV_GC_S 18
02373
02374
02375
02376
02377 #define AR5K_PHY_RFBUS_REQ 0x997C
02378 #define AR5K_PHY_RFBUS_REQ_REQUEST 0x00000001
02379
02380
02381
02382
02383 #define AR5K_PHY_TIMING_7 0x9980
02384 #define AR5K_PHY_TIMING_8 0x9984
02385 #define AR5K_PHY_TIMING_8_PILOT_MASK_2 0x000fffff
02386 #define AR5K_PHY_TIMING_8_PILOT_MASK_2_S 0
02387
02388 #define AR5K_PHY_BIN_MASK2_1 0x9988
02389 #define AR5K_PHY_BIN_MASK2_2 0x998c
02390 #define AR5K_PHY_BIN_MASK2_3 0x9990
02391
02392 #define AR5K_PHY_BIN_MASK2_4 0x9994
02393 #define AR5K_PHY_BIN_MASK2_4_MASK_4 0x00003fff
02394 #define AR5K_PHY_BIN_MASK2_4_MASK_4_S 0
02395
02396 #define AR5K_PHY_TIMING_9 0x9998
02397 #define AR5K_PHY_TIMING_10 0x999c
02398 #define AR5K_PHY_TIMING_10_PILOT_MASK_2 0x000fffff
02399 #define AR5K_PHY_TIMING_10_PILOT_MASK_2_S 0
02400
02401
02402
02403
02404 #define AR5K_PHY_TIMING_11 0x99a0
02405 #define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE 0x000fffff
02406 #define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE_S 0
02407 #define AR5K_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000
02408 #define AR5K_PHY_TIMING_11_SPUR_FREQ_SD_S 20
02409 #define AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC 0x40000000
02410 #define AR5K_PHY_TIMING_11_USE_SPUR_IN_SELFCOR 0x80000000
02411
02412
02413
02414
02415 #define AR5K_BB_GAIN_BASE 0x9b00
02416 #define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2))
02417 #define AR5K_RF_GAIN_BASE 0x9a00
02418 #define AR5K_RF_GAIN(_n) (AR5K_RF_GAIN_BASE + ((_n) << 2))
02419
02420
02421
02422
02423 #define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10
02424 #define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14
02425 #define AR5K_PHY_IQRES_CAL_CORR 0x9c18
02426
02427
02428
02429
02430 #define AR5K_PHY_CURRENT_RSSI 0x9c1c
02431
02432
02433
02434
02435 #define AR5K_PHY_RFBUS_GRANT 0x9c20
02436 #define AR5K_PHY_RFBUS_GRANT_OK 0x00000001
02437
02438
02439
02440
02441 #define AR5K_PHY_ADC_TEST 0x9c24
02442 #define AR5K_PHY_ADC_TEST_I 0x00000001
02443 #define AR5K_PHY_ADC_TEST_Q 0x00000200
02444
02445
02446
02447
02448 #define AR5K_PHY_DAC_TEST 0x9c28
02449 #define AR5K_PHY_DAC_TEST_I 0x00000001
02450 #define AR5K_PHY_DAC_TEST_Q 0x00000200
02451
02452
02453
02454
02455 #define AR5K_PHY_PTAT 0x9c2c
02456
02457
02458
02459
02460 #define AR5K_PHY_BAD_TX_RATE 0x9c30
02461
02462
02463
02464
02465 #define AR5K_PHY_SPUR_PWR 0x9c34
02466 #define AR5K_PHY_SPUR_PWR_I 0x00000001
02467 #define AR5K_PHY_SPUR_PWR_Q 0x00000100
02468 #define AR5K_PHY_SPUR_PWR_FILT 0x00010000
02469
02470
02471
02472
02473 #define AR5K_PHY_CHAN_STATUS 0x9c38
02474 #define AR5K_PHY_CHAN_STATUS_BT_ACT 0x00000001
02475 #define AR5K_PHY_CHAN_STATUS_RX_CLR_RAW 0x00000002
02476 #define AR5K_PHY_CHAN_STATUS_RX_CLR_MAC 0x00000004
02477 #define AR5K_PHY_CHAN_STATUS_RX_CLR_PAP 0x00000008
02478
02479
02480
02481
02482 #define AR5K_PHY_HEAVY_CLIP_ENABLE 0x99e0
02483
02484
02485
02486
02487 #define AR5K_PHY_SCLOCK 0x99f0
02488 #define AR5K_PHY_SCLOCK_32MHZ 0x0000000c
02489 #define AR5K_PHY_SDELAY 0x99f4
02490 #define AR5K_PHY_SDELAY_32MHZ 0x000000ff
02491 #define AR5K_PHY_SPENDING 0x99f8
02492
02493
02494
02495
02496
02497
02498 #define AR5K_PHY_PAPD_I_BASE 0xa000
02499 #define AR5K_PHY_PAPD_I(_n) (AR5K_PHY_PAPD_I_BASE + ((_n) << 2))
02500
02501
02502
02503
02504 #define AR5K_PHY_PCDAC_TXPOWER_BASE 0xa180
02505 #define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2))
02506
02507
02508
02509
02510 #define AR5K_PHY_MODE 0x0a200
02511 #define AR5K_PHY_MODE_MOD 0x00000001
02512 #define AR5K_PHY_MODE_MOD_OFDM 0
02513 #define AR5K_PHY_MODE_MOD_CCK 1
02514 #define AR5K_PHY_MODE_FREQ 0x00000002
02515 #define AR5K_PHY_MODE_FREQ_5GHZ 0
02516 #define AR5K_PHY_MODE_FREQ_2GHZ 2
02517 #define AR5K_PHY_MODE_MOD_DYN 0x00000004
02518 #define AR5K_PHY_MODE_RAD 0x00000008
02519 #define AR5K_PHY_MODE_RAD_RF5111 0
02520 #define AR5K_PHY_MODE_RAD_RF5112 8
02521 #define AR5K_PHY_MODE_XR 0x00000010
02522 #define AR5K_PHY_MODE_HALF_RATE 0x00000020
02523 #define AR5K_PHY_MODE_QUARTER_RATE 0x00000040
02524
02525
02526
02527
02528 #define AR5K_PHY_CCKTXCTL 0xa204
02529 #define AR5K_PHY_CCKTXCTL_WORLD 0x00000000
02530 #define AR5K_PHY_CCKTXCTL_JAPAN 0x00000010
02531 #define AR5K_PHY_CCKTXCTL_SCRAMBLER_DIS 0x00000001
02532 #define AR5K_PHY_CCKTXCTK_DAC_SCALE 0x00000004
02533
02534
02535
02536
02537 #define AR5K_PHY_CCK_CROSSCORR 0xa208
02538 #define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR 0x0000003f
02539 #define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR_S 0
02540
02541
02542 #define AR5K_PHY_FAST_ANT_DIV 0xa208
02543 #define AR5K_PHY_FAST_ANT_DIV_EN 0x00002000
02544
02545
02546
02547
02548 #define AR5K_PHY_GAIN_2GHZ 0xa20c
02549 #define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000
02550 #define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S 18
02551 #define AR5K_PHY_GAIN_2GHZ_INI_5111 0x6480416c
02552
02553 #define AR5K_PHY_CCK_RX_CTL_4 0xa21c
02554 #define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT 0x01f80000
02555 #define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT_S 19
02556
02557 #define AR5K_PHY_DAG_CCK_CTL 0xa228
02558 #define AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR 0x00000200
02559 #define AR5K_PHY_DAG_CCK_CTL_RSSI_THR 0x0001fc00
02560 #define AR5K_PHY_DAG_CCK_CTL_RSSI_THR_S 10
02561
02562 #define AR5K_PHY_FAST_ADC 0xa24c
02563
02564 #define AR5K_PHY_BLUETOOTH 0xa254
02565
02566
02567
02568
02569
02570 #define AR5K_PHY_TPC_RG1 0xa258
02571 #define AR5K_PHY_TPC_RG1_NUM_PD_GAIN 0x0000c000
02572 #define AR5K_PHY_TPC_RG1_NUM_PD_GAIN_S 14
02573 #define AR5K_PHY_TPC_RG1_PDGAIN_1 0x00030000
02574 #define AR5K_PHY_TPC_RG1_PDGAIN_1_S 16
02575 #define AR5K_PHY_TPC_RG1_PDGAIN_2 0x000c0000
02576 #define AR5K_PHY_TPC_RG1_PDGAIN_2_S 18
02577 #define AR5K_PHY_TPC_RG1_PDGAIN_3 0x00300000
02578 #define AR5K_PHY_TPC_RG1_PDGAIN_3_S 20
02579
02580 #define AR5K_PHY_TPC_RG5 0xa26C
02581 #define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP 0x0000000F
02582 #define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP_S 0
02583 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1 0x000003F0
02584 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1_S 4
02585 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2 0x0000FC00
02586 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2_S 10
02587 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3 0x003F0000
02588 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3_S 16
02589 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4 0x0FC00000
02590 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S 22
02591
02592
02593
02594
02595 #define AR5K_PHY_PDADC_TXPOWER_BASE 0xa280
02596 #define AR5K_PHY_PDADC_TXPOWER(_n) (AR5K_PHY_PDADC_TXPOWER_BASE + ((_n) << 2))