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00020
00021
00022 #define AR5K_EEPROM_PCIE_OFFSET 0x02
00023 #define AR5K_EEPROM_PCIE_SERDES_SECTION 0x40
00024
00025 #define AR5K_EEPROM_MAGIC 0x003d
00026 #define AR5K_EEPROM_MAGIC_VALUE 0x5aa5
00027 #define AR5K_EEPROM_MAGIC_5212 0x0000145c
00028 #define AR5K_EEPROM_MAGIC_5211 0x0000145b
00029 #define AR5K_EEPROM_MAGIC_5210 0x0000145a
00030
00031 #define AR5K_EEPROM_IS_HB63 0x000b
00032
00033 #define AR5K_EEPROM_RFKILL 0x0f
00034 #define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c
00035 #define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2
00036 #define AR5K_EEPROM_RFKILL_POLARITY 0x00000002
00037 #define AR5K_EEPROM_RFKILL_POLARITY_S 1
00038
00039 #define AR5K_EEPROM_REG_DOMAIN 0x00bf
00040 #define AR5K_EEPROM_CHECKSUM 0x00c0
00041 #define AR5K_EEPROM_INFO_BASE 0x00c0
00042 #define AR5K_EEPROM_INFO_MAX (0x400 - AR5K_EEPROM_INFO_BASE)
00043 #define AR5K_EEPROM_INFO_CKSUM 0xffff
00044 #define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n))
00045
00046 #define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1)
00047 #define AR5K_EEPROM_VERSION_3_0 0x3000
00048 #define AR5K_EEPROM_VERSION_3_1 0x3001
00049 #define AR5K_EEPROM_VERSION_3_2 0x3002
00050 #define AR5K_EEPROM_VERSION_3_3 0x3003
00051 #define AR5K_EEPROM_VERSION_3_4 0x3004
00052 #define AR5K_EEPROM_VERSION_4_0 0x4000
00053 #define AR5K_EEPROM_VERSION_4_1 0x4001
00054 #define AR5K_EEPROM_VERSION_4_2 0x4002
00055 #define AR5K_EEPROM_VERSION_4_3 0x4003
00056 #define AR5K_EEPROM_VERSION_4_4 0x4004
00057 #define AR5K_EEPROM_VERSION_4_5 0x4005
00058 #define AR5K_EEPROM_VERSION_4_6 0x4006
00059 #define AR5K_EEPROM_VERSION_4_7 0x3007
00060 #define AR5K_EEPROM_VERSION_4_9 0x4009
00061 #define AR5K_EEPROM_VERSION_5_0 0x5000
00062 #define AR5K_EEPROM_VERSION_5_1 0x5001
00063 #define AR5K_EEPROM_VERSION_5_3 0x5003
00064
00065 #define AR5K_EEPROM_MODE_11A 0
00066 #define AR5K_EEPROM_MODE_11B 1
00067 #define AR5K_EEPROM_MODE_11G 2
00068
00069 #define AR5K_EEPROM_HDR AR5K_EEPROM_INFO(2)
00070 #define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1)
00071 #define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1)
00072 #define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1)
00073 #define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1)
00074 #define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f)
00075 #define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7)
00076 #define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1)
00077 #define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1)
00078
00079
00080 #define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \
00081 (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0)
00082
00083 #define AR5K_EEPROM_ANT_GAIN(_v) AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3)
00084 #define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) ((s8)(((_v) >> 8) & 0xff))
00085 #define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) ((s8)((_v) & 0xff))
00086
00087
00088 #define AR5K_EEPROM_MISC0 AR5K_EEPROM_INFO(4)
00089 #define AR5K_EEPROM_EARSTART(_v) ((_v) & 0xfff)
00090 #define AR5K_EEPROM_HDR_XR2_DIS(_v) (((_v) >> 12) & 0x1)
00091 #define AR5K_EEPROM_HDR_XR5_DIS(_v) (((_v) >> 13) & 0x1)
00092 #define AR5K_EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3)
00093
00094 #define AR5K_EEPROM_MISC1 AR5K_EEPROM_INFO(5)
00095 #define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff)
00096 #define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1)
00097 #define AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(_v) (((_v) >> 15) & 0x1)
00098
00099 #define AR5K_EEPROM_MISC2 AR5K_EEPROM_INFO(6)
00100 #define AR5K_EEPROM_EEP_FILE_VERSION(_v) (((_v) >> 8) & 0xff)
00101 #define AR5K_EEPROM_EAR_FILE_VERSION(_v) ((_v) & 0xff)
00102
00103 #define AR5K_EEPROM_MISC3 AR5K_EEPROM_INFO(7)
00104 #define AR5K_EEPROM_ART_BUILD_NUM(_v) (((_v) >> 10) & 0x3f)
00105 #define AR5K_EEPROM_EAR_FILE_ID(_v) ((_v) & 0xff)
00106
00107 #define AR5K_EEPROM_MISC4 AR5K_EEPROM_INFO(8)
00108 #define AR5K_EEPROM_CAL_DATA_START(_v) (((_v) >> 4) & 0xfff)
00109 #define AR5K_EEPROM_MASK_R0(_v) (((_v) >> 2) & 0x3)
00110 #define AR5K_EEPROM_MASK_R1(_v) ((_v) & 0x3)
00111
00112 #define AR5K_EEPROM_MISC5 AR5K_EEPROM_INFO(9)
00113 #define AR5K_EEPROM_COMP_DIS(_v) ((_v) & 0x1)
00114 #define AR5K_EEPROM_AES_DIS(_v) (((_v) >> 1) & 0x1)
00115 #define AR5K_EEPROM_FF_DIS(_v) (((_v) >> 2) & 0x1)
00116 #define AR5K_EEPROM_BURST_DIS(_v) (((_v) >> 3) & 0x1)
00117 #define AR5K_EEPROM_MAX_QCU(_v) (((_v) >> 4) & 0xf)
00118 #define AR5K_EEPROM_HEAVY_CLIP_EN(_v) (((_v) >> 8) & 0x1)
00119 #define AR5K_EEPROM_KEY_CACHE_SIZE(_v) (((_v) >> 12) & 0xf)
00120
00121 #define AR5K_EEPROM_MISC6 AR5K_EEPROM_INFO(10)
00122 #define AR5K_EEPROM_TX_CHAIN_DIS ((_v) & 0x8)
00123 #define AR5K_EEPROM_RX_CHAIN_DIS (((_v) >> 3) & 0x8)
00124 #define AR5K_EEPROM_FCC_MID_EN (((_v) >> 6) & 0x1)
00125 #define AR5K_EEPROM_JAP_U1EVEN_EN (((_v) >> 7) & 0x1)
00126 #define AR5K_EEPROM_JAP_U2_EN (((_v) >> 8) & 0x1)
00127 #define AR5K_EEPROM_JAP_U1ODD_EN (((_v) >> 9) & 0x1)
00128 #define AR5K_EEPROM_JAP_11A_NEW_EN (((_v) >> 10) & 0x1)
00129
00130
00131 #define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4)
00132 #define AR5K_EEPROM_MODES_11B(_v) AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2)
00133 #define AR5K_EEPROM_MODES_11G(_v) AR5K_EEPROM_OFF(_v, 0x00da, 0x010d)
00134 #define AR5K_EEPROM_CTL(_v) AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128)
00135 #define AR5K_EEPROM_GROUPS_START(_v) AR5K_EEPROM_OFF(_v, 0x0100, 0x0150)
00136 #define AR5K_EEPROM_GROUP1_OFFSET 0x0
00137 #define AR5K_EEPROM_GROUP2_OFFSET 0x5
00138 #define AR5K_EEPROM_GROUP3_OFFSET 0x37
00139 #define AR5K_EEPROM_GROUP4_OFFSET 0x46
00140 #define AR5K_EEPROM_GROUP5_OFFSET 0x55
00141 #define AR5K_EEPROM_GROUP6_OFFSET 0x65
00142 #define AR5K_EEPROM_GROUP7_OFFSET 0x69
00143 #define AR5K_EEPROM_GROUP8_OFFSET 0x6f
00144
00145 #define AR5K_EEPROM_TARGET_PWR_OFF_11A(_v) AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
00146 AR5K_EEPROM_GROUP5_OFFSET, 0x0000)
00147 #define AR5K_EEPROM_TARGET_PWR_OFF_11B(_v) AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
00148 AR5K_EEPROM_GROUP6_OFFSET, 0x0010)
00149 #define AR5K_EEPROM_TARGET_PWR_OFF_11G(_v) AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
00150 AR5K_EEPROM_GROUP7_OFFSET, 0x0014)
00151
00152
00153 #define AR5K_EEPROM_OBDB0_2GHZ 0x00ec
00154 #define AR5K_EEPROM_OBDB1_2GHZ 0x00ed
00155
00156 #define AR5K_EEPROM_PROTECT 0x003f
00157 #define AR5K_EEPROM_PROTECT_RD_0_31 0x0001
00158 #define AR5K_EEPROM_PROTECT_WR_0_31 0x0002
00159 #define AR5K_EEPROM_PROTECT_RD_32_63 0x0004
00160 #define AR5K_EEPROM_PROTECT_WR_32_63 0x0008
00161 #define AR5K_EEPROM_PROTECT_RD_64_127 0x0010
00162 #define AR5K_EEPROM_PROTECT_WR_64_127 0x0020
00163 #define AR5K_EEPROM_PROTECT_RD_128_191 0x0040
00164 #define AR5K_EEPROM_PROTECT_WR_128_191 0x0080
00165 #define AR5K_EEPROM_PROTECT_RD_192_207 0x0100
00166 #define AR5K_EEPROM_PROTECT_WR_192_207 0x0200
00167 #define AR5K_EEPROM_PROTECT_RD_208_223 0x0400
00168 #define AR5K_EEPROM_PROTECT_WR_208_223 0x0800
00169 #define AR5K_EEPROM_PROTECT_RD_224_239 0x1000
00170 #define AR5K_EEPROM_PROTECT_WR_224_239 0x2000
00171 #define AR5K_EEPROM_PROTECT_RD_240_255 0x4000
00172 #define AR5K_EEPROM_PROTECT_WR_240_255 0x8000
00173
00174
00175 #define AR5K_EEPROM_EEP_SCALE 100
00176 #define AR5K_EEPROM_EEP_DELTA 10
00177 #define AR5K_EEPROM_N_MODES 3
00178 #define AR5K_EEPROM_N_5GHZ_CHAN 10
00179 #define AR5K_EEPROM_N_2GHZ_CHAN 3
00180 #define AR5K_EEPROM_N_2GHZ_CHAN_2413 4
00181 #define AR5K_EEPROM_N_2GHZ_CHAN_MAX 4
00182 #define AR5K_EEPROM_MAX_CHAN 10
00183 #define AR5K_EEPROM_N_PWR_POINTS_5111 11
00184 #define AR5K_EEPROM_N_PCDAC 11
00185 #define AR5K_EEPROM_N_PHASE_CAL 5
00186 #define AR5K_EEPROM_N_TEST_FREQ 8
00187 #define AR5K_EEPROM_N_EDGES 8
00188 #define AR5K_EEPROM_N_INTERCEPTS 11
00189 #define AR5K_EEPROM_FREQ_M(_v) AR5K_EEPROM_OFF(_v, 0x7f, 0xff)
00190 #define AR5K_EEPROM_PCDAC_M 0x3f
00191 #define AR5K_EEPROM_PCDAC_START 1
00192 #define AR5K_EEPROM_PCDAC_STOP 63
00193 #define AR5K_EEPROM_PCDAC_STEP 1
00194 #define AR5K_EEPROM_NON_EDGE_M 0x40
00195 #define AR5K_EEPROM_CHANNEL_POWER 8
00196 #define AR5K_EEPROM_N_OBDB 4
00197 #define AR5K_EEPROM_OBDB_DIS 0xffff
00198 #define AR5K_EEPROM_CHANNEL_DIS 0xff
00199 #define AR5K_EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10)
00200 #define AR5K_EEPROM_N_CTLS(_v) AR5K_EEPROM_OFF(_v, 16, 32)
00201 #define AR5K_EEPROM_MAX_CTLS 32
00202 #define AR5K_EEPROM_N_PD_CURVES 4
00203 #define AR5K_EEPROM_N_XPD0_POINTS 4
00204 #define AR5K_EEPROM_N_XPD3_POINTS 3
00205 #define AR5K_EEPROM_N_PD_GAINS 4
00206 #define AR5K_EEPROM_N_PD_POINTS 5
00207 #define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35
00208 #define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55
00209 #define AR5K_EEPROM_POWER_M 0x3f
00210 #define AR5K_EEPROM_POWER_MIN 0
00211 #define AR5K_EEPROM_POWER_MAX 3150
00212 #define AR5K_EEPROM_POWER_STEP 50
00213 #define AR5K_EEPROM_POWER_TABLE_SIZE 64
00214 #define AR5K_EEPROM_N_POWER_LOC_11B 4
00215 #define AR5K_EEPROM_N_POWER_LOC_11G 6
00216 #define AR5K_EEPROM_I_GAIN 10
00217 #define AR5K_EEPROM_CCK_OFDM_DELTA 15
00218 #define AR5K_EEPROM_N_IQ_CAL 2
00219
00220 enum ath5k_eeprom_freq_bands{
00221 AR5K_EEPROM_BAND_5GHZ = 0,
00222 AR5K_EEPROM_BAND_2GHZ = 1,
00223 AR5K_EEPROM_N_FREQ_BANDS,
00224 };
00225
00226 #define AR5K_EEPROM_N_SPUR_CHANS 5
00227
00228 #define AR5K_EEPROM_5413_SPUR_CHAN_1 1640
00229
00230 #define AR5K_EEPROM_5413_SPUR_CHAN_2 1200
00231 #define AR5K_EEPROM_SPUR_CHAN_MASK 0x3FFF
00232 #define AR5K_EEPROM_NO_SPUR 0x8000
00233 #define AR5K_SPUR_CHAN_WIDTH 87
00234 #define AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz 3125
00235 #define AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz 6250
00236
00237 #define AR5K_EEPROM_READ(_o, _v) do { \
00238 ret = ath5k_hw_eeprom_read(ah, (_o), &(_v)); \
00239 if (ret) \
00240 return ret; \
00241 } while (0)
00242
00243 #define AR5K_EEPROM_READ_HDR(_o, _v) \
00244 AR5K_EEPROM_READ(_o, ah->ah_capabilities.cap_eeprom._v); \
00245
00246 enum ath5k_ant_table {
00247 AR5K_ANT_CTL = 0,
00248 AR5K_ANT_SWTABLE_A = 1,
00249 AR5K_ANT_SWTABLE_B = 2,
00250 AR5K_ANT_MAX,
00251 };
00252
00253 enum ath5k_ctl_mode {
00254 AR5K_CTL_11A = 0,
00255 AR5K_CTL_11B = 1,
00256 AR5K_CTL_11G = 2,
00257 AR5K_CTL_TURBO = 3,
00258 AR5K_CTL_TURBOG = 4,
00259 AR5K_CTL_2GHT20 = 5,
00260 AR5K_CTL_5GHT20 = 6,
00261 AR5K_CTL_2GHT40 = 7,
00262 AR5K_CTL_5GHT40 = 8,
00263 AR5K_CTL_MODE_M = 15,
00264 };
00265
00266
00267
00268
00269
00270
00271
00272
00273
00274
00275 #define AR5K_CTL_FCC 0x10
00276 #define AR5K_CTL_CUSTOM 0x20
00277 #define AR5K_CTL_ETSI 0x30
00278 #define AR5K_CTL_MKK 0x40
00279
00280
00281
00282
00283
00284 #define AR5K_CTL_NO_REGDOMAIN 0xf0
00285
00286
00287 #define AR5K_CTL_NO_CTL 0xff
00288
00289
00290 struct ath5k_chan_pcal_info_rf5111 {
00291
00292
00293 u8 pwr[AR5K_EEPROM_N_PWR_POINTS_5111];
00294
00295
00296 u8 pcdac[AR5K_EEPROM_N_PWR_POINTS_5111];
00297
00298 u8 pcdac_min;
00299
00300 u8 pcdac_max;
00301 };
00302
00303 struct ath5k_chan_pcal_info_rf5112 {
00304
00305
00306
00307 s8 pwr_x0[AR5K_EEPROM_N_XPD0_POINTS];
00308 s8 pwr_x3[AR5K_EEPROM_N_XPD3_POINTS];
00309
00310
00311 u8 pcdac_x0[AR5K_EEPROM_N_XPD0_POINTS];
00312 u8 pcdac_x3[AR5K_EEPROM_N_XPD3_POINTS];
00313 };
00314
00315 struct ath5k_chan_pcal_info_rf2413 {
00316
00317 s8 pwr_i[AR5K_EEPROM_N_PD_GAINS];
00318 u8 pddac_i[AR5K_EEPROM_N_PD_GAINS];
00319
00320
00321 s8 pwr[AR5K_EEPROM_N_PD_GAINS]
00322 [AR5K_EEPROM_N_PD_POINTS];
00323 u8 pddac[AR5K_EEPROM_N_PD_GAINS]
00324 [AR5K_EEPROM_N_PD_POINTS];
00325 };
00326
00327 enum ath5k_powertable_type {
00328 AR5K_PWRTABLE_PWR_TO_PCDAC = 0,
00329 AR5K_PWRTABLE_LINEAR_PCDAC = 1,
00330 AR5K_PWRTABLE_PWR_TO_PDADC = 2,
00331 };
00332
00333 struct ath5k_pdgain_info {
00334 u8 pd_points;
00335 u8 *pd_step;
00336
00337
00338 s16 *pd_pwr;
00339 };
00340
00341 struct ath5k_chan_pcal_info {
00342
00343 u16 freq;
00344
00345 s16 max_pwr;
00346 s16 min_pwr;
00347 union {
00348 struct ath5k_chan_pcal_info_rf5111 rf5111_info;
00349 struct ath5k_chan_pcal_info_rf5112 rf5112_info;
00350 struct ath5k_chan_pcal_info_rf2413 rf2413_info;
00351 };
00352
00353
00354
00355 struct ath5k_pdgain_info *pd_curves;
00356 };
00357
00358
00359
00360
00361 struct ath5k_rate_pcal_info {
00362 u16 freq;
00363
00364
00365 u16 target_power_6to24;
00366
00367
00368 u16 target_power_36;
00369
00370
00371 u16 target_power_48;
00372
00373
00374 u16 target_power_54;
00375 };
00376
00377
00378 struct ath5k_edge_power {
00379 u16 freq;
00380 u16 edge;
00381 bool flag;
00382 };
00383
00384
00385 struct ath5k_eeprom_info {
00386
00387
00388 u16 ee_magic;
00389 u16 ee_protect;
00390 u16 ee_regdomain;
00391 u16 ee_version;
00392 u16 ee_header;
00393 u16 ee_ant_gain;
00394 u8 ee_rfkill_pin;
00395 bool ee_rfkill_pol;
00396 bool ee_is_hb63;
00397 bool ee_serdes;
00398 u16 ee_misc0;
00399 u16 ee_misc1;
00400 u16 ee_misc2;
00401 u16 ee_misc3;
00402 u16 ee_misc4;
00403 u16 ee_misc5;
00404 u16 ee_misc6;
00405 u16 ee_cck_ofdm_gain_delta;
00406 u16 ee_cck_ofdm_power_delta;
00407 u16 ee_scaled_cck_delta;
00408
00409
00410 u16 ee_i_cal[AR5K_EEPROM_N_MODES];
00411 u16 ee_q_cal[AR5K_EEPROM_N_MODES];
00412 u16 ee_fixed_bias[AR5K_EEPROM_N_MODES];
00413 u16 ee_turbo_max_power[AR5K_EEPROM_N_MODES];
00414 u16 ee_xr_power[AR5K_EEPROM_N_MODES];
00415 u16 ee_switch_settling[AR5K_EEPROM_N_MODES];
00416 u16 ee_atn_tx_rx[AR5K_EEPROM_N_MODES];
00417 u16 ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC];
00418 u16 ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
00419 u16 ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
00420 u16 ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES];
00421 u16 ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES];
00422 u16 ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES];
00423 u16 ee_thr_62[AR5K_EEPROM_N_MODES];
00424 u16 ee_xlna_gain[AR5K_EEPROM_N_MODES];
00425 u16 ee_xpd[AR5K_EEPROM_N_MODES];
00426 u16 ee_x_gain[AR5K_EEPROM_N_MODES];
00427 u16 ee_i_gain[AR5K_EEPROM_N_MODES];
00428 u16 ee_margin_tx_rx[AR5K_EEPROM_N_MODES];
00429 u16 ee_switch_settling_turbo[AR5K_EEPROM_N_MODES];
00430 u16 ee_margin_tx_rx_turbo[AR5K_EEPROM_N_MODES];
00431 u16 ee_atn_tx_rx_turbo[AR5K_EEPROM_N_MODES];
00432
00433
00434 u16 ee_false_detect[AR5K_EEPROM_N_MODES];
00435
00436
00437 u8 ee_pd_gains[AR5K_EEPROM_N_MODES];
00438
00439 u8 ee_pdc_to_idx[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PD_GAINS];
00440
00441 u8 ee_n_piers[AR5K_EEPROM_N_MODES];
00442 struct ath5k_chan_pcal_info ee_pwr_cal_a[AR5K_EEPROM_N_5GHZ_CHAN];
00443 struct ath5k_chan_pcal_info ee_pwr_cal_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
00444 struct ath5k_chan_pcal_info ee_pwr_cal_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
00445
00446
00447 u8 ee_rate_target_pwr_num[AR5K_EEPROM_N_MODES];
00448 struct ath5k_rate_pcal_info ee_rate_tpwr_a[AR5K_EEPROM_N_5GHZ_CHAN];
00449 struct ath5k_rate_pcal_info ee_rate_tpwr_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
00450 struct ath5k_rate_pcal_info ee_rate_tpwr_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
00451
00452
00453 u8 ee_ctls;
00454 u8 ee_ctl[AR5K_EEPROM_MAX_CTLS];
00455 struct ath5k_edge_power ee_ctl_pwr[AR5K_EEPROM_N_EDGES * AR5K_EEPROM_MAX_CTLS];
00456
00457
00458 s16 ee_noise_floor_thr[AR5K_EEPROM_N_MODES];
00459 s8 ee_adc_desired_size[AR5K_EEPROM_N_MODES];
00460 s8 ee_pga_desired_size[AR5K_EEPROM_N_MODES];
00461 s8 ee_adc_desired_size_turbo[AR5K_EEPROM_N_MODES];
00462 s8 ee_pga_desired_size_turbo[AR5K_EEPROM_N_MODES];
00463 s8 ee_pd_gain_overlap;
00464
00465
00466 u16 ee_spur_chans[AR5K_EEPROM_N_SPUR_CHANS][AR5K_EEPROM_N_FREQ_BANDS];
00467
00468
00469 u32 ee_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
00470 };
00471