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00018 #ifndef _ATH5K_H
00019 #define _ATH5K_H
00020 #include <asm/delay.h>
00021 #include <linux/delay.h>
00022 #include <linux/io.h>
00023 #include <linux/types.h>
00024 #include "mac80211.h"
00025
00026
00027
00028 #include "desc.h"
00029
00030
00031
00032
00033 #include "eeprom.h"
00034
00035
00036 #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007
00037 #define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011
00038 #define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012
00039 #define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013
00040 #define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013
00041 #define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013
00042 #define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207
00043 #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014
00044 #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107
00045 #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113
00046 #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112
00047 #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013
00048 #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12
00049 #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b
00050 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052
00051 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057
00052 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058
00053 #define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014
00054 #define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015
00055 #define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016
00056 #define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017
00057 #define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018
00058 #define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019
00059 #define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a
00060 #define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b
00061 #define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c
00062 #define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023
00063 #define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024
00064
00065
00066
00067
00068
00069 #define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__)
00070
00071 #define ATH5K_INFO(_sc, _fmt, ...) \
00072 printk("ath5k info:" _fmt, ##__VA_ARGS__)
00073
00074 #define ATH5K_WARN(_sc, _fmt, ...) \
00075 printk("ath5k warn:" _fmt, ##__VA_ARGS__)
00076
00077 #define ATH5K_ERR(_sc, _fmt, ...) \
00078 printk("ath5k error:" _fmt, ##__VA_ARGS__)
00079
00080
00081
00082
00083
00084
00085
00086
00087 #define AR5K_REG_SM(_val, _flags) \
00088 (((_val) << _flags##_S) & (_flags))
00089
00090
00091 #define AR5K_REG_MS(_val, _flags) \
00092 (((_val) & (_flags)) >> _flags##_S)
00093
00094
00095
00096
00097
00098
00099 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \
00100 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
00101 (((_val) << _flags##_S) & (_flags)), _reg)
00102
00103 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \
00104 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
00105 (_mask)) | (_flags), _reg)
00106
00107 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \
00108 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
00109
00110 #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \
00111 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
00112
00113
00114 #define AR5K_PHY_READ(ah, _reg) \
00115 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
00116
00117 #define AR5K_PHY_WRITE(ah, _reg, _val) \
00118 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
00119
00120
00121 #define AR5K_REG_READ_Q(ah, _reg, _queue) \
00122 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
00123
00124 #define AR5K_REG_WRITE_Q(ah, _reg, _queue) \
00125 ath5k_hw_reg_write(ah, (1 << _queue), _reg)
00126
00127 #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
00128 _reg |= 1 << _queue; \
00129 } while (0)
00130
00131 #define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
00132 _reg &= ~(1 << _queue); \
00133 } while (0)
00134
00135
00136 #define AR5K_REG_WAIT(_i) do { \
00137 if (_i % 64) \
00138 udelay(1); \
00139 } while (0)
00140
00141
00142 #define AR5K_INI_RFGAIN_5GHZ 0
00143 #define AR5K_INI_RFGAIN_2GHZ 1
00144
00145
00146 #define AR5K_INI_VAL_11A 0
00147 #define AR5K_INI_VAL_11A_TURBO 1
00148 #define AR5K_INI_VAL_11B 2
00149 #define AR5K_INI_VAL_11G 3
00150 #define AR5K_INI_VAL_11G_TURBO 4
00151 #define AR5K_INI_VAL_XR 0
00152 #define AR5K_INI_VAL_MAX 5
00153
00154
00155 #define AR5K_LOW_ID(_a)( \
00156 (_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \
00157 )
00158
00159 #define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8)
00160
00161
00162
00163
00164
00165 #define AR5K_TUNE_DMA_BEACON_RESP 2
00166 #define AR5K_TUNE_SW_BEACON_RESP 10
00167 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
00168 #define AR5K_TUNE_RADAR_ALERT false
00169 #define AR5K_TUNE_MIN_TX_FIFO_THRES 1
00170 #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1)
00171 #define AR5K_TUNE_REGISTER_TIMEOUT 20000
00172
00173
00174 #define AR5K_TUNE_RSSI_THRES 129
00175
00176
00177
00178
00179
00180 #define AR5K_TUNE_BMISS_THRES 7
00181 #define AR5K_TUNE_REGISTER_DWELL_TIME 20000
00182 #define AR5K_TUNE_BEACON_INTERVAL 100
00183 #define AR5K_TUNE_AIFS 2
00184 #define AR5K_TUNE_AIFS_11B 2
00185 #define AR5K_TUNE_AIFS_XR 0
00186 #define AR5K_TUNE_CWMIN 15
00187 #define AR5K_TUNE_CWMIN_11B 31
00188 #define AR5K_TUNE_CWMIN_XR 3
00189 #define AR5K_TUNE_CWMAX 1023
00190 #define AR5K_TUNE_CWMAX_11B 1023
00191 #define AR5K_TUNE_CWMAX_XR 7
00192 #define AR5K_TUNE_NOISE_FLOOR -72
00193 #define AR5K_TUNE_MAX_TXPOWER 63
00194 #define AR5K_TUNE_DEFAULT_TXPOWER 25
00195 #define AR5K_TUNE_TPC_TXPOWER false
00196 #define AR5K_TUNE_HWTXTRIES 0
00197
00198 #define AR5K_INIT_CARR_SENSE_EN 1
00199
00200
00201 #if defined(__BIG_ENDIAN)
00202 #define AR5K_INIT_CFG ( \
00203 AR5K_CFG_SWTD | AR5K_CFG_SWRD \
00204 )
00205 #else
00206 #define AR5K_INIT_CFG 0x00000000
00207 #endif
00208
00209
00210 #define AR5K_INIT_CYCRSSI_THR1 2
00211 #define AR5K_INIT_TX_LATENCY 502
00212 #define AR5K_INIT_USEC 39
00213 #define AR5K_INIT_USEC_TURBO 79
00214 #define AR5K_INIT_USEC_32 31
00215 #define AR5K_INIT_SLOT_TIME 396
00216 #define AR5K_INIT_SLOT_TIME_TURBO 480
00217 #define AR5K_INIT_ACK_CTS_TIMEOUT 1024
00218 #define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
00219 #define AR5K_INIT_PROG_IFS 920
00220 #define AR5K_INIT_PROG_IFS_TURBO 960
00221 #define AR5K_INIT_EIFS 3440
00222 #define AR5K_INIT_EIFS_TURBO 6880
00223 #define AR5K_INIT_SIFS 560
00224 #define AR5K_INIT_SIFS_TURBO 480
00225 #define AR5K_INIT_SH_RETRY 10
00226 #define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY
00227 #define AR5K_INIT_SSH_RETRY 32
00228 #define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY
00229 #define AR5K_INIT_TX_RETRY 10
00230
00231 #define AR5K_INIT_TRANSMIT_LATENCY ( \
00232 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
00233 (AR5K_INIT_USEC) \
00234 )
00235 #define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \
00236 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
00237 (AR5K_INIT_USEC_TURBO) \
00238 )
00239 #define AR5K_INIT_PROTO_TIME_CNTRL ( \
00240 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \
00241 (AR5K_INIT_PROG_IFS) \
00242 )
00243 #define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \
00244 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \
00245 (AR5K_INIT_PROG_IFS_TURBO) \
00246 )
00247
00248
00249 #define AR5K_TXQ_USEDEFAULT ((u32) -1)
00250
00251
00252
00253
00254 enum ath5k_version {
00255 AR5K_AR5210 = 0,
00256 AR5K_AR5211 = 1,
00257 AR5K_AR5212 = 2,
00258 };
00259
00260
00261 enum ath5k_radio {
00262 AR5K_RF5110 = 0,
00263 AR5K_RF5111 = 1,
00264 AR5K_RF5112 = 2,
00265 AR5K_RF2413 = 3,
00266 AR5K_RF5413 = 4,
00267 AR5K_RF2316 = 5,
00268 AR5K_RF2317 = 6,
00269 AR5K_RF2425 = 7,
00270 };
00271
00272
00273
00274
00275
00276 enum ath5k_srev_type {
00277 AR5K_VERSION_MAC,
00278 AR5K_VERSION_RAD,
00279 };
00280
00281 struct ath5k_srev_name {
00282 const char *sr_name;
00283 enum ath5k_srev_type sr_type;
00284 u_int sr_val;
00285 };
00286
00287 #define AR5K_SREV_UNKNOWN 0xffff
00288
00289 #define AR5K_SREV_AR5210 0x00
00290 #define AR5K_SREV_AR5311 0x10
00291 #define AR5K_SREV_AR5311A 0x20
00292 #define AR5K_SREV_AR5311B 0x30
00293 #define AR5K_SREV_AR5211 0x40
00294 #define AR5K_SREV_AR5212 0x50
00295 #define AR5K_SREV_AR5212_V4 0x54
00296 #define AR5K_SREV_AR5213 0x55
00297 #define AR5K_SREV_AR5213A 0x59
00298 #define AR5K_SREV_AR2413 0x78
00299 #define AR5K_SREV_AR2414 0x70
00300 #define AR5K_SREV_AR5424 0x90
00301 #define AR5K_SREV_AR5413 0xa4
00302 #define AR5K_SREV_AR5414 0xa0
00303 #define AR5K_SREV_AR2415 0xb0
00304 #define AR5K_SREV_AR5416 0xc0
00305 #define AR5K_SREV_AR5418 0xca
00306 #define AR5K_SREV_AR2425 0xe0
00307 #define AR5K_SREV_AR2417 0xf0
00308
00309 #define AR5K_SREV_RAD_5110 0x00
00310 #define AR5K_SREV_RAD_5111 0x10
00311 #define AR5K_SREV_RAD_5111A 0x15
00312 #define AR5K_SREV_RAD_2111 0x20
00313 #define AR5K_SREV_RAD_5112 0x30
00314 #define AR5K_SREV_RAD_5112A 0x35
00315 #define AR5K_SREV_RAD_5112B 0x36
00316 #define AR5K_SREV_RAD_2112 0x40
00317 #define AR5K_SREV_RAD_2112A 0x45
00318 #define AR5K_SREV_RAD_2112B 0x46
00319 #define AR5K_SREV_RAD_2413 0x50
00320 #define AR5K_SREV_RAD_5413 0x60
00321 #define AR5K_SREV_RAD_2316 0x70
00322 #define AR5K_SREV_RAD_2317 0x80
00323 #define AR5K_SREV_RAD_5424 0xa0
00324 #define AR5K_SREV_RAD_2425 0xa2
00325 #define AR5K_SREV_RAD_5133 0xc0
00326
00327 #define AR5K_SREV_PHY_5211 0x30
00328 #define AR5K_SREV_PHY_5212 0x41
00329 #define AR5K_SREV_PHY_5212A 0x42
00330 #define AR5K_SREV_PHY_5212B 0x43
00331 #define AR5K_SREV_PHY_2413 0x45
00332 #define AR5K_SREV_PHY_5413 0x61
00333 #define AR5K_SREV_PHY_2425 0x70
00334
00335
00336 #define IEEE80211_MAX_LEN 2500
00337
00338
00339
00340
00341
00342
00343
00344
00345
00346
00347
00348
00349
00350
00351
00352
00353
00354
00355
00356 #define MODULATION_XR 0x00000200
00357
00358
00359
00360
00361
00362
00363
00364
00365
00366
00367
00368
00369
00370
00371
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00374
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00380
00381
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00383
00384
00385
00386
00387
00388
00389
00390
00391
00392
00393
00394
00395 #define MODULATION_TURBO 0x00000080
00396
00397 enum ath5k_driver_mode {
00398 AR5K_MODE_11A = 0,
00399 AR5K_MODE_11A_TURBO = 1,
00400 AR5K_MODE_11B = 2,
00401 AR5K_MODE_11G = 3,
00402 AR5K_MODE_11G_TURBO = 4,
00403 AR5K_MODE_XR = 0,
00404 AR5K_MODE_MAX = 5
00405 };
00406
00407
00408
00409
00410
00411
00412
00413
00414
00415 struct ath5k_tx_status {
00416 u16 ts_seqnum;
00417 u16 ts_tstamp;
00418 u8 ts_status;
00419 u8 ts_rate[4];
00420 u8 ts_retry[4];
00421 u8 ts_final_idx;
00422 s8 ts_rssi;
00423 u8 ts_shortretry;
00424 u8 ts_longretry;
00425 u8 ts_virtcol;
00426 u8 ts_antenna;
00427 };
00428
00429 #define AR5K_TXSTAT_ALTRATE 0x80
00430 #define AR5K_TXERR_XRETRY 0x01
00431 #define AR5K_TXERR_FILT 0x02
00432 #define AR5K_TXERR_FIFO 0x04
00433
00443 enum ath5k_tx_queue {
00444 AR5K_TX_QUEUE_INACTIVE = 0,
00445 AR5K_TX_QUEUE_DATA,
00446 AR5K_TX_QUEUE_XR_DATA,
00447 AR5K_TX_QUEUE_BEACON,
00448 AR5K_TX_QUEUE_CAB,
00449 AR5K_TX_QUEUE_UAPSD,
00450 };
00451
00452 #define AR5K_NUM_TX_QUEUES 10
00453 #define AR5K_NUM_TX_QUEUES_NOQCU 2
00454
00455
00456
00457
00458
00459
00460
00461
00462 enum ath5k_tx_queue_subtype {
00463 AR5K_WME_AC_BK = 0,
00464 AR5K_WME_AC_BE,
00465 AR5K_WME_AC_VI,
00466 AR5K_WME_AC_VO,
00467 };
00468
00469
00470
00471
00472
00473
00474
00475 enum ath5k_tx_queue_id {
00476 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,
00477 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1,
00478 AR5K_TX_QUEUE_ID_DATA_MIN = 0,
00479 AR5K_TX_QUEUE_ID_DATA_MAX = 4,
00480 AR5K_TX_QUEUE_ID_DATA_SVP = 5,
00481 AR5K_TX_QUEUE_ID_CAB = 6,
00482 AR5K_TX_QUEUE_ID_BEACON = 7,
00483 AR5K_TX_QUEUE_ID_UAPSD = 8,
00484 AR5K_TX_QUEUE_ID_XR_DATA = 9,
00485 };
00486
00487
00488
00489
00490 #define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001
00491 #define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002
00492 #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004
00493 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008
00494 #define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010
00495 #define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020
00496 #define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040
00497 #define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080
00498 #define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100
00499 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200
00500 #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300
00501 #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800
00502 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000
00503 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000
00504
00505
00506
00507
00508 struct ath5k_txq_info {
00509 enum ath5k_tx_queue tqi_type;
00510 enum ath5k_tx_queue_subtype tqi_subtype;
00511 u16 tqi_flags;
00512 u32 tqi_aifs;
00513 s32 tqi_cw_min;
00514 s32 tqi_cw_max;
00515 u32 tqi_cbr_period;
00516 u32 tqi_cbr_overflow_limit;
00517 u32 tqi_burst_time;
00518 u32 tqi_ready_time;
00519 };
00520
00521
00522
00523
00524
00525
00526 enum ath5k_pkt_type {
00527 AR5K_PKT_TYPE_NORMAL = 0,
00528 AR5K_PKT_TYPE_ATIM = 1,
00529 AR5K_PKT_TYPE_PSPOLL = 2,
00530 AR5K_PKT_TYPE_BEACON = 3,
00531 AR5K_PKT_TYPE_PROBE_RESP = 4,
00532 AR5K_PKT_TYPE_PIFS = 5,
00533 };
00534
00535
00536
00537
00538 #define AR5K_TXPOWER_OFDM(_r, _v) ( \
00539 ((0 & 1) << ((_v) + 6)) | \
00540 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
00541 )
00542
00543 #define AR5K_TXPOWER_CCK(_r, _v) ( \
00544 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
00545 )
00546
00547
00548
00549
00550 enum ath5k_dmasize {
00551 AR5K_DMASIZE_4B = 0,
00552 AR5K_DMASIZE_8B,
00553 AR5K_DMASIZE_16B,
00554 AR5K_DMASIZE_32B,
00555 AR5K_DMASIZE_64B,
00556 AR5K_DMASIZE_128B,
00557 AR5K_DMASIZE_256B,
00558 AR5K_DMASIZE_512B
00559 };
00560
00561
00562
00563
00564
00565
00566
00567
00568
00569 struct ath5k_rx_status {
00570 u16 rs_datalen;
00571 u16 rs_tstamp;
00572 u8 rs_status;
00573 u8 rs_phyerr;
00574 s8 rs_rssi;
00575 u8 rs_keyix;
00576 u8 rs_rate;
00577 u8 rs_antenna;
00578 u8 rs_more;
00579 };
00580
00581 #define AR5K_RXERR_CRC 0x01
00582 #define AR5K_RXERR_PHY 0x02
00583 #define AR5K_RXERR_FIFO 0x04
00584 #define AR5K_RXERR_DECRYPT 0x08
00585 #define AR5K_RXERR_MIC 0x10
00586 #define AR5K_RXKEYIX_INVALID ((u8) - 1)
00587 #define AR5K_TXKEYIX_INVALID ((u32) - 1)
00588
00589
00590
00591
00592
00593
00594 #define AR5K_BEACON_PERIOD 0x0000ffff
00595 #define AR5K_BEACON_ENA 0x00800000
00596 #define AR5K_BEACON_RESET_TSF 0x01000000
00597
00598 #if 0
00599
00605 struct ath5k_beacon_state {
00606 u32 bs_next_beacon;
00607 u32 bs_next_dtim;
00608 u32 bs_interval;
00609 u8 bs_dtim_period;
00610 u8 bs_cfp_period;
00611 u16 bs_cfp_max_duration;
00612 u16 bs_cfp_du_remain;
00613 u16 bs_tim_offset;
00614 u16 bs_sleep_duration;
00615 u16 bs_bmiss_threshold;
00616 u32 bs_cfp_next;
00617 };
00618 #endif
00619
00620
00621
00622
00623
00624
00625
00626
00627
00628 #define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
00629
00630
00631
00632
00633
00634
00635 enum ath5k_rfgain {
00636 AR5K_RFGAIN_INACTIVE = 0,
00637 AR5K_RFGAIN_ACTIVE,
00638 AR5K_RFGAIN_READ_REQUESTED,
00639 AR5K_RFGAIN_NEED_CHANGE,
00640 };
00641
00642 struct ath5k_gain {
00643 u8 g_step_idx;
00644 u8 g_current;
00645 u8 g_target;
00646 u8 g_low;
00647 u8 g_high;
00648 u8 g_f_corr;
00649 u8 g_state;
00650 };
00651
00652
00653
00654
00655
00656 #define AR5K_SLOT_TIME_9 396
00657 #define AR5K_SLOT_TIME_20 880
00658 #define AR5K_SLOT_TIME_MAX 0xffff
00659
00660
00661 #define CHANNEL_CW_INT 0x0008
00662 #define CHANNEL_TURBO 0x0010
00663 #define CHANNEL_CCK 0x0020
00664 #define CHANNEL_OFDM 0x0040
00665 #define CHANNEL_2GHZ 0x0080
00666 #define CHANNEL_5GHZ 0x0100
00667 #define CHANNEL_PASSIVE 0x0200
00668 #define CHANNEL_DYN 0x0400
00669 #define CHANNEL_XR 0x0800
00670
00671 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
00672 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
00673 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
00674 #define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
00675 #define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
00676 #define CHANNEL_108A CHANNEL_T
00677 #define CHANNEL_108G CHANNEL_TG
00678 #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
00679
00680 #define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
00681 CHANNEL_TURBO)
00682
00683 #define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO)
00684 #define CHANNEL_MODES CHANNEL_ALL
00685
00686
00687
00688
00689
00690 #define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0)
00691 #define IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0)
00692
00693
00694
00695
00696
00697
00698 struct ath5k_athchan_2ghz {
00699 u32 a2_flags;
00700 u16 a2_athchan;
00701 };
00702
00703
00704
00705
00706
00707
00736 #define AR5K_MAX_RATES 32
00737
00738
00739 #define ATH5K_RATE_CODE_1M 0x1B
00740 #define ATH5K_RATE_CODE_2M 0x1A
00741 #define ATH5K_RATE_CODE_5_5M 0x19
00742 #define ATH5K_RATE_CODE_11M 0x18
00743
00744 #define ATH5K_RATE_CODE_6M 0x0B
00745 #define ATH5K_RATE_CODE_9M 0x0F
00746 #define ATH5K_RATE_CODE_12M 0x0A
00747 #define ATH5K_RATE_CODE_18M 0x0E
00748 #define ATH5K_RATE_CODE_24M 0x09
00749 #define ATH5K_RATE_CODE_36M 0x0D
00750 #define ATH5K_RATE_CODE_48M 0x08
00751 #define ATH5K_RATE_CODE_54M 0x0C
00752
00753 #define ATH5K_RATE_CODE_XR_500K 0x07
00754 #define ATH5K_RATE_CODE_XR_1M 0x02
00755 #define ATH5K_RATE_CODE_XR_2M 0x06
00756 #define ATH5K_RATE_CODE_XR_3M 0x01
00757
00758
00759 #define AR5K_SET_SHORT_PREAMBLE 0x04
00760
00761
00762
00763
00764
00765 #define AR5K_KEYCACHE_SIZE 8
00766
00767
00768
00769
00770
00771
00772
00773
00774 #define AR5K_RSSI_EP_MULTIPLIER (1<<7)
00775
00776 #define AR5K_ASSERT_ENTRY(_e, _s) do { \
00777 if (_e >= _s) \
00778 return (false); \
00779 } while (0)
00780
00781
00782
00783
00784
00837 enum ath5k_int {
00838 AR5K_INT_RXOK = 0x00000001,
00839 AR5K_INT_RXDESC = 0x00000002,
00840 AR5K_INT_RXERR = 0x00000004,
00841 AR5K_INT_RXNOFRM = 0x00000008,
00842 AR5K_INT_RXEOL = 0x00000010,
00843 AR5K_INT_RXORN = 0x00000020,
00844 AR5K_INT_TXOK = 0x00000040,
00845 AR5K_INT_TXDESC = 0x00000080,
00846 AR5K_INT_TXERR = 0x00000100,
00847 AR5K_INT_TXNOFRM = 0x00000200,
00848 AR5K_INT_TXEOL = 0x00000400,
00849 AR5K_INT_TXURN = 0x00000800,
00850 AR5K_INT_MIB = 0x00001000,
00851 AR5K_INT_SWI = 0x00002000,
00852 AR5K_INT_RXPHY = 0x00004000,
00853 AR5K_INT_RXKCM = 0x00008000,
00854 AR5K_INT_SWBA = 0x00010000,
00855 AR5K_INT_BRSSI = 0x00020000,
00856 AR5K_INT_BMISS = 0x00040000,
00857 AR5K_INT_FATAL = 0x00080000,
00858 AR5K_INT_BNR = 0x00100000,
00859 AR5K_INT_TIM = 0x00200000,
00860 AR5K_INT_DTIM = 0x00400000,
00861 AR5K_INT_DTIM_SYNC = 0x00800000,
00862 AR5K_INT_GPIO = 0x01000000,
00863 AR5K_INT_BCN_TIMEOUT = 0x02000000,
00864 AR5K_INT_CAB_TIMEOUT = 0x04000000,
00865 AR5K_INT_RX_DOPPLER = 0x08000000,
00866 AR5K_INT_QCBRORN = 0x10000000,
00867 AR5K_INT_QCBRURN = 0x20000000,
00868 AR5K_INT_QTRIG = 0x40000000,
00869 AR5K_INT_GLOBAL = 0x80000000,
00870
00871 AR5K_INT_COMMON = AR5K_INT_RXOK
00872 | AR5K_INT_RXDESC
00873 | AR5K_INT_RXERR
00874 | AR5K_INT_RXNOFRM
00875 | AR5K_INT_RXEOL
00876 | AR5K_INT_RXORN
00877 | AR5K_INT_TXOK
00878 | AR5K_INT_TXDESC
00879 | AR5K_INT_TXERR
00880 | AR5K_INT_TXNOFRM
00881 | AR5K_INT_TXEOL
00882 | AR5K_INT_TXURN
00883 | AR5K_INT_MIB
00884 | AR5K_INT_SWI
00885 | AR5K_INT_RXPHY
00886 | AR5K_INT_RXKCM
00887 | AR5K_INT_SWBA
00888 | AR5K_INT_BRSSI
00889 | AR5K_INT_BMISS
00890 | AR5K_INT_GPIO
00891 | AR5K_INT_GLOBAL,
00892
00893 AR5K_INT_NOCARD = 0xffffffff
00894 };
00895
00896
00897 enum ath5k_software_interrupt {
00898 AR5K_SWI_FULL_CALIBRATION = 0x01,
00899 AR5K_SWI_SHORT_CALIBRATION = 0x02,
00900 };
00901
00902
00903
00904
00905 enum ath5k_power_mode {
00906 AR5K_PM_UNDEFINED = 0,
00907 AR5K_PM_AUTO,
00908 AR5K_PM_AWAKE,
00909 AR5K_PM_FULL_SLEEP,
00910 AR5K_PM_NETWORK_SLEEP,
00911 };
00912
00913
00914
00915
00916
00917
00918 #define AR5K_LED_INIT 0
00919 #define AR5K_LED_SCAN 1
00920 #define AR5K_LED_AUTH 2
00921 #define AR5K_LED_ASSOC 3
00922 #define AR5K_LED_RUN 4
00923
00924
00925 #define AR5K_SOFTLED_PIN 0
00926 #define AR5K_SOFTLED_ON 0
00927 #define AR5K_SOFTLED_OFF 1
00928
00929
00930
00931
00932
00933
00934
00935 enum ath5k_capability_type {
00936 AR5K_CAP_REG_DMN = 0,
00937 AR5K_CAP_TKIP_MIC = 2,
00938 AR5K_CAP_TKIP_SPLIT = 3,
00939 AR5K_CAP_PHYCOUNTERS = 4,
00940 AR5K_CAP_DIVERSITY = 5,
00941 AR5K_CAP_NUM_TXQUEUES = 6,
00942 AR5K_CAP_VEOL = 7,
00943 AR5K_CAP_COMPRESSION = 8,
00944 AR5K_CAP_BURST = 9,
00945 AR5K_CAP_FASTFRAME = 10,
00946 AR5K_CAP_TXPOW = 11,
00947 AR5K_CAP_TPC = 12,
00948 AR5K_CAP_BSSIDMASK = 13,
00949 AR5K_CAP_MCAST_KEYSRCH = 14,
00950 AR5K_CAP_TSF_ADJUST = 15,
00951 AR5K_CAP_XR = 16,
00952 AR5K_CAP_WME_TKIPMIC = 17,
00953 AR5K_CAP_CHAN_HALFRATE = 18,
00954 AR5K_CAP_CHAN_QUARTERRATE = 19,
00955 AR5K_CAP_RFSILENT = 20,
00956 };
00957
00958
00959
00960 struct ath5k_capabilities {
00961
00962
00963
00964
00965 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
00966
00967
00968
00969
00970 struct {
00971 u16 range_2ghz_min;
00972 u16 range_2ghz_max;
00973 u16 range_5ghz_min;
00974 u16 range_5ghz_max;
00975 } cap_range;
00976
00977
00978
00979
00980 struct ath5k_eeprom_info cap_eeprom;
00981
00982
00983
00984
00985 struct {
00986 u8 q_tx_num;
00987 } cap_queues;
00988 };
00989
00990
00991
00992
00993
00994
00995
00996
00997
00998
00999 #define AR5K_MAX_GPIO 10
01000 #define AR5K_MAX_RF_BANKS 8
01001
01002
01003 struct ath5k_hw {
01004 u32 ah_magic;
01005
01006 struct ath5k_softc *ah_sc;
01007 void __iomem *ah_iobase;
01008
01009 enum ath5k_int ah_imr;
01010
01011 struct ieee80211_channel *ah_current_channel;
01012 bool ah_turbo;
01013 bool ah_calibration;
01014 bool ah_single_chip;
01015 bool ah_combined_mic;
01016
01017 enum ath5k_version ah_version;
01018 enum ath5k_radio ah_radio;
01019 u32 ah_phy;
01020 u32 ah_mac_srev;
01021 u16 ah_mac_version;
01022 u16 ah_mac_revision;
01023 u16 ah_phy_revision;
01024 u16 ah_radio_5ghz_revision;
01025 u16 ah_radio_2ghz_revision;
01026
01027 #define ah_modes ah_capabilities.cap_mode
01028 #define ah_ee_version ah_capabilities.cap_eeprom.ee_version
01029
01030 u32 ah_atim_window;
01031 u32 ah_aifs;
01032 u32 ah_cw_min;
01033 u32 ah_cw_max;
01034 u32 ah_limit_tx_retries;
01035
01036
01037 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
01038 u8 ah_ant_mode;
01039 u8 ah_tx_ant;
01040 u8 ah_def_ant;
01041 bool ah_software_retry;
01042
01043 u8 ah_sta_id[ETH_ALEN];
01044
01045
01046
01047
01048 u8 ah_bssid[ETH_ALEN];
01049 u8 ah_bssid_mask[ETH_ALEN];
01050
01051
01052 struct ath5k_capabilities ah_capabilities;
01053
01054 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];
01055 u32 ah_txq_status;
01056 u32 ah_txq_imr_txok;
01057 u32 ah_txq_imr_txerr;
01058 u32 ah_txq_imr_txurn;
01059 u32 ah_txq_imr_txdesc;
01060 u32 ah_txq_imr_txeol;
01061 u32 ah_txq_imr_cbrorn;
01062 u32 ah_txq_imr_cbrurn;
01063 u32 ah_txq_imr_qtrig;
01064 u32 ah_txq_imr_nofrm;
01065 u32 ah_txq_isr;
01066 u32 *ah_rf_banks;
01067 size_t ah_rf_banks_size;
01068 size_t ah_rf_regs_count;
01069 struct ath5k_gain ah_gain;
01070 u8 ah_offset[AR5K_MAX_RF_BANKS];
01071
01072
01073 struct {
01074
01075 u8 tmpL[AR5K_EEPROM_N_PD_GAINS]
01076 [AR5K_EEPROM_POWER_TABLE_SIZE];
01077 u8 tmpR[AR5K_EEPROM_N_PD_GAINS]
01078 [AR5K_EEPROM_POWER_TABLE_SIZE];
01079 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2];
01080 u16 txp_rates_power_table[AR5K_MAX_RATES];
01081 u8 txp_min_idx;
01082 bool txp_tpc;
01083
01084 s16 txp_min_pwr;
01085 s16 txp_max_pwr;
01086
01087 s16 txp_offset;
01088 s16 txp_ofdm;
01089 s16 txp_cck_ofdm_gainf_delta;
01090
01091 s16 txp_cck_ofdm_pwr_delta;
01092 } ah_txpower;
01093
01094 struct {
01095 bool r_enabled;
01096 int r_last_alert;
01097 struct ieee80211_channel r_last_channel;
01098 } ah_radar;
01099
01100
01101 s32 ah_noise_floor;
01102
01103
01104 unsigned long ah_cal_tstamp;
01105
01106
01107 u8 ah_cal_intval;
01108
01109
01110 u8 ah_swi_mask;
01111
01112
01113
01114
01115 int (*ah_setup_rx_desc)(struct ath5k_hw *ah, struct ath5k_desc *desc,
01116 u32 size, unsigned int flags);
01117 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
01118 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
01119 unsigned int, unsigned int, unsigned int, unsigned int,
01120 unsigned int, unsigned int, unsigned int);
01121 int (*ah_setup_mrr_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
01122 unsigned int, unsigned int, unsigned int, unsigned int,
01123 unsigned int, unsigned int);
01124 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
01125 struct ath5k_tx_status *);
01126 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
01127 struct ath5k_rx_status *);
01128 };
01129
01130
01131
01132
01133
01134
01135 extern int ath5k_hw_attach(struct ath5k_softc *sc);
01136 extern void ath5k_hw_detach(struct ath5k_hw *ah);
01137
01138
01139 extern int ath5k_init_leds(struct ath5k_softc *sc);
01140 extern void ath5k_led_enable(struct ath5k_softc *sc);
01141 extern void ath5k_led_off(struct ath5k_softc *sc);
01142 extern void ath5k_unregister_leds(struct ath5k_softc *sc);
01143
01144
01145 extern int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial);
01146 extern int ath5k_hw_on_hold(struct ath5k_hw *ah);
01147 extern int ath5k_hw_reset(struct ath5k_hw *ah, struct ieee80211_channel *channel, bool change_channel);
01148
01149 extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration);
01150
01151
01152 extern void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
01153 extern int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
01154 extern u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
01155 extern void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
01156 extern int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
01157 extern int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
01158 extern u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
01159 extern int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
01160 u32 phys_addr);
01161 extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
01162
01163 extern bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
01164 extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
01165 extern enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum
01166 ath5k_int new_mask);
01167 extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ieee80211_low_level_stats *stats);
01168
01169
01170 extern int ath5k_eeprom_init(struct ath5k_hw *ah);
01171 extern void ath5k_eeprom_detach(struct ath5k_hw *ah);
01172 extern int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
01173 extern bool ath5k_eeprom_is_hb63(struct ath5k_hw *ah);
01174
01175
01176 extern int ath5k_hw_set_opmode(struct ath5k_hw *ah);
01177
01178 extern void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac);
01179 extern int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
01180 extern void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id);
01181 extern int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
01182
01183 extern void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
01184 extern void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
01185
01186 extern void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
01187 extern int ath5k_hw_set_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
01188 extern int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
01189 extern u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
01190 extern void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
01191
01192 extern u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah);
01193 extern u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
01194 extern void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
01195 extern void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
01196 extern void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
01197
01198 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
01199
01200 extern int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout);
01201 extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah);
01202 extern int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout);
01203 extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah);
01204
01205
01206 extern int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, struct ath5k_txq_info *queue_info);
01207 extern int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
01208 const struct ath5k_txq_info *queue_info);
01209 extern int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
01210 enum ath5k_tx_queue queue_type,
01211 struct ath5k_txq_info *queue_info);
01212 extern u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
01213 extern void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
01214 extern int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
01215 extern unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah);
01216 extern int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
01217
01218
01219 extern int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
01220
01221
01222 extern void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
01223 extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
01224 extern int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
01225 extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
01226 extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
01227 extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level);
01228
01229
01230 extern void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
01231 extern void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
01232
01233
01234 int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
01235 extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result);
01236 extern int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
01237 extern int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
01238
01239
01240 extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
01241
01242
01243 extern int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
01244 struct ieee80211_channel *channel,
01245 unsigned int mode);
01246 extern int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq);
01247 extern enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
01248 extern int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
01249
01250 extern bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
01251 extern int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel);
01252
01253 extern int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct ieee80211_channel *channel);
01254 extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq);
01255 extern void ath5k_hw_calibration_poll(struct ath5k_hw *ah);
01256
01257 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
01258 struct ieee80211_channel *channel);
01259 void ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
01260 struct ieee80211_channel *channel);
01261
01262 extern u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
01263 extern int ath5k_hw_phy_disable(struct ath5k_hw *ah);
01264
01265 extern void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode);
01266 extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant);
01267 extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah);
01268
01269 extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, u8 ee_mode, u8 txpower);
01270 extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower);
01271
01272
01273
01274
01275
01276
01277
01278
01279
01280 static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
01281 {
01282 return turbo ? (usec * 80) : (usec * 40);
01283 }
01284
01285
01286
01287
01288
01289 static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
01290 {
01291 return turbo ? (clock / 80) : (clock / 40);
01292 }
01293
01294 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
01295 {
01296 return ioread32(ah->ah_iobase + reg);
01297 }
01298
01299 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
01300 {
01301 iowrite32(val, ah->ah_iobase + reg);
01302 }
01303
01304 #if defined(_ATH5K_RESET) || defined(_ATH5K_PHY)
01305
01306
01307
01308 static int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag,
01309 u32 val, bool is_set)
01310 {
01311 int i;
01312 u32 data;
01313
01314 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
01315 data = ath5k_hw_reg_read(ah, reg);
01316 if (is_set && (data & flag))
01317 break;
01318 else if ((data & flag) == val)
01319 break;
01320 udelay(15);
01321 }
01322
01323 return (i <= 0) ? -EAGAIN : 0;
01324 }
01325 #endif
01326
01327 static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
01328 {
01329 u32 retval = 0, bit, i;
01330
01331 for (i = 0; i < bits; i++) {
01332 bit = (val >> i) & 1;
01333 retval = (retval << 1) | bit;
01334 }
01335
01336 return retval;
01337 }
01338
01339 static inline int ath5k_pad_size(int hdrlen)
01340 {
01341 return (hdrlen < 24) ? 0 : hdrlen & 3;
01342 }
01343
01344 #endif