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00078 #define AR5K_NOQCU_TXDP0 0x0000
00079 #define AR5K_NOQCU_TXDP1 0x0004
00080
00081
00082
00083
00084 #define AR5K_CR 0x0008
00085 #define AR5K_CR_TXE0 0x00000001
00086 #define AR5K_CR_TXE1 0x00000002
00087 #define AR5K_CR_RXE 0x00000004
00088 #define AR5K_CR_TXD0 0x00000008
00089 #define AR5K_CR_TXD1 0x00000010
00090 #define AR5K_CR_RXD 0x00000020
00091 #define AR5K_CR_SWI 0x00000040
00092
00093
00094
00095
00096 #define AR5K_RXDP 0x000c
00097
00098
00099
00100
00101 #define AR5K_CFG 0x0014
00102 #define AR5K_CFG_SWTD 0x00000001
00103 #define AR5K_CFG_SWTB 0x00000002
00104 #define AR5K_CFG_SWRD 0x00000004
00105 #define AR5K_CFG_SWRB 0x00000008
00106 #define AR5K_CFG_SWRG 0x00000010
00107 #define AR5K_CFG_IBSS 0x00000020
00108 #define AR5K_CFG_PHY_OK 0x00000100
00109 #define AR5K_CFG_EEBS 0x00000200
00110 #define AR5K_CFG_CLKGD 0x00000400
00111 #define AR5K_CFG_TXCNT 0x00007800
00112 #define AR5K_CFG_TXCNT_S 11
00113 #define AR5K_CFG_TXFSTAT 0x00008000
00114 #define AR5K_CFG_TXFSTRT 0x00010000
00115 #define AR5K_CFG_PCI_THRES 0x00060000
00116 #define AR5K_CFG_PCI_THRES_S 17
00117
00118
00119
00120
00121 #define AR5K_IER 0x0024
00122 #define AR5K_IER_DISABLE 0x00000000
00123 #define AR5K_IER_ENABLE 0x00000001
00124
00125
00126
00127
00128
00129
00130
00131
00132
00133
00134 #define AR5K_BCR 0x0028
00135 #define AR5K_BCR_AP 0x00000000
00136 #define AR5K_BCR_ADHOC 0x00000001
00137 #define AR5K_BCR_BDMAE 0x00000002
00138 #define AR5K_BCR_TQ1FV 0x00000004
00139 #define AR5K_BCR_TQ1V 0x00000008
00140 #define AR5K_BCR_BCGET 0x00000010
00141
00142
00143
00144
00145 #define AR5K_RTSD0 0x0028
00146 #define AR5K_RTSD0_6 0x000000ff
00147 #define AR5K_RTSD0_6_S 0
00148 #define AR5K_RTSD0_9 0x0000ff00
00149 #define AR5K_RTSD0_9_S 8
00150 #define AR5K_RTSD0_12 0x00ff0000
00151 #define AR5K_RTSD0_12_S 16
00152 #define AR5K_RTSD0_18 0xff000000
00153 #define AR5K_RTSD0_18_S 24
00154
00155
00156
00157
00158
00159
00160
00161
00162
00163
00164
00165
00166
00167
00168
00169
00170
00171 #define AR5K_BSR 0x002c
00172 #define AR5K_BSR_BDLYSW 0x00000001
00173 #define AR5K_BSR_BDLYDMA 0x00000002
00174 #define AR5K_BSR_TXQ1F 0x00000004
00175 #define AR5K_BSR_ATIMDLY 0x00000008
00176 #define AR5K_BSR_SNPADHOC 0x00000100
00177 #define AR5K_BSR_SNPBDMAE 0x00000200
00178 #define AR5K_BSR_SNPTQ1FV 0x00000400
00179 #define AR5K_BSR_SNPTQ1V 0x00000800
00180 #define AR5K_BSR_SNAPSHOTSVALID 0x00001000
00181 #define AR5K_BSR_SWBA_CNT 0x00ff0000
00182
00183
00184
00185
00186 #define AR5K_RTSD1 0x002c
00187 #define AR5K_RTSD1_24 0x000000ff
00188 #define AR5K_RTSD1_24_S 0
00189 #define AR5K_RTSD1_36 0x0000ff00
00190 #define AR5K_RTSD1_36_S 8
00191 #define AR5K_RTSD1_48 0x00ff0000
00192 #define AR5K_RTSD1_48_S 16
00193 #define AR5K_RTSD1_54 0xff000000
00194 #define AR5K_RTSD1_54_S 24
00195
00196
00197
00198
00199
00200 #define AR5K_TXCFG 0x0030
00201 #define AR5K_TXCFG_SDMAMR 0x00000007
00202 #define AR5K_TXCFG_SDMAMR_S 0
00203 #define AR5K_TXCFG_B_MODE 0x00000008
00204 #define AR5K_TXCFG_TXFSTP 0x00000008
00205 #define AR5K_TXCFG_TXFULL 0x000003f0
00206 #define AR5K_TXCFG_TXFULL_S 4
00207 #define AR5K_TXCFG_TXFULL_0B 0x00000000
00208 #define AR5K_TXCFG_TXFULL_64B 0x00000010
00209 #define AR5K_TXCFG_TXFULL_128B 0x00000020
00210 #define AR5K_TXCFG_TXFULL_192B 0x00000030
00211 #define AR5K_TXCFG_TXFULL_256B 0x00000040
00212 #define AR5K_TXCFG_TXCONT_EN 0x00000080
00213 #define AR5K_TXCFG_DMASIZE 0x00000100
00214 #define AR5K_TXCFG_JUMBO_DESC_EN 0x00000400
00215 #define AR5K_TXCFG_ADHOC_BCN_ATIM 0x00000800
00216 #define AR5K_TXCFG_ATIM_WINDOW_DEF_DIS 0x00001000
00217 #define AR5K_TXCFG_RTSRND 0x00001000
00218 #define AR5K_TXCFG_FRMPAD_DIS 0x00002000
00219 #define AR5K_TXCFG_RDY_CBR_DIS 0x00004000
00220 #define AR5K_TXCFG_JUMBO_FRM_MODE 0x00008000
00221 #define AR5K_TXCFG_DCU_DBL_BUF_DIS 0x00008000
00222 #define AR5K_TXCFG_DCU_CACHING_DIS 0x00010000
00223
00224
00225
00226
00227 #define AR5K_RXCFG 0x0034
00228 #define AR5K_RXCFG_SDMAMW 0x00000007
00229 #define AR5K_RXCFG_SDMAMW_S 0
00230 #define AR5K_RXCFG_ZLFDMA 0x00000008
00231 #define AR5K_RXCFG_DEF_ANTENNA 0x00000010
00232 #define AR5K_RXCFG_JUMBO_RXE 0x00000020
00233 #define AR5K_RXCFG_JUMBO_WRAP 0x00000040
00234 #define AR5K_RXCFG_SLE_ENTRY 0x00000080
00235
00236
00237
00238
00239
00240 #define AR5K_RXJLA 0x0038
00241
00242
00243
00244
00245 #define AR5K_MIBC 0x0040
00246 #define AR5K_MIBC_COW 0x00000001
00247 #define AR5K_MIBC_FMC 0x00000002
00248 #define AR5K_MIBC_CMC 0x00000004
00249 #define AR5K_MIBC_MCS 0x00000008
00250
00251
00252
00253
00254 #define AR5K_TOPS 0x0044
00255 #define AR5K_TOPS_M 0x0000ffff
00256
00257
00258
00259
00260 #define AR5K_RXNOFRM 0x0048
00261 #define AR5K_RXNOFRM_M 0x000003ff
00262
00263
00264
00265
00266 #define AR5K_TXNOFRM 0x004c
00267 #define AR5K_TXNOFRM_M 0x000003ff
00268 #define AR5K_TXNOFRM_QCU 0x000ffc00
00269 #define AR5K_TXNOFRM_QCU_S 10
00270
00271
00272
00273
00274 #define AR5K_RPGTO 0x0050
00275 #define AR5K_RPGTO_M 0x000003ff
00276
00277
00278
00279
00280 #define AR5K_RFCNT 0x0054
00281 #define AR5K_RFCNT_M 0x0000001f
00282 #define AR5K_RFCNT_RFCL 0x0000000f
00283
00284
00285
00286
00287
00288 #define AR5K_MISC 0x0058
00289 #define AR5K_MISC_DMA_OBS_M 0x000001e0
00290 #define AR5K_MISC_DMA_OBS_S 5
00291 #define AR5K_MISC_MISC_OBS_M 0x00000e00
00292 #define AR5K_MISC_MISC_OBS_S 9
00293 #define AR5K_MISC_MAC_OBS_LSB_M 0x00007000
00294 #define AR5K_MISC_MAC_OBS_LSB_S 12
00295 #define AR5K_MISC_MAC_OBS_MSB_M 0x00038000
00296 #define AR5K_MISC_MAC_OBS_MSB_S 15
00297 #define AR5K_MISC_LED_DECAY 0x001c0000
00298 #define AR5K_MISC_LED_BLINK 0x00e00000
00299
00300
00301
00302
00303
00304 #define AR5K_QCUDCU_CLKGT 0x005c
00305 #define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff
00306 #define AR5K_QCUDCU_CLKGT_DCU 0x07ff0000
00307
00308
00309
00310
00311
00312
00313
00314
00315
00316 #define AR5K_ISR 0x001c
00317 #define AR5K_PISR 0x0080
00318 #define AR5K_ISR_RXOK 0x00000001
00319 #define AR5K_ISR_RXDESC 0x00000002
00320 #define AR5K_ISR_RXERR 0x00000004
00321 #define AR5K_ISR_RXNOFRM 0x00000008
00322 #define AR5K_ISR_RXEOL 0x00000010
00323 #define AR5K_ISR_RXORN 0x00000020
00324 #define AR5K_ISR_TXOK 0x00000040
00325 #define AR5K_ISR_TXDESC 0x00000080
00326 #define AR5K_ISR_TXERR 0x00000100
00327 #define AR5K_ISR_TXNOFRM 0x00000200
00328 #define AR5K_ISR_TXEOL 0x00000400
00329 #define AR5K_ISR_TXURN 0x00000800
00330 #define AR5K_ISR_MIB 0x00001000
00331 #define AR5K_ISR_SWI 0x00002000
00332 #define AR5K_ISR_RXPHY 0x00004000
00333 #define AR5K_ISR_RXKCM 0x00008000
00334 #define AR5K_ISR_SWBA 0x00010000
00335 #define AR5K_ISR_BRSSI 0x00020000
00336 #define AR5K_ISR_BMISS 0x00040000
00337 #define AR5K_ISR_HIUERR 0x00080000
00338 #define AR5K_ISR_BNR 0x00100000
00339 #define AR5K_ISR_MCABT 0x00100000
00340 #define AR5K_ISR_RXCHIRP 0x00200000
00341 #define AR5K_ISR_SSERR 0x00200000
00342 #define AR5K_ISR_DPERR 0x00400000
00343 #define AR5K_ISR_RXDOPPLER 0x00400000
00344 #define AR5K_ISR_TIM 0x00800000
00345 #define AR5K_ISR_BCNMISC 0x00800000
00346
00347 #define AR5K_ISR_GPIO 0x01000000
00348 #define AR5K_ISR_QCBRORN 0x02000000
00349 #define AR5K_ISR_QCBRURN 0x04000000
00350 #define AR5K_ISR_QTRIG 0x08000000
00351
00352
00353
00354
00355
00356
00357
00358 #define AR5K_SISR0 0x0084
00359 #define AR5K_SISR0_QCU_TXOK 0x000003ff
00360 #define AR5K_SISR0_QCU_TXOK_S 0
00361 #define AR5K_SISR0_QCU_TXDESC 0x03ff0000
00362 #define AR5K_SISR0_QCU_TXDESC_S 16
00363
00364 #define AR5K_SISR1 0x0088
00365 #define AR5K_SISR1_QCU_TXERR 0x000003ff
00366 #define AR5K_SISR1_QCU_TXERR_S 0
00367 #define AR5K_SISR1_QCU_TXEOL 0x03ff0000
00368 #define AR5K_SISR1_QCU_TXEOL_S 16
00369
00370 #define AR5K_SISR2 0x008c
00371 #define AR5K_SISR2_QCU_TXURN 0x000003ff
00372 #define AR5K_SISR2_QCU_TXURN_S 0
00373 #define AR5K_SISR2_MCABT 0x00010000
00374 #define AR5K_SISR2_SSERR 0x00020000
00375 #define AR5K_SISR2_DPERR 0x00040000
00376 #define AR5K_SISR2_TIM 0x01000000
00377 #define AR5K_SISR2_CAB_END 0x02000000
00378 #define AR5K_SISR2_DTIM_SYNC 0x04000000
00379 #define AR5K_SISR2_BCN_TIMEOUT 0x08000000
00380 #define AR5K_SISR2_CAB_TIMEOUT 0x10000000
00381 #define AR5K_SISR2_DTIM 0x20000000
00382 #define AR5K_SISR2_TSFOOR 0x80000000
00383
00384 #define AR5K_SISR3 0x0090
00385 #define AR5K_SISR3_QCBRORN 0x000003ff
00386 #define AR5K_SISR3_QCBRORN_S 0
00387 #define AR5K_SISR3_QCBRURN 0x03ff0000
00388 #define AR5K_SISR3_QCBRURN_S 16
00389
00390 #define AR5K_SISR4 0x0094
00391 #define AR5K_SISR4_QTRIG 0x000003ff
00392 #define AR5K_SISR4_QTRIG_S 0
00393
00394
00395
00396
00397 #define AR5K_RAC_PISR 0x00c0
00398 #define AR5K_RAC_SISR0 0x00c4
00399 #define AR5K_RAC_SISR1 0x00c8
00400 #define AR5K_RAC_SISR2 0x00cc
00401 #define AR5K_RAC_SISR3 0x00d0
00402 #define AR5K_RAC_SISR4 0x00d4
00403
00404
00405
00406
00407
00408
00409
00410 #define AR5K_IMR 0x0020
00411 #define AR5K_PIMR 0x00a0
00412 #define AR5K_IMR_RXOK 0x00000001
00413 #define AR5K_IMR_RXDESC 0x00000002
00414 #define AR5K_IMR_RXERR 0x00000004
00415 #define AR5K_IMR_RXNOFRM 0x00000008
00416 #define AR5K_IMR_RXEOL 0x00000010
00417 #define AR5K_IMR_RXORN 0x00000020
00418 #define AR5K_IMR_TXOK 0x00000040
00419 #define AR5K_IMR_TXDESC 0x00000080
00420 #define AR5K_IMR_TXERR 0x00000100
00421 #define AR5K_IMR_TXNOFRM 0x00000200
00422 #define AR5K_IMR_TXEOL 0x00000400
00423 #define AR5K_IMR_TXURN 0x00000800
00424 #define AR5K_IMR_MIB 0x00001000
00425 #define AR5K_IMR_SWI 0x00002000
00426 #define AR5K_IMR_RXPHY 0x00004000
00427 #define AR5K_IMR_RXKCM 0x00008000
00428 #define AR5K_IMR_SWBA 0x00010000
00429 #define AR5K_IMR_BRSSI 0x00020000
00430 #define AR5K_IMR_BMISS 0x00040000
00431 #define AR5K_IMR_HIUERR 0x00080000
00432 #define AR5K_IMR_BNR 0x00100000
00433 #define AR5K_IMR_MCABT 0x00100000
00434 #define AR5K_IMR_RXCHIRP 0x00200000
00435 #define AR5K_IMR_SSERR 0x00200000
00436 #define AR5K_IMR_DPERR 0x00400000
00437 #define AR5K_IMR_RXDOPPLER 0x00400000
00438 #define AR5K_IMR_TIM 0x00800000
00439 #define AR5K_IMR_BCNMISC 0x00800000
00440
00441 #define AR5K_IMR_GPIO 0x01000000
00442 #define AR5K_IMR_QCBRORN 0x02000000
00443 #define AR5K_IMR_QCBRURN 0x04000000
00444 #define AR5K_IMR_QTRIG 0x08000000
00445
00446
00447
00448
00449 #define AR5K_SIMR0 0x00a4
00450 #define AR5K_SIMR0_QCU_TXOK 0x000003ff
00451 #define AR5K_SIMR0_QCU_TXOK_S 0
00452 #define AR5K_SIMR0_QCU_TXDESC 0x03ff0000
00453 #define AR5K_SIMR0_QCU_TXDESC_S 16
00454
00455 #define AR5K_SIMR1 0x00a8
00456 #define AR5K_SIMR1_QCU_TXERR 0x000003ff
00457 #define AR5K_SIMR1_QCU_TXERR_S 0
00458 #define AR5K_SIMR1_QCU_TXEOL 0x03ff0000
00459 #define AR5K_SIMR1_QCU_TXEOL_S 16
00460
00461 #define AR5K_SIMR2 0x00ac
00462 #define AR5K_SIMR2_QCU_TXURN 0x000003ff
00463 #define AR5K_SIMR2_QCU_TXURN_S 0
00464 #define AR5K_SIMR2_MCABT 0x00010000
00465 #define AR5K_SIMR2_SSERR 0x00020000
00466 #define AR5K_SIMR2_DPERR 0x00040000
00467 #define AR5K_SIMR2_TIM 0x01000000
00468 #define AR5K_SIMR2_CAB_END 0x02000000
00469 #define AR5K_SIMR2_DTIM_SYNC 0x04000000
00470 #define AR5K_SIMR2_BCN_TIMEOUT 0x08000000
00471 #define AR5K_SIMR2_CAB_TIMEOUT 0x10000000
00472 #define AR5K_SIMR2_DTIM 0x20000000
00473 #define AR5K_SIMR2_TSFOOR 0x80000000
00474
00475 #define AR5K_SIMR3 0x00b0
00476 #define AR5K_SIMR3_QCBRORN 0x000003ff
00477 #define AR5K_SIMR3_QCBRORN_S 0
00478 #define AR5K_SIMR3_QCBRURN 0x03ff0000
00479 #define AR5K_SIMR3_QCBRURN_S 16
00480
00481 #define AR5K_SIMR4 0x00b4
00482 #define AR5K_SIMR4_QTRIG 0x000003ff
00483 #define AR5K_SIMR4_QTRIG_S 0
00484
00485
00486
00487
00488
00489
00490
00491
00492
00493 #define AR5K_DCM_ADDR 0x0400
00494 #define AR5K_DCM_DATA 0x0404
00495
00496
00497
00498
00499 #define AR5K_WOW_PCFG 0x0410
00500 #define AR5K_WOW_PCFG_PAT_MATCH_EN 0x00000001
00501 #define AR5K_WOW_PCFG_LONG_FRAME_POL 0x00000002
00502 #define AR5K_WOW_PCFG_WOBMISS 0x00000004
00503 #define AR5K_WOW_PCFG_PAT_0_EN 0x00000100
00504 #define AR5K_WOW_PCFG_PAT_1_EN 0x00000200
00505 #define AR5K_WOW_PCFG_PAT_2_EN 0x00000400
00506 #define AR5K_WOW_PCFG_PAT_3_EN 0x00000800
00507 #define AR5K_WOW_PCFG_PAT_4_EN 0x00001000
00508 #define AR5K_WOW_PCFG_PAT_5_EN 0x00002000
00509
00510
00511
00512
00513 #define AR5K_WOW_PAT_IDX 0x0414
00514
00515
00516
00517
00518 #define AR5K_WOW_PAT_DATA 0x0418
00519 #define AR5K_WOW_PAT_DATA_0_3_V 0x00000001
00520 #define AR5K_WOW_PAT_DATA_1_4_V 0x00000100
00521 #define AR5K_WOW_PAT_DATA_2_5_V 0x00010000
00522 #define AR5K_WOW_PAT_DATA_0_3_M 0x01000000
00523 #define AR5K_WOW_PAT_DATA_1_4_M 0x04000000
00524 #define AR5K_WOW_PAT_DATA_2_5_M 0x10000000
00525
00526
00527
00528
00529 #define AR5K_DCCFG 0x0420
00530 #define AR5K_DCCFG_GLOBAL_EN 0x00000001
00531 #define AR5K_DCCFG_BYPASS_EN 0x00000002
00532 #define AR5K_DCCFG_BCAST_EN 0x00000004
00533 #define AR5K_DCCFG_MCAST_EN 0x00000008
00534
00535
00536
00537
00538 #define AR5K_CCFG 0x0600
00539 #define AR5K_CCFG_WINDOW_SIZE 0x00000007
00540 #define AR5K_CCFG_CPC_EN 0x00000008
00541
00542 #define AR5K_CCFG_CCU 0x0604
00543 #define AR5K_CCFG_CCU_CUP_EN 0x00000001
00544 #define AR5K_CCFG_CCU_CREDIT 0x00000002
00545 #define AR5K_CCFG_CCU_CD_THRES 0x00000080
00546 #define AR5K_CCFG_CCU_CUP_LCNT 0x00010000
00547 #define AR5K_CCFG_CCU_INIT 0x00100200
00548
00549
00550
00551
00552 #define AR5K_CPC0 0x0610
00553 #define AR5K_CPC1 0x0614
00554 #define AR5K_CPC2 0x0618
00555 #define AR5K_CPC3 0x061c
00556 #define AR5K_CPCOVF 0x0620
00557
00558
00559
00560
00561
00562
00563
00564
00565
00566
00567
00568
00569
00570
00571
00572
00573
00574
00575
00576
00577 #define AR5K_QUEUE_REG(_r, _q) (((_q) << 2) + _r)
00578 #define AR5K_QCU_GLOBAL_READ(_r, _q) (AR5K_REG_READ(_r) & (1 << _q))
00579 #define AR5K_QCU_GLOBAL_WRITE(_r, _q) AR5K_REG_WRITE(_r, (1 << _q))
00580
00581
00582
00583
00584 #define AR5K_QCU_TXDP_BASE 0x0800
00585 #define AR5K_QUEUE_TXDP(_q) AR5K_QUEUE_REG(AR5K_QCU_TXDP_BASE, _q)
00586
00587
00588
00589
00590 #define AR5K_QCU_TXE 0x0840
00591 #define AR5K_ENABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXE, _q)
00592 #define AR5K_QUEUE_ENABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXE, _q)
00593
00594
00595
00596
00597 #define AR5K_QCU_TXD 0x0880
00598 #define AR5K_DISABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXD, _q)
00599 #define AR5K_QUEUE_DISABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXD, _q)
00600
00601
00602
00603
00604 #define AR5K_QCU_CBRCFG_BASE 0x08c0
00605 #define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff
00606 #define AR5K_QCU_CBRCFG_INTVAL_S 0
00607 #define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000
00608 #define AR5K_QCU_CBRCFG_ORN_THRES_S 24
00609 #define AR5K_QUEUE_CBRCFG(_q) AR5K_QUEUE_REG(AR5K_QCU_CBRCFG_BASE, _q)
00610
00611
00612
00613
00614 #define AR5K_QCU_RDYTIMECFG_BASE 0x0900
00615 #define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff
00616 #define AR5K_QCU_RDYTIMECFG_INTVAL_S 0
00617 #define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000
00618 #define AR5K_QUEUE_RDYTIMECFG(_q) AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q)
00619
00620
00621
00622
00623 #define AR5K_QCU_ONESHOTARM_SET 0x0940
00624 #define AR5K_QCU_ONESHOTARM_SET_M 0x0000ffff
00625
00626
00627
00628
00629 #define AR5K_QCU_ONESHOTARM_CLEAR 0x0980
00630 #define AR5K_QCU_ONESHOTARM_CLEAR_M 0x0000ffff
00631
00632
00633
00634
00635 #define AR5K_QCU_MISC_BASE 0x09c0
00636 #define AR5K_QCU_MISC_FRSHED_M 0x0000000f
00637 #define AR5K_QCU_MISC_FRSHED_ASAP 0
00638 #define AR5K_QCU_MISC_FRSHED_CBR 1
00639 #define AR5K_QCU_MISC_FRSHED_DBA_GT 2
00640 #define AR5K_QCU_MISC_FRSHED_TIM_GT 3
00641 #define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4
00642 #define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010
00643 #define AR5K_QCU_MISC_CBREXP_DIS 0x00000020
00644 #define AR5K_QCU_MISC_CBREXP_BCN_DIS 0x00000040
00645 #define AR5K_QCU_MISC_BCN_ENABLE 0x00000080
00646 #define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100
00647 #define AR5K_QCU_MISC_RDY_VEOL_POLICY 0x00000200
00648 #define AR5K_QCU_MISC_CBR_RESET_CNT 0x00000400
00649 #define AR5K_QCU_MISC_DCU_EARLY 0x00000800
00650 #define AR5K_QCU_MISC_DCU_CMP_EN 0x00001000
00651 #define AR5K_QUEUE_MISC(_q) AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q)
00652
00653
00654
00655
00656
00657 #define AR5K_QCU_STS_BASE 0x0a00
00658 #define AR5K_QCU_STS_FRMPENDCNT 0x00000003
00659 #define AR5K_QCU_STS_CBREXPCNT 0x0000ff00
00660 #define AR5K_QUEUE_STATUS(_q) AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q)
00661
00662
00663
00664
00665 #define AR5K_QCU_RDYTIMESHDN 0x0a40
00666 #define AR5K_QCU_RDYTIMESHDN_M 0x000003ff
00667
00668
00669
00670
00671 #define AR5K_QCU_CBB_SELECT 0x0b00
00672 #define AR5K_QCU_CBB_ADDR 0x0b04
00673 #define AR5K_QCU_CBB_ADDR_S 9
00674
00675
00676
00677
00678
00679 #define AR5K_QCU_CBCFG 0x0b08
00680
00681
00682
00683
00684
00685
00686
00687
00688
00689
00690
00691
00692
00693
00694
00695
00696
00697
00698
00699
00700
00701
00702 #define AR5K_DCU_QCUMASK_BASE 0x1000
00703 #define AR5K_DCU_QCUMASK_M 0x000003ff
00704 #define AR5K_QUEUE_QCUMASK(_q) AR5K_QUEUE_REG(AR5K_DCU_QCUMASK_BASE, _q)
00705
00706
00707
00708
00709 #define AR5K_DCU_LCL_IFS_BASE 0x1040
00710 #define AR5K_DCU_LCL_IFS_CW_MIN 0x000003ff
00711 #define AR5K_DCU_LCL_IFS_CW_MIN_S 0
00712 #define AR5K_DCU_LCL_IFS_CW_MAX 0x000ffc00
00713 #define AR5K_DCU_LCL_IFS_CW_MAX_S 10
00714 #define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000
00715 #define AR5K_DCU_LCL_IFS_AIFS_S 20
00716 #define AR5K_DCU_LCL_IFS_AIFS_MAX 0xfc
00717 #define AR5K_QUEUE_DFS_LOCAL_IFS(_q) AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q)
00718
00719
00720
00721
00722 #define AR5K_DCU_RETRY_LMT_BASE 0x1080
00723 #define AR5K_DCU_RETRY_LMT_SH_RETRY 0x0000000f
00724 #define AR5K_DCU_RETRY_LMT_SH_RETRY_S 0
00725 #define AR5K_DCU_RETRY_LMT_LG_RETRY 0x000000f0
00726 #define AR5K_DCU_RETRY_LMT_LG_RETRY_S 4
00727 #define AR5K_DCU_RETRY_LMT_SSH_RETRY 0x00003f00
00728 #define AR5K_DCU_RETRY_LMT_SSH_RETRY_S 8
00729 #define AR5K_DCU_RETRY_LMT_SLG_RETRY 0x000fc000
00730 #define AR5K_DCU_RETRY_LMT_SLG_RETRY_S 14
00731 #define AR5K_QUEUE_DFS_RETRY_LIMIT(_q) AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q)
00732
00733
00734
00735
00736 #define AR5K_DCU_CHAN_TIME_BASE 0x10c0
00737 #define AR5K_DCU_CHAN_TIME_DUR 0x000fffff
00738 #define AR5K_DCU_CHAN_TIME_DUR_S 0
00739 #define AR5K_DCU_CHAN_TIME_ENABLE 0x00100000
00740 #define AR5K_QUEUE_DFS_CHANNEL_TIME(_q) AR5K_QUEUE_REG(AR5K_DCU_CHAN_TIME_BASE, _q)
00741
00742
00743
00744
00745
00746
00747
00748
00749
00750
00751
00752
00753
00754 #define AR5K_DCU_MISC_BASE 0x1100
00755 #define AR5K_DCU_MISC_BACKOFF 0x0000003f
00756 #define AR5K_DCU_MISC_ETS_RTS_POL 0x00000040
00757
00758
00759 #define AR5K_DCU_MISC_ETS_CW_POL 0x00000080
00760
00761 #define AR5K_DCU_MISC_FRAG_WAIT 0x00000100
00762 #define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200
00763 #define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800
00764 #define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000
00765 #define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000
00766 #define AR5K_DCU_MISC_VIRTCOL 0x0000c000
00767 #define AR5K_DCU_MISC_VIRTCOL_NORMAL 0
00768 #define AR5K_DCU_MISC_VIRTCOL_IGNORE 1
00769 #define AR5K_DCU_MISC_BCN_ENABLE 0x00010000
00770 #define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000
00771 #define AR5K_DCU_MISC_ARBLOCK_CTL_S 17
00772 #define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0
00773 #define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1
00774 #define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2
00775 #define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000
00776 #define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000
00777 #define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000
00778 #define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000
00779 #define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000
00780 #define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000
00781 #define AR5K_QUEUE_DFS_MISC(_q) AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q)
00782
00783
00784
00785
00786 #define AR5K_DCU_SEQNUM_BASE 0x1140
00787 #define AR5K_DCU_SEQNUM_M 0x00000fff
00788 #define AR5K_QUEUE_DCU_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q)
00789
00790
00791
00792
00793 #define AR5K_DCU_GBL_IFS_SIFS 0x1030
00794 #define AR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff
00795
00796
00797
00798
00799 #define AR5K_DCU_GBL_IFS_SLOT 0x1070
00800 #define AR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff
00801
00802
00803
00804
00805 #define AR5K_DCU_GBL_IFS_EIFS 0x10b0
00806 #define AR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff
00807
00808
00809
00810
00811
00812
00813
00814
00815
00816
00817
00818 #define AR5K_DCU_GBL_IFS_MISC 0x10f0
00819 #define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007
00820 #define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008
00821 #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0
00822 #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00
00823 #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR_S 10
00824 #define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000
00825 #define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST 0x00400000
00826 #define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST 0x00800000
00827 #define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS 0x01000000
00828
00829
00830
00831
00832 #define AR5K_DCU_FP 0x1230
00833 #define AR5K_DCU_FP_NOBURST_DCU_EN 0x00000001
00834 #define AR5K_DCU_FP_NOBURST_EN 0x00000010
00835 #define AR5K_DCU_FP_BURST_DCU_EN 0x00000020
00836
00837
00838
00839
00840 #define AR5K_DCU_TXP 0x1270
00841 #define AR5K_DCU_TXP_M 0x000003ff
00842 #define AR5K_DCU_TXP_STATUS 0x00010000
00843
00844
00845
00846
00847
00848
00849 #define AR5K_DCU_TX_FILTER_0_BASE 0x1038
00850 #define AR5K_DCU_TX_FILTER_0(_n) (AR5K_DCU_TX_FILTER_0_BASE + (_n * 64))
00851
00852
00853
00854
00855 #define AR5K_DCU_TX_FILTER_1_BASE 0x103c
00856 #define AR5K_DCU_TX_FILTER_1(_n) (AR5K_DCU_TX_FILTER_1_BASE + (_n * 64))
00857
00858
00859
00860
00861 #define AR5K_DCU_TX_FILTER_CLR 0x143c
00862
00863
00864
00865
00866 #define AR5K_DCU_TX_FILTER_SET 0x147c
00867
00868
00869
00870
00871 #define AR5K_RESET_CTL 0x4000
00872 #define AR5K_RESET_CTL_PCU 0x00000001
00873 #define AR5K_RESET_CTL_DMA 0x00000002
00874 #define AR5K_RESET_CTL_BASEBAND 0x00000002
00875 #define AR5K_RESET_CTL_MAC 0x00000004
00876 #define AR5K_RESET_CTL_PHY 0x00000008
00877 #define AR5K_RESET_CTL_PCI 0x00000010
00878
00879
00880
00881
00882 #define AR5K_SLEEP_CTL 0x4004
00883 #define AR5K_SLEEP_CTL_SLDUR 0x0000ffff
00884 #define AR5K_SLEEP_CTL_SLDUR_S 0
00885 #define AR5K_SLEEP_CTL_SLE 0x00030000
00886 #define AR5K_SLEEP_CTL_SLE_S 16
00887 #define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000
00888 #define AR5K_SLEEP_CTL_SLE_SLP 0x00010000
00889 #define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000
00890 #define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008
00891 #define AR5K_SLEEP_CTL_DUR_TIM_POL 0x00040000
00892 #define AR5K_SLEEP_CTL_DUR_WRITE_POL 0x00080000
00893 #define AR5K_SLEEP_CTL_SLE_POL 0x00100000
00894
00895
00896
00897
00898 #define AR5K_INTPEND 0x4008
00899 #define AR5K_INTPEND_M 0x00000001
00900
00901
00902
00903
00904 #define AR5K_SFR 0x400c
00905 #define AR5K_SFR_EN 0x00000001
00906
00907
00908
00909
00910
00911 #define AR5K_PCICFG 0x4010
00912 #define AR5K_PCICFG_EEAE 0x00000001
00913 #define AR5K_PCICFG_SLEEP_CLOCK_EN 0x00000002
00914 #define AR5K_PCICFG_CLKRUNEN 0x00000004
00915 #define AR5K_PCICFG_EESIZE 0x00000018
00916 #define AR5K_PCICFG_EESIZE_S 3
00917 #define AR5K_PCICFG_EESIZE_4K 0
00918 #define AR5K_PCICFG_EESIZE_8K 1
00919 #define AR5K_PCICFG_EESIZE_16K 2
00920 #define AR5K_PCICFG_EESIZE_FAIL 3
00921 #define AR5K_PCICFG_LED 0x00000060
00922 #define AR5K_PCICFG_LED_NONE 0x00000000
00923 #define AR5K_PCICFG_LED_PEND 0x00000020
00924 #define AR5K_PCICFG_LED_ASSOC 0x00000040
00925 #define AR5K_PCICFG_BUS_SEL 0x00000380
00926 #define AR5K_PCICFG_CBEFIX_DIS 0x00000400
00927 #define AR5K_PCICFG_SL_INTEN 0x00000800
00928 #define AR5K_PCICFG_LED_BCTL 0x00001000
00929 #define AR5K_PCICFG_RETRY_FIX 0x00001000
00930 #define AR5K_PCICFG_SL_INPEN 0x00002000
00931 #define AR5K_PCICFG_SPWR_DN 0x00010000
00932 #define AR5K_PCICFG_LEDMODE 0x000e0000
00933 #define AR5K_PCICFG_LEDMODE_PROP 0x00000000
00934 #define AR5K_PCICFG_LEDMODE_PROM 0x00020000
00935 #define AR5K_PCICFG_LEDMODE_PWR 0x00040000
00936 #define AR5K_PCICFG_LEDMODE_RAND 0x00060000
00937 #define AR5K_PCICFG_LEDBLINK 0x00700000
00938 #define AR5K_PCICFG_LEDBLINK_S 20
00939 #define AR5K_PCICFG_LEDSLOW 0x00800000
00940 #define AR5K_PCICFG_LEDSTATE \
00941 (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \
00942 AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW)
00943 #define AR5K_PCICFG_SLEEP_CLOCK_RATE 0x03000000
00944 #define AR5K_PCICFG_SLEEP_CLOCK_RATE_S 24
00945
00946
00947
00948
00949
00950
00951
00952
00953
00954
00955
00956
00957
00958
00959
00960
00961
00962 #define AR5K_NUM_GPIO 6
00963
00964 #define AR5K_GPIOCR 0x4014
00965 #define AR5K_GPIOCR_INT_ENA 0x00008000
00966 #define AR5K_GPIOCR_INT_SELL 0x00000000
00967 #define AR5K_GPIOCR_INT_SELH 0x00010000
00968 #define AR5K_GPIOCR_IN(n) (0 << ((n) * 2))
00969 #define AR5K_GPIOCR_OUT0(n) (1 << ((n) * 2))
00970 #define AR5K_GPIOCR_OUT1(n) (2 << ((n) * 2))
00971 #define AR5K_GPIOCR_OUT(n) (3 << ((n) * 2))
00972 #define AR5K_GPIOCR_INT_SEL(n) ((n) << 12)
00973
00974
00975
00976
00977 #define AR5K_GPIODO 0x4018
00978
00979
00980
00981
00982 #define AR5K_GPIODI 0x401c
00983 #define AR5K_GPIODI_M 0x0000002f
00984
00985
00986
00987
00988 #define AR5K_SREV 0x4020
00989 #define AR5K_SREV_REV 0x0000000f
00990 #define AR5K_SREV_REV_S 0
00991 #define AR5K_SREV_VER 0x000000ff
00992 #define AR5K_SREV_VER_S 4
00993
00994
00995
00996
00997 #define AR5K_TXEPOST 0x4028
00998
00999
01000
01001
01002 #define AR5K_QCU_SLEEP_MASK 0x402c
01003
01004
01005
01006
01007
01008
01009
01010
01011
01012 #define AR5K_5414_CBCFG 0x4068
01013 #define AR5K_5414_CBCFG_BUF_DIS 0x10
01014
01015
01016
01017
01018
01019 #define AR5K_PCIE_PM_CTL 0x4068
01020
01021 #define AR5K_PCIE_PM_CTL_L1_WHEN_D2 0x00000001
01022
01023 #define AR5K_PCIE_PM_CTL_L0_L0S_CLEAR 0x00000002
01024 #define AR5K_PCIE_PM_CTL_L0_L0S_EN 0x00000004
01025 #define AR5K_PCIE_PM_CTL_LDRESET_EN 0x00000008
01026
01027
01028 #define AR5K_PCIE_PM_CTL_PME_EN 0x00000010
01029 #define AR5K_PCIE_PM_CTL_AUX_PWR_DET 0x00000020
01030 #define AR5K_PCIE_PM_CTL_PME_CLEAR 0x00000040
01031 #define AR5K_PCIE_PM_CTL_PSM_D0 0x00000080
01032 #define AR5K_PCIE_PM_CTL_PSM_D1 0x00000100
01033 #define AR5K_PCIE_PM_CTL_PSM_D2 0x00000200
01034 #define AR5K_PCIE_PM_CTL_PSM_D3 0x00000400
01035
01036
01037
01038
01039 #define AR5K_PCIE_WAEN 0x407c
01040
01041
01042
01043
01044
01045 #define AR5K_PCIE_SERDES 0x4080
01046 #define AR5K_PCIE_SERDES_RESET 0x4084
01047
01048
01049
01050
01051
01052
01053
01054
01055
01056
01057
01058
01059
01060
01061
01062
01063
01064
01065
01066
01067
01068
01069
01070
01071
01072
01073
01074
01075
01076
01077
01078
01079
01080
01081
01082
01083
01084
01085 #define AR5K_EEPROM_BASE 0x6000
01086
01087
01088
01089
01090 #define AR5K_EEPROM_DATA_5211 0x6004
01091 #define AR5K_EEPROM_DATA_5210 0x6800
01092 #define AR5K_EEPROM_DATA (ah->ah_version == AR5K_AR5210 ? \
01093 AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211)
01094
01095
01096
01097
01098 #define AR5K_EEPROM_CMD 0x6008
01099 #define AR5K_EEPROM_CMD_READ 0x00000001
01100 #define AR5K_EEPROM_CMD_WRITE 0x00000002
01101 #define AR5K_EEPROM_CMD_RESET 0x00000004
01102
01103
01104
01105
01106 #define AR5K_EEPROM_STAT_5210 0x6c00
01107 #define AR5K_EEPROM_STAT_5211 0x600c
01108 #define AR5K_EEPROM_STATUS (ah->ah_version == AR5K_AR5210 ? \
01109 AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211)
01110 #define AR5K_EEPROM_STAT_RDERR 0x00000001
01111 #define AR5K_EEPROM_STAT_RDDONE 0x00000002
01112 #define AR5K_EEPROM_STAT_WRERR 0x00000004
01113 #define AR5K_EEPROM_STAT_WRDONE 0x00000008
01114
01115
01116
01117
01118 #define AR5K_EEPROM_CFG 0x6010
01119 #define AR5K_EEPROM_CFG_SIZE 0x00000003
01120 #define AR5K_EEPROM_CFG_SIZE_AUTO 0
01121 #define AR5K_EEPROM_CFG_SIZE_4KBIT 1
01122 #define AR5K_EEPROM_CFG_SIZE_8KBIT 2
01123 #define AR5K_EEPROM_CFG_SIZE_16KBIT 3
01124 #define AR5K_EEPROM_CFG_WR_WAIT_DIS 0x00000004
01125 #define AR5K_EEPROM_CFG_CLK_RATE 0x00000018
01126 #define AR5K_EEPROM_CFG_CLK_RATE_S 3
01127 #define AR5K_EEPROM_CFG_CLK_RATE_156KHZ 0
01128 #define AR5K_EEPROM_CFG_CLK_RATE_312KHZ 1
01129 #define AR5K_EEPROM_CFG_CLK_RATE_625KHZ 2
01130 #define AR5K_EEPROM_CFG_PROT_KEY 0x00ffff00
01131 #define AR5K_EEPROM_CFG_PROT_KEY_S 8
01132 #define AR5K_EEPROM_CFG_LIND_EN 0x01000000
01133
01134
01135
01136
01137
01138
01139
01140
01141
01142
01143
01144
01145
01146
01147 #define AR5K_PCU_MIN 0x8000
01148 #define AR5K_PCU_MAX 0x8fff
01149
01150
01151
01152
01153 #define AR5K_STA_ID0 0x8000
01154 #define AR5K_STA_ID0_ARRD_L32 0xffffffff
01155
01156
01157
01158
01159 #define AR5K_STA_ID1 0x8004
01160 #define AR5K_STA_ID1_ADDR_U16 0x0000ffff
01161 #define AR5K_STA_ID1_AP 0x00010000
01162 #define AR5K_STA_ID1_ADHOC 0x00020000
01163 #define AR5K_STA_ID1_PWR_SV 0x00040000
01164 #define AR5K_STA_ID1_NO_KEYSRCH 0x00080000
01165 #define AR5K_STA_ID1_NO_PSPOLL 0x00100000
01166 #define AR5K_STA_ID1_PCF_5211 0x00100000
01167 #define AR5K_STA_ID1_PCF_5210 0x00200000
01168 #define AR5K_STA_ID1_PCF (ah->ah_version == AR5K_AR5210 ? \
01169 AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211)
01170 #define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000
01171 #define AR5K_STA_ID1_DESC_ANTENNA 0x00400000
01172 #define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000
01173 #define AR5K_STA_ID1_ACKCTS_6MB 0x01000000
01174 #define AR5K_STA_ID1_BASE_RATE_11B 0x02000000
01175 #define AR5K_STA_ID1_SELFGEN_DEF_ANT 0x04000000
01176 #define AR5K_STA_ID1_CRYPT_MIC_EN 0x08000000
01177 #define AR5K_STA_ID1_KEYSRCH_MODE 0x10000000
01178 #define AR5K_STA_ID1_PRESERVE_SEQ_NUM 0x20000000
01179 #define AR5K_STA_ID1_CBCIV_ENDIAN 0x40000000
01180 #define AR5K_STA_ID1_KEYSRCH_MCAST 0x80000000
01181
01182 #define AR5K_STA_ID1_ANTENNA_SETTINGS (AR5K_STA_ID1_DEFAULT_ANTENNA | \
01183 AR5K_STA_ID1_DESC_ANTENNA | \
01184 AR5K_STA_ID1_RTS_DEF_ANTENNA | \
01185 AR5K_STA_ID1_SELFGEN_DEF_ANT)
01186
01187
01188
01189
01190 #define AR5K_BSS_ID0 0x8008
01191
01192
01193
01194
01195
01196
01197 #define AR5K_BSS_ID1 0x800c
01198 #define AR5K_BSS_ID1_AID 0xffff0000
01199 #define AR5K_BSS_ID1_AID_S 16
01200
01201
01202
01203
01204 #define AR5K_SLOT_TIME 0x8010
01205
01206
01207
01208
01209 #define AR5K_TIME_OUT 0x8014
01210 #define AR5K_TIME_OUT_ACK 0x00001fff
01211 #define AR5K_TIME_OUT_ACK_S 0
01212 #define AR5K_TIME_OUT_CTS 0x1fff0000
01213 #define AR5K_TIME_OUT_CTS_S 16
01214
01215
01216
01217
01218 #define AR5K_RSSI_THR 0x8018
01219 #define AR5K_RSSI_THR_M 0x000000ff
01220 #define AR5K_RSSI_THR_BMISS_5210 0x00000700
01221 #define AR5K_RSSI_THR_BMISS_5210_S 8
01222 #define AR5K_RSSI_THR_BMISS_5211 0x0000ff00
01223 #define AR5K_RSSI_THR_BMISS_5211_S 8
01224 #define AR5K_RSSI_THR_BMISS (ah->ah_version == AR5K_AR5210 ? \
01225 AR5K_RSSI_THR_BMISS_5210 : AR5K_RSSI_THR_BMISS_5211)
01226 #define AR5K_RSSI_THR_BMISS_S 8
01227
01228
01229
01230
01231
01232
01233
01234
01235
01236
01237
01238
01239
01240
01241 #define AR5K_NODCU_RETRY_LMT 0x801c
01242 #define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f
01243 #define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 0
01244 #define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0
01245 #define AR5K_NODCU_RETRY_LMT_LG_RETRY_S 4
01246 #define AR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00
01247 #define AR5K_NODCU_RETRY_LMT_SSH_RETRY_S 8
01248 #define AR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000
01249 #define AR5K_NODCU_RETRY_LMT_SLG_RETRY_S 14
01250 #define AR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000
01251 #define AR5K_NODCU_RETRY_LMT_CW_MIN_S 20
01252
01253
01254
01255
01256 #define AR5K_USEC_5210 0x8020
01257 #define AR5K_USEC_5211 0x801c
01258 #define AR5K_USEC (ah->ah_version == AR5K_AR5210 ? \
01259 AR5K_USEC_5210 : AR5K_USEC_5211)
01260 #define AR5K_USEC_1 0x0000007f
01261 #define AR5K_USEC_1_S 0
01262 #define AR5K_USEC_32 0x00003f80
01263 #define AR5K_USEC_32_S 7
01264 #define AR5K_USEC_TX_LATENCY_5211 0x007fc000
01265 #define AR5K_USEC_TX_LATENCY_5211_S 14
01266 #define AR5K_USEC_RX_LATENCY_5211 0x1f800000
01267 #define AR5K_USEC_RX_LATENCY_5211_S 23
01268 #define AR5K_USEC_TX_LATENCY_5210 0x000fc000
01269 #define AR5K_USEC_TX_LATENCY_5210_S 14
01270 #define AR5K_USEC_RX_LATENCY_5210 0x03f00000
01271 #define AR5K_USEC_RX_LATENCY_5210_S 20
01272
01273
01274
01275
01276 #define AR5K_BEACON_5210 0x8024
01277 #define AR5K_BEACON_5211 0x8020
01278 #define AR5K_BEACON (ah->ah_version == AR5K_AR5210 ? \
01279 AR5K_BEACON_5210 : AR5K_BEACON_5211)
01280 #define AR5K_BEACON_PERIOD 0x0000ffff
01281 #define AR5K_BEACON_PERIOD_S 0
01282 #define AR5K_BEACON_TIM 0x007f0000
01283 #define AR5K_BEACON_TIM_S 16
01284 #define AR5K_BEACON_ENABLE 0x00800000
01285 #define AR5K_BEACON_RESET_TSF 0x01000000
01286
01287
01288
01289
01290 #define AR5K_CFP_PERIOD_5210 0x8028
01291 #define AR5K_CFP_PERIOD_5211 0x8024
01292 #define AR5K_CFP_PERIOD (ah->ah_version == AR5K_AR5210 ? \
01293 AR5K_CFP_PERIOD_5210 : AR5K_CFP_PERIOD_5211)
01294
01295
01296
01297
01298 #define AR5K_TIMER0_5210 0x802c
01299 #define AR5K_TIMER0_5211 0x8028
01300 #define AR5K_TIMER0 (ah->ah_version == AR5K_AR5210 ? \
01301 AR5K_TIMER0_5210 : AR5K_TIMER0_5211)
01302
01303
01304
01305
01306 #define AR5K_TIMER1_5210 0x8030
01307 #define AR5K_TIMER1_5211 0x802c
01308 #define AR5K_TIMER1 (ah->ah_version == AR5K_AR5210 ? \
01309 AR5K_TIMER1_5210 : AR5K_TIMER1_5211)
01310
01311
01312
01313
01314 #define AR5K_TIMER2_5210 0x8034
01315 #define AR5K_TIMER2_5211 0x8030
01316 #define AR5K_TIMER2 (ah->ah_version == AR5K_AR5210 ? \
01317 AR5K_TIMER2_5210 : AR5K_TIMER2_5211)
01318
01319
01320
01321
01322 #define AR5K_TIMER3_5210 0x8038
01323 #define AR5K_TIMER3_5211 0x8034
01324 #define AR5K_TIMER3 (ah->ah_version == AR5K_AR5210 ? \
01325 AR5K_TIMER3_5210 : AR5K_TIMER3_5211)
01326
01327
01328
01329
01330
01331 #define AR5K_IFS0 0x8040
01332 #define AR5K_IFS0_SIFS 0x000007ff
01333 #define AR5K_IFS0_SIFS_S 0
01334 #define AR5K_IFS0_DIFS 0x007ff800
01335 #define AR5K_IFS0_DIFS_S 11
01336
01337
01338
01339
01340 #define AR5K_IFS1 0x8044
01341 #define AR5K_IFS1_PIFS 0x00000fff
01342 #define AR5K_IFS1_PIFS_S 0
01343 #define AR5K_IFS1_EIFS 0x03fff000
01344 #define AR5K_IFS1_EIFS_S 12
01345 #define AR5K_IFS1_CS_EN 0x04000000
01346
01347
01348
01349
01350
01351 #define AR5K_CFP_DUR_5210 0x8048
01352 #define AR5K_CFP_DUR_5211 0x8038
01353 #define AR5K_CFP_DUR (ah->ah_version == AR5K_AR5210 ? \
01354 AR5K_CFP_DUR_5210 : AR5K_CFP_DUR_5211)
01355
01356
01357
01358
01359 #define AR5K_RX_FILTER_5210 0x804c
01360 #define AR5K_RX_FILTER_5211 0x803c
01361 #define AR5K_RX_FILTER (ah->ah_version == AR5K_AR5210 ? \
01362 AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211)
01363 #define AR5K_RX_FILTER_UCAST 0x00000001
01364 #define AR5K_RX_FILTER_MCAST 0x00000002
01365 #define AR5K_RX_FILTER_BCAST 0x00000004
01366 #define AR5K_RX_FILTER_CONTROL 0x00000008
01367 #define AR5K_RX_FILTER_BEACON 0x00000010
01368 #define AR5K_RX_FILTER_PROM 0x00000020
01369 #define AR5K_RX_FILTER_XRPOLL 0x00000040
01370 #define AR5K_RX_FILTER_PROBEREQ 0x00000080
01371 #define AR5K_RX_FILTER_PHYERR_5212 0x00000100
01372 #define AR5K_RX_FILTER_RADARERR_5212 0x00000200
01373 #define AR5K_RX_FILTER_PHYERR_5211 0x00000040
01374 #define AR5K_RX_FILTER_RADARERR_5211 0x00000080
01375 #define AR5K_RX_FILTER_PHYERR \
01376 ((ah->ah_version == AR5K_AR5211 ? \
01377 AR5K_RX_FILTER_PHYERR_5211 : AR5K_RX_FILTER_PHYERR_5212))
01378 #define AR5K_RX_FILTER_RADARERR \
01379 ((ah->ah_version == AR5K_AR5211 ? \
01380 AR5K_RX_FILTER_RADARERR_5211 : AR5K_RX_FILTER_RADARERR_5212))
01381
01382
01383
01384
01385 #define AR5K_MCAST_FILTER0_5210 0x8050
01386 #define AR5K_MCAST_FILTER0_5211 0x8040
01387 #define AR5K_MCAST_FILTER0 (ah->ah_version == AR5K_AR5210 ? \
01388 AR5K_MCAST_FILTER0_5210 : AR5K_MCAST_FILTER0_5211)
01389
01390
01391
01392
01393 #define AR5K_MCAST_FILTER1_5210 0x8054
01394 #define AR5K_MCAST_FILTER1_5211 0x8044
01395 #define AR5K_MCAST_FILTER1 (ah->ah_version == AR5K_AR5210 ? \
01396 AR5K_MCAST_FILTER1_5210 : AR5K_MCAST_FILTER1_5211)
01397
01398
01399
01400
01401
01402 #define AR5K_TX_MASK0 0x8058
01403
01404
01405
01406
01407 #define AR5K_TX_MASK1 0x805c
01408
01409
01410
01411
01412 #define AR5K_CLR_TMASK 0x8060
01413
01414
01415
01416
01417 #define AR5K_TRIG_LVL 0x8064
01418
01419
01420
01421
01422
01423
01424
01425
01426 #define AR5K_DIAG_SW_5210 0x8068
01427 #define AR5K_DIAG_SW_5211 0x8048
01428 #define AR5K_DIAG_SW (ah->ah_version == AR5K_AR5210 ? \
01429 AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211)
01430 #define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001
01431 #define AR5K_DIAG_SW_DIS_ACK 0x00000002
01432 #define AR5K_DIAG_SW_DIS_CTS 0x00000004
01433 #define AR5K_DIAG_SW_DIS_ENC 0x00000008
01434 #define AR5K_DIAG_SW_DIS_DEC 0x00000010
01435 #define AR5K_DIAG_SW_DIS_TX 0x00000020
01436 #define AR5K_DIAG_SW_DIS_RX_5210 0x00000040
01437 #define AR5K_DIAG_SW_DIS_RX_5211 0x00000020
01438 #define AR5K_DIAG_SW_DIS_RX (ah->ah_version == AR5K_AR5210 ? \
01439 AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211)
01440 #define AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080
01441 #define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040
01442 #define AR5K_DIAG_SW_LOOP_BACK (ah->ah_version == AR5K_AR5210 ? \
01443 AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211)
01444 #define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100
01445 #define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080
01446 #define AR5K_DIAG_SW_CORR_FCS (ah->ah_version == AR5K_AR5210 ? \
01447 AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211)
01448 #define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200
01449 #define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100
01450 #define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \
01451 AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211)
01452 #define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400
01453 #define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200
01454 #define AR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \
01455 AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211)
01456 #define AR5K_DIAG_SW_ECO_ENABLE 0x00000400
01457 #define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800
01458 #define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00
01459 #define AR5K_DIAG_SW_SCRAM_SEED_S 10
01460 #define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000
01461 #define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000
01462 #define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000
01463 #define AR5K_DIAG_SW_FRAME_NV0 (ah->ah_version == AR5K_AR5210 ? \
01464 AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211)
01465 #define AR5K_DIAG_SW_OBSPT_M 0x000c0000
01466 #define AR5K_DIAG_SW_OBSPT_S 18
01467 #define AR5K_DIAG_SW_RX_CLEAR_HIGH 0x0010000
01468 #define AR5K_DIAG_SW_IGNORE_CARR_SENSE 0x0020000
01469 #define AR5K_DIAG_SW_CHANEL_IDLE_HIGH 0x0040000
01470 #define AR5K_DIAG_SW_PHEAR_ME 0x0080000
01471
01472
01473
01474
01475 #define AR5K_TSF_L32_5210 0x806c
01476 #define AR5K_TSF_L32_5211 0x804c
01477 #define AR5K_TSF_L32 (ah->ah_version == AR5K_AR5210 ? \
01478 AR5K_TSF_L32_5210 : AR5K_TSF_L32_5211)
01479
01480
01481
01482
01483 #define AR5K_TSF_U32_5210 0x8070
01484 #define AR5K_TSF_U32_5211 0x8050
01485 #define AR5K_TSF_U32 (ah->ah_version == AR5K_AR5210 ? \
01486 AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211)
01487
01488
01489
01490
01491 #define AR5K_LAST_TSTP 0x8080
01492
01493
01494
01495
01496 #define AR5K_ADDAC_TEST 0x8054
01497 #define AR5K_ADDAC_TEST_TXCONT 0x00000001
01498 #define AR5K_ADDAC_TEST_TST_MODE 0x00000002
01499 #define AR5K_ADDAC_TEST_LOOP_EN 0x00000004
01500 #define AR5K_ADDAC_TEST_LOOP_LEN 0x00000008
01501 #define AR5K_ADDAC_TEST_USE_U8 0x00004000
01502 #define AR5K_ADDAC_TEST_MSB 0x00008000
01503 #define AR5K_ADDAC_TEST_TRIG_SEL 0x00010000
01504 #define AR5K_ADDAC_TEST_TRIG_PTY 0x00020000
01505 #define AR5K_ADDAC_TEST_RXCONT 0x00040000
01506 #define AR5K_ADDAC_TEST_CAPTURE 0x00080000
01507 #define AR5K_ADDAC_TEST_TST_ARM 0x00100000
01508
01509
01510
01511
01512 #define AR5K_DEFAULT_ANTENNA 0x8058
01513
01514
01515
01516
01517
01518 #define AR5K_FRAME_CTL_QOSM 0x805c
01519
01520
01521
01522
01523 #define AR5K_SEQ_MASK 0x8060
01524
01525
01526
01527
01528 #define AR5K_RETRY_CNT 0x8084
01529 #define AR5K_RETRY_CNT_SSH 0x0000003f
01530 #define AR5K_RETRY_CNT_SLG 0x00000fc0
01531
01532
01533
01534
01535 #define AR5K_BACKOFF 0x8088
01536 #define AR5K_BACKOFF_CW 0x000003ff
01537 #define AR5K_BACKOFF_CNT 0x03ff0000
01538
01539
01540
01541
01542
01543
01544 #define AR5K_NAV_5210 0x808c
01545 #define AR5K_NAV_5211 0x8084
01546 #define AR5K_NAV (ah->ah_version == AR5K_AR5210 ? \
01547 AR5K_NAV_5210 : AR5K_NAV_5211)
01548
01549
01550
01551
01552 #define AR5K_RTS_OK_5210 0x8090
01553 #define AR5K_RTS_OK_5211 0x8088
01554 #define AR5K_RTS_OK (ah->ah_version == AR5K_AR5210 ? \
01555 AR5K_RTS_OK_5210 : AR5K_RTS_OK_5211)
01556
01557
01558
01559
01560 #define AR5K_RTS_FAIL_5210 0x8094
01561 #define AR5K_RTS_FAIL_5211 0x808c
01562 #define AR5K_RTS_FAIL (ah->ah_version == AR5K_AR5210 ? \
01563 AR5K_RTS_FAIL_5210 : AR5K_RTS_FAIL_5211)
01564
01565
01566
01567
01568 #define AR5K_ACK_FAIL_5210 0x8098
01569 #define AR5K_ACK_FAIL_5211 0x8090
01570 #define AR5K_ACK_FAIL (ah->ah_version == AR5K_AR5210 ? \
01571 AR5K_ACK_FAIL_5210 : AR5K_ACK_FAIL_5211)
01572
01573
01574
01575
01576 #define AR5K_FCS_FAIL_5210 0x809c
01577 #define AR5K_FCS_FAIL_5211 0x8094
01578 #define AR5K_FCS_FAIL (ah->ah_version == AR5K_AR5210 ? \
01579 AR5K_FCS_FAIL_5210 : AR5K_FCS_FAIL_5211)
01580
01581
01582
01583
01584 #define AR5K_BEACON_CNT_5210 0x80a0
01585 #define AR5K_BEACON_CNT_5211 0x8098
01586 #define AR5K_BEACON_CNT (ah->ah_version == AR5K_AR5210 ? \
01587 AR5K_BEACON_CNT_5210 : AR5K_BEACON_CNT_5211)
01588
01589
01590
01591
01592
01593
01594
01595 #define AR5K_TPC 0x80e8
01596 #define AR5K_TPC_ACK 0x0000003f
01597 #define AR5K_TPC_ACK_S 0
01598 #define AR5K_TPC_CTS 0x00003f00
01599 #define AR5K_TPC_CTS_S 8
01600 #define AR5K_TPC_CHIRP 0x003f0000
01601 #define AR5K_TPC_CHIRP_S 16
01602 #define AR5K_TPC_DOPPLER 0x0f000000
01603 #define AR5K_TPC_DOPPLER_S 24
01604
01605
01606
01607
01608 #define AR5K_XRMODE 0x80c0
01609 #define AR5K_XRMODE_POLL_TYPE_M 0x0000003f
01610 #define AR5K_XRMODE_POLL_TYPE_S 0
01611 #define AR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c
01612 #define AR5K_XRMODE_POLL_SUBTYPE_S 2
01613 #define AR5K_XRMODE_POLL_WAIT_ALL 0x00000080
01614 #define AR5K_XRMODE_SIFS_DELAY 0x000fff00
01615 #define AR5K_XRMODE_FRAME_HOLD_M 0xfff00000
01616 #define AR5K_XRMODE_FRAME_HOLD_S 20
01617
01618
01619
01620
01621 #define AR5K_XRDELAY 0x80c4
01622 #define AR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff
01623 #define AR5K_XRDELAY_SLOT_DELAY_S 0
01624 #define AR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000
01625 #define AR5K_XRDELAY_CHIRP_DELAY_S 16
01626
01627
01628
01629
01630 #define AR5K_XRTIMEOUT 0x80c8
01631 #define AR5K_XRTIMEOUT_CHIRP_M 0x0000ffff
01632 #define AR5K_XRTIMEOUT_CHIRP_S 0
01633 #define AR5K_XRTIMEOUT_POLL_M 0xffff0000
01634 #define AR5K_XRTIMEOUT_POLL_S 16
01635
01636
01637
01638
01639 #define AR5K_XRCHIRP 0x80cc
01640 #define AR5K_XRCHIRP_SEND 0x00000001
01641 #define AR5K_XRCHIRP_GAP 0xffff0000
01642
01643
01644
01645
01646 #define AR5K_XRSTOMP 0x80d0
01647 #define AR5K_XRSTOMP_TX 0x00000001
01648 #define AR5K_XRSTOMP_RX 0x00000002
01649 #define AR5K_XRSTOMP_TX_RSSI 0x00000004
01650 #define AR5K_XRSTOMP_TX_BSSID 0x00000008
01651 #define AR5K_XRSTOMP_DATA 0x00000010
01652 #define AR5K_XRSTOMP_RSSI_THRES 0x0000ff00
01653
01654
01655
01656
01657 #define AR5K_SLEEP0 0x80d4
01658 #define AR5K_SLEEP0_NEXT_DTIM 0x0007ffff
01659 #define AR5K_SLEEP0_NEXT_DTIM_S 0
01660 #define AR5K_SLEEP0_ASSUME_DTIM 0x00080000
01661 #define AR5K_SLEEP0_ENH_SLEEP_EN 0x00100000
01662 #define AR5K_SLEEP0_CABTO 0xff000000
01663 #define AR5K_SLEEP0_CABTO_S 24
01664
01665
01666
01667
01668 #define AR5K_SLEEP1 0x80d8
01669 #define AR5K_SLEEP1_NEXT_TIM 0x0007ffff
01670 #define AR5K_SLEEP1_NEXT_TIM_S 0
01671 #define AR5K_SLEEP1_BEACON_TO 0xff000000
01672 #define AR5K_SLEEP1_BEACON_TO_S 24
01673
01674
01675
01676
01677 #define AR5K_SLEEP2 0x80dc
01678 #define AR5K_SLEEP2_TIM_PER 0x0000ffff
01679 #define AR5K_SLEEP2_TIM_PER_S 0
01680 #define AR5K_SLEEP2_DTIM_PER 0xffff0000
01681 #define AR5K_SLEEP2_DTIM_PER_S 16
01682
01683
01684
01685
01686 #define AR5K_BSS_IDM0 0x80e0
01687 #define AR5K_BSS_IDM1 0x80e4
01688
01689
01690
01691
01692
01693
01694
01695 #define AR5K_TXPC 0x80e8
01696 #define AR5K_TXPC_ACK_M 0x0000003f
01697 #define AR5K_TXPC_ACK_S 0
01698 #define AR5K_TXPC_CTS_M 0x00003f00
01699 #define AR5K_TXPC_CTS_S 8
01700 #define AR5K_TXPC_CHIRP_M 0x003f0000
01701 #define AR5K_TXPC_CHIRP_S 16
01702 #define AR5K_TXPC_DOPPLER 0x0f000000
01703 #define AR5K_TXPC_DOPPLER_S 24
01704
01705
01706
01707
01708 #define AR5K_PROFCNT_TX 0x80ec
01709 #define AR5K_PROFCNT_RX 0x80f0
01710 #define AR5K_PROFCNT_RXCLR 0x80f4
01711 #define AR5K_PROFCNT_CYCLE 0x80f8
01712
01713
01714
01715
01716 #define AR5K_QUIET_CTL1 0x80fc
01717 #define AR5K_QUIET_CTL1_NEXT_QT_TSF 0x0000ffff
01718 #define AR5K_QUIET_CTL1_NEXT_QT_TSF_S 0
01719 #define AR5K_QUIET_CTL1_QT_EN 0x00010000
01720 #define AR5K_QUIET_CTL1_ACK_CTS_EN 0x00020000
01721
01722 #define AR5K_QUIET_CTL2 0x8100
01723 #define AR5K_QUIET_CTL2_QT_PER 0x0000ffff
01724 #define AR5K_QUIET_CTL2_QT_PER_S 0
01725 #define AR5K_QUIET_CTL2_QT_DUR 0xffff0000
01726 #define AR5K_QUIET_CTL2_QT_DUR_S 16
01727
01728
01729
01730
01731 #define AR5K_TSF_PARM 0x8104
01732 #define AR5K_TSF_PARM_INC 0x000000ff
01733 #define AR5K_TSF_PARM_INC_S 0
01734
01735
01736
01737
01738 #define AR5K_QOS_NOACK 0x8108
01739 #define AR5K_QOS_NOACK_2BIT_VALUES 0x0000000f
01740 #define AR5K_QOS_NOACK_2BIT_VALUES_S 0
01741 #define AR5K_QOS_NOACK_BIT_OFFSET 0x00000070
01742 #define AR5K_QOS_NOACK_BIT_OFFSET_S 4
01743 #define AR5K_QOS_NOACK_BYTE_OFFSET 0x00000180
01744 #define AR5K_QOS_NOACK_BYTE_OFFSET_S 7
01745
01746
01747
01748
01749 #define AR5K_PHY_ERR_FIL 0x810c
01750 #define AR5K_PHY_ERR_FIL_RADAR 0x00000020
01751 #define AR5K_PHY_ERR_FIL_OFDM 0x00020000
01752 #define AR5K_PHY_ERR_FIL_CCK 0x02000000
01753
01754
01755
01756
01757 #define AR5K_XRLAT_TX 0x8110
01758
01759
01760
01761
01762 #define AR5K_ACKSIFS 0x8114
01763 #define AR5K_ACKSIFS_INC 0x00000000
01764
01765
01766
01767
01768 #define AR5K_MIC_QOS_CTL 0x8118
01769 #define AR5K_MIC_QOS_CTL_OFF(_n) (1 << (_n * 2))
01770 #define AR5K_MIC_QOS_CTL_MQ_EN 0x00010000
01771
01772
01773
01774
01775 #define AR5K_MIC_QOS_SEL 0x811c
01776 #define AR5K_MIC_QOS_SEL_OFF(_n) (1 << (_n * 4))
01777
01778
01779
01780
01781 #define AR5K_MISC_MODE 0x8120
01782 #define AR5K_MISC_MODE_FBSSID_MATCH 0x00000001
01783 #define AR5K_MISC_MODE_ACKSIFS_MEM 0x00000002
01784 #define AR5K_MISC_MODE_COMBINED_MIC 0x00000004
01785
01786
01787
01788
01789
01790 #define AR5K_OFDM_FIL_CNT 0x8124
01791
01792
01793
01794
01795 #define AR5K_CCK_FIL_CNT 0x8128
01796
01797
01798
01799
01800 #define AR5K_PHYERR_CNT1 0x812c
01801 #define AR5K_PHYERR_CNT1_MASK 0x8130
01802
01803 #define AR5K_PHYERR_CNT2 0x8134
01804 #define AR5K_PHYERR_CNT2_MASK 0x8138
01805
01806
01807
01808
01809 #define AR5K_TSF_THRES 0x813c
01810
01811
01812
01813
01814
01815
01816
01817
01818
01819 #define AR5K_RATE_ACKSIFS_BASE 0x8680
01820 #define AR5K_RATE_ACKSIFS(_n) (AR5K_RATE_ACKSIFS_BSE + ((_n) << 2))
01821 #define AR5K_RATE_ACKSIFS_NORMAL 0x00000001
01822 #define AR5K_RATE_ACKSIFS_TURBO 0x00000400
01823
01824
01825
01826
01827 #define AR5K_RATE_DUR_BASE 0x8700
01828 #define AR5K_RATE_DUR(_n) (AR5K_RATE_DUR_BASE + ((_n) << 2))
01829
01830
01831
01832
01833
01834 #define AR5K_RATE2DB_BASE 0x87c0
01835 #define AR5K_RATE2DB(_n) (AR5K_RATE2DB_BASE + ((_n) << 2))
01836
01837
01838
01839
01840
01841 #define AR5K_DB2RATE_BASE 0x87e0
01842 #define AR5K_DB2RATE(_n) (AR5K_DB2RATE_BASE + ((_n) << 2))
01843
01844
01845
01846
01847
01848
01849 #define AR5K_KEYTABLE_0_5210 0x9000
01850 #define AR5K_KEYTABLE_0_5211 0x8800
01851 #define AR5K_KEYTABLE_5210(_n) (AR5K_KEYTABLE_0_5210 + ((_n) << 5))
01852 #define AR5K_KEYTABLE_5211(_n) (AR5K_KEYTABLE_0_5211 + ((_n) << 5))
01853 #define AR5K_KEYTABLE(_n) (ah->ah_version == AR5K_AR5210 ? \
01854 AR5K_KEYTABLE_5210(_n) : AR5K_KEYTABLE_5211(_n))
01855 #define AR5K_KEYTABLE_OFF(_n, x) (AR5K_KEYTABLE(_n) + (x << 2))
01856 #define AR5K_KEYTABLE_TYPE(_n) AR5K_KEYTABLE_OFF(_n, 5)
01857 #define AR5K_KEYTABLE_TYPE_40 0x00000000
01858 #define AR5K_KEYTABLE_TYPE_104 0x00000001
01859 #define AR5K_KEYTABLE_TYPE_128 0x00000003
01860 #define AR5K_KEYTABLE_TYPE_TKIP 0x00000004
01861 #define AR5K_KEYTABLE_TYPE_AES 0x00000005
01862 #define AR5K_KEYTABLE_TYPE_CCM 0x00000006
01863 #define AR5K_KEYTABLE_TYPE_NULL 0x00000007
01864 #define AR5K_KEYTABLE_ANTENNA 0x00000008
01865 #define AR5K_KEYTABLE_MAC0(_n) AR5K_KEYTABLE_OFF(_n, 6)
01866 #define AR5K_KEYTABLE_MAC1(_n) AR5K_KEYTABLE_OFF(_n, 7)
01867 #define AR5K_KEYTABLE_VALID 0x00008000
01868
01869
01870
01871 #define AR5K_KEYTABLE_MIC_OFFSET 64
01872
01873
01874
01875
01876
01877
01878
01879
01880
01881
01882
01883
01884
01885 #define AR5K_KEYTABLE_SIZE_5210 64
01886 #define AR5K_KEYTABLE_SIZE_5211 128
01887 #define AR5K_KEYTABLE_SIZE (ah->ah_version == AR5K_AR5210 ? \
01888 AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211)
01889
01890
01891
01892
01893
01894
01895
01896 #define AR5K_PHY_BASE 0x9800
01897 #define AR5K_PHY(_n) (AR5K_PHY_BASE + ((_n) << 2))
01898
01899
01900
01901
01902 #define AR5K_PHY_TST2 0x9800
01903 #define AR5K_PHY_TST2_TRIG_SEL 0x00000007
01904 #define AR5K_PHY_TST2_TRIG 0x00000010
01905 #define AR5K_PHY_TST2_CBUS_MODE 0x00000060
01906 #define AR5K_PHY_TST2_CLK32 0x00000400
01907 #define AR5K_PHY_TST2_CHANCOR_DUMP_EN 0x00000800
01908 #define AR5K_PHY_TST2_EVEN_CHANCOR_DUMP 0x00001000
01909 #define AR5K_PHY_TST2_RFSILENT_EN 0x00002000
01910 #define AR5K_PHY_TST2_ALT_RFDATA 0x00004000
01911 #define AR5K_PHY_TST2_MINI_OBS_EN 0x00008000
01912 #define AR5K_PHY_TST2_RX2_IS_RX5_INV 0x00010000
01913 #define AR5K_PHY_TST2_SLOW_CLK160 0x00020000
01914 #define AR5K_PHY_TST2_AGC_OBS_SEL_3 0x00040000
01915 #define AR5K_PHY_TST2_BBB_OBS_SEL 0x00080000
01916 #define AR5K_PHY_TST2_ADC_OBS_SEL 0x00800000
01917 #define AR5K_PHY_TST2_RX_CLR_SEL 0x08000000
01918 #define AR5K_PHY_TST2_FORCE_AGC_CLR 0x10000000
01919 #define AR5K_PHY_SHIFT_2GHZ 0x00004007
01920 #define AR5K_PHY_SHIFT_5GHZ 0x00000007
01921
01922
01923
01924
01925
01926
01927
01928
01929
01930
01931
01932 #define AR5K_PHY_TURBO 0x9804
01933 #define AR5K_PHY_TURBO_MODE 0x00000001
01934 #define AR5K_PHY_TURBO_SHORT 0x00000002
01935 #define AR5K_PHY_TURBO_MIMO 0x00000004
01936
01937
01938
01939
01940
01941 #define AR5K_PHY_AGC 0x9808
01942 #define AR5K_PHY_TST1 0x9808
01943 #define AR5K_PHY_AGC_DISABLE 0x08000000
01944 #define AR5K_PHY_TST1_TXHOLD 0x00003800
01945 #define AR5K_PHY_TST1_TXSRC_SRC 0x00000002
01946 #define AR5K_PHY_TST1_TXSRC_SRC_S 1
01947 #define AR5K_PHY_TST1_TXSRC_ALT 0x00000080
01948 #define AR5K_PHY_TST1_TXSRC_ALT_S 7
01949
01950
01951
01952
01953
01954 #define AR5K_PHY_TIMING_3 0x9814
01955 #define AR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000
01956 #define AR5K_PHY_TIMING_3_DSC_MAN_S 17
01957 #define AR5K_PHY_TIMING_3_DSC_EXP 0x0001e000
01958 #define AR5K_PHY_TIMING_3_DSC_EXP_S 13
01959
01960
01961
01962
01963 #define AR5K_PHY_CHIP_ID 0x9818
01964
01965
01966
01967
01968 #define AR5K_PHY_ACT 0x981c
01969 #define AR5K_PHY_ACT_ENABLE 0x00000001
01970 #define AR5K_PHY_ACT_DISABLE 0x00000002
01971
01972
01973
01974
01975 #define AR5K_PHY_RF_CTL2 0x9824
01976 #define AR5K_PHY_RF_CTL2_TXF2TXD_START 0x0000000f
01977 #define AR5K_PHY_RF_CTL2_TXF2TXD_START_S 0
01978
01979 #define AR5K_PHY_RF_CTL3 0x9828
01980 #define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000ff00
01981 #define AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S 8
01982
01983 #define AR5K_PHY_ADC_CTL 0x982c
01984 #define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF 0x00000003
01985 #define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_S 0
01986 #define AR5K_PHY_ADC_CTL_PWD_DAC_OFF 0x00002000
01987 #define AR5K_PHY_ADC_CTL_PWD_BAND_GAP_OFF 0x00004000
01988 #define AR5K_PHY_ADC_CTL_PWD_ADC_OFF 0x00008000
01989 #define AR5K_PHY_ADC_CTL_INBUFGAIN_ON 0x00030000
01990 #define AR5K_PHY_ADC_CTL_INBUFGAIN_ON_S 16
01991
01992 #define AR5K_PHY_RF_CTL4 0x9834
01993 #define AR5K_PHY_RF_CTL4_TXF2XPA_A_ON 0x00000001
01994 #define AR5K_PHY_RF_CTL4_TXF2XPA_B_ON 0x00000100
01995 #define AR5K_PHY_RF_CTL4_TXE2XPA_A_OFF 0x00010000
01996 #define AR5K_PHY_RF_CTL4_TXE2XPA_B_OFF 0x01000000
01997
01998
01999
02000
02001
02002 #define AR5K_PHY_PA_CTL 0x9838
02003 #define AR5K_PHY_PA_CTL_XPA_A_HI 0x00000001
02004 #define AR5K_PHY_PA_CTL_XPA_B_HI 0x00000002
02005 #define AR5K_PHY_PA_CTL_XPA_A_EN 0x00000004
02006 #define AR5K_PHY_PA_CTL_XPA_B_EN 0x00000008
02007
02008
02009
02010
02011 #define AR5K_PHY_SETTLING 0x9844
02012 #define AR5K_PHY_SETTLING_AGC 0x0000007f
02013 #define AR5K_PHY_SETTLING_AGC_S 0
02014 #define AR5K_PHY_SETTLING_SWITCH 0x00003f80
02015 #define AR5K_PHY_SETTLING_SWITCH_S 7
02016
02017
02018
02019
02020 #define AR5K_PHY_GAIN 0x9848
02021 #define AR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000
02022 #define AR5K_PHY_GAIN_TXRX_ATTEN_S 12
02023 #define AR5K_PHY_GAIN_TXRX_RF_MAX 0x007c0000
02024 #define AR5K_PHY_GAIN_TXRX_RF_MAX_S 18
02025
02026 #define AR5K_PHY_GAIN_OFFSET 0x984c
02027 #define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000
02028
02029
02030
02031
02032
02033 #define AR5K_PHY_DESIRED_SIZE 0x9850
02034 #define AR5K_PHY_DESIRED_SIZE_ADC 0x000000ff
02035 #define AR5K_PHY_DESIRED_SIZE_ADC_S 0
02036 #define AR5K_PHY_DESIRED_SIZE_PGA 0x0000ff00
02037 #define AR5K_PHY_DESIRED_SIZE_PGA_S 8
02038 #define AR5K_PHY_DESIRED_SIZE_TOT 0x0ff00000
02039 #define AR5K_PHY_DESIRED_SIZE_TOT_S 20
02040
02041
02042
02043
02044
02045 #define AR5K_PHY_SIG 0x9858
02046 #define AR5K_PHY_SIG_FIRSTEP 0x0003f000
02047 #define AR5K_PHY_SIG_FIRSTEP_S 12
02048 #define AR5K_PHY_SIG_FIRPWR 0x03fc0000
02049 #define AR5K_PHY_SIG_FIRPWR_S 18
02050
02051
02052
02053
02054
02055 #define AR5K_PHY_AGCCOARSE 0x985c
02056 #define AR5K_PHY_AGCCOARSE_LO 0x00007f80
02057 #define AR5K_PHY_AGCCOARSE_LO_S 7
02058 #define AR5K_PHY_AGCCOARSE_HI 0x003f8000
02059 #define AR5K_PHY_AGCCOARSE_HI_S 15
02060
02061
02062
02063
02064 #define AR5K_PHY_AGCCTL 0x9860
02065 #define AR5K_PHY_AGCCTL_CAL 0x00000001
02066 #define AR5K_PHY_AGCCTL_NF 0x00000002
02067 #define AR5K_PHY_AGCCTL_OFDM_DIV_DIS 0x00000008
02068 #define AR5K_PHY_AGCCTL_NF_EN 0x00008000
02069 #define AR5K_PHY_AGCTL_FLTR_CAL 0x00010000
02070 #define AR5K_PHY_AGCCTL_NF_NOUPDATE 0x00020000
02071
02072
02073
02074
02075 #define AR5K_PHY_NF 0x9864
02076 #define AR5K_PHY_NF_M 0x000001ff
02077 #define AR5K_PHY_NF_ACTIVE 0x00000100
02078 #define AR5K_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_PHY_NF_M)
02079 #define AR5K_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_PHY_NF_M) + 1)
02080 #define AR5K_PHY_NF_SVAL(_n) (((_n) & AR5K_PHY_NF_M) | (1 << 9))
02081 #define AR5K_PHY_NF_THRESH62 0x0007f000
02082 #define AR5K_PHY_NF_THRESH62_S 12
02083 #define AR5K_PHY_NF_MINCCA_PWR 0x0ff80000
02084 #define AR5K_PHY_NF_MINCCA_PWR_S 19
02085
02086
02087
02088
02089 #define AR5K_PHY_ADCSAT 0x9868
02090 #define AR5K_PHY_ADCSAT_ICNT 0x0001f800
02091 #define AR5K_PHY_ADCSAT_ICNT_S 11
02092 #define AR5K_PHY_ADCSAT_THR 0x000007e0
02093 #define AR5K_PHY_ADCSAT_THR_S 5
02094
02095
02096
02097
02098
02099
02100 #define AR5K_PHY_WEAK_OFDM_HIGH_THR 0x9868
02101 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT 0x0000001f
02102 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT_S 0
02103 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1 0x00fe0000
02104 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_S 17
02105 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2 0x7f000000
02106 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_S 24
02107
02108
02109 #define AR5K_PHY_WEAK_OFDM_LOW_THR 0x986c
02110 #define AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN 0x00000001
02111 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT 0x00003f00
02112 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT_S 8
02113 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M1 0x001fc000
02114 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M1_S 14
02115 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2 0x0fe00000
02116 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_S 21
02117
02118
02119
02120
02121
02122 #define AR5K_PHY_SCR 0x9870
02123
02124 #define AR5K_PHY_SLMT 0x9874
02125 #define AR5K_PHY_SLMT_32MHZ 0x0000007f
02126
02127 #define AR5K_PHY_SCAL 0x9878
02128 #define AR5K_PHY_SCAL_32MHZ 0x0000000e
02129 #define AR5K_PHY_SCAL_32MHZ_2417 0x0000000a
02130 #define AR5K_PHY_SCAL_32MHZ_HB63 0x00000032
02131
02132
02133
02134
02135 #define AR5K_PHY_PLL 0x987c
02136 #define AR5K_PHY_PLL_20MHZ 0x00000013
02137
02138 #define AR5K_PHY_PLL_40MHZ_5211 0x00000018
02139 #define AR5K_PHY_PLL_40MHZ_5212 0x000000aa
02140 #define AR5K_PHY_PLL_40MHZ_5413 0x00000004
02141 #define AR5K_PHY_PLL_40MHZ (ah->ah_version == AR5K_AR5211 ? \
02142 AR5K_PHY_PLL_40MHZ_5211 : AR5K_PHY_PLL_40MHZ_5212)
02143
02144 #define AR5K_PHY_PLL_44MHZ_5211 0x00000019
02145 #define AR5K_PHY_PLL_44MHZ_5212 0x000000ab
02146 #define AR5K_PHY_PLL_44MHZ (ah->ah_version == AR5K_AR5211 ? \
02147 AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212)
02148
02149 #define AR5K_PHY_PLL_RF5111 0x00000000
02150 #define AR5K_PHY_PLL_RF5112 0x00000040
02151 #define AR5K_PHY_PLL_HALF_RATE 0x00000100
02152 #define AR5K_PHY_PLL_QUARTER_RATE 0x00000200
02153
02154
02155
02156
02157
02158
02159
02160
02161
02162
02163 #define AR5K_RF_BUFFER 0x989c
02164 #define AR5K_RF_BUFFER_CONTROL_0 0x98c0
02165 #define AR5K_RF_BUFFER_CONTROL_1 0x98c4
02166 #define AR5K_RF_BUFFER_CONTROL_2 0x98cc
02167
02168 #define AR5K_RF_BUFFER_CONTROL_3 0x98d0
02169
02170
02171
02172 #define AR5K_RF_BUFFER_CONTROL_4 0x98d4
02173
02174
02175
02176
02177 #define AR5K_RF_BUFFER_CONTROL_5 0x98d8
02178
02179
02180
02181
02182 #define AR5K_RF_BUFFER_CONTROL_6 0x98dc
02183
02184
02185
02186
02187 #define AR5K_PHY_RFSTG 0x98d4
02188 #define AR5K_PHY_RFSTG_DISABLE 0x00000021
02189
02190
02191
02192
02193 #define AR5K_PHY_BIN_MASK_1 0x9900
02194 #define AR5K_PHY_BIN_MASK_2 0x9904
02195 #define AR5K_PHY_BIN_MASK_3 0x9908
02196
02197 #define AR5K_PHY_BIN_MASK_CTL 0x990c
02198 #define AR5K_PHY_BIN_MASK_CTL_MASK_4 0x00003fff
02199 #define AR5K_PHY_BIN_MASK_CTL_MASK_4_S 0
02200 #define AR5K_PHY_BIN_MASK_CTL_RATE 0xff000000
02201 #define AR5K_PHY_BIN_MASK_CTL_RATE_S 24
02202
02203
02204
02205
02206 #define AR5K_PHY_ANT_CTL 0x9910
02207 #define AR5K_PHY_ANT_CTL_TXRX_EN 0x00000001
02208 #define AR5K_PHY_ANT_CTL_SECTORED_ANT 0x00000004
02209 #define AR5K_PHY_ANT_CTL_HITUNE5 0x00000008
02210 #define AR5K_PHY_ANT_CTL_SWTABLE_IDLE 0x000003f0
02211 #define AR5K_PHY_ANT_CTL_SWTABLE_IDLE_S 4
02212
02213
02214
02215
02216 #define AR5K_PHY_RX_DELAY 0x9914
02217 #define AR5K_PHY_RX_DELAY_M 0x00003fff
02218
02219
02220
02221
02222 #define AR5K_PHY_MAX_RX_LEN 0x991c
02223
02224
02225
02226
02227
02228 #define AR5K_PHY_IQ 0x9920
02229 #define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f
02230 #define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0
02231 #define AR5K_PHY_IQ_CORR_Q_I_COFF_S 5
02232 #define AR5K_PHY_IQ_CORR_ENABLE 0x00000800
02233 #define AR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000
02234 #define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 12
02235 #define AR5K_PHY_IQ_RUN 0x00010000
02236 #define AR5K_PHY_IQ_USE_PT_DF 0x00020000
02237 #define AR5K_PHY_IQ_EARLY_TRIG_THR 0x00200000
02238 #define AR5K_PHY_IQ_PILOT_MASK_EN 0x10000000
02239 #define AR5K_PHY_IQ_CHAN_MASK_EN 0x20000000
02240 #define AR5K_PHY_IQ_SPUR_FILT_EN 0x40000000
02241 #define AR5K_PHY_IQ_SPUR_RSSI_EN 0x80000000
02242
02243
02244
02245
02246
02247
02248 #define AR5K_PHY_OFDM_SELFCORR 0x9924
02249 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN 0x00000001
02250 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1 0x000000fe
02251 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_S 1
02252 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3 0x00000100
02253 #define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN 0x00008000
02254 #define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR 0x00010000
02255 #define AR5K_PHY_OFDM_SELFCORR_LSCTHR_HIRSSI 0x00800000
02256
02257
02258
02259
02260 #define AR5K_PHY_WARM_RESET 0x9928
02261
02262
02263
02264
02265 #define AR5K_PHY_CTL 0x992c
02266 #define AR5K_PHY_CTL_RX_DRAIN_RATE 0x00000001
02267 #define AR5K_PHY_CTL_LATE_TX_SIG_SYM 0x00000002
02268 #define AR5K_PHY_CTL_GEN_SCRAMBLER 0x00000004
02269 #define AR5K_PHY_CTL_TX_ANT_SEL 0x00000008
02270 #define AR5K_PHY_CTL_TX_ANT_STATIC 0x00000010
02271 #define AR5K_PHY_CTL_RX_ANT_SEL 0x00000020
02272 #define AR5K_PHY_CTL_RX_ANT_STATIC 0x00000040
02273 #define AR5K_PHY_CTL_LOW_FREQ_SLE_EN 0x00000080
02274
02275
02276
02277
02278 #define AR5K_PHY_PAPD_PROBE 0x9930
02279 #define AR5K_PHY_PAPD_PROBE_SH_HI_PAR 0x00000001
02280 #define AR5K_PHY_PAPD_PROBE_PCDAC_BIAS 0x00000002
02281 #define AR5K_PHY_PAPD_PROBE_COMP_GAIN 0x00000040
02282 #define AR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00
02283 #define AR5K_PHY_PAPD_PROBE_TXPOWER_S 9
02284 #define AR5K_PHY_PAPD_PROBE_TX_NEXT 0x00008000
02285 #define AR5K_PHY_PAPD_PROBE_PREDIST_EN 0x00010000
02286 #define AR5K_PHY_PAPD_PROBE_TYPE 0x01800000
02287 #define AR5K_PHY_PAPD_PROBE_TYPE_S 23
02288 #define AR5K_PHY_PAPD_PROBE_TYPE_OFDM 0
02289 #define AR5K_PHY_PAPD_PROBE_TYPE_XR 1
02290 #define AR5K_PHY_PAPD_PROBE_TYPE_CCK 2
02291 #define AR5K_PHY_PAPD_PROBE_GAINF 0xfe000000
02292 #define AR5K_PHY_PAPD_PROBE_GAINF_S 25
02293 #define AR5K_PHY_PAPD_PROBE_INI_5111 0x00004883
02294 #define AR5K_PHY_PAPD_PROBE_INI_5112 0x00004882
02295
02296
02297
02298
02299 #define AR5K_PHY_TXPOWER_RATE1 0x9934
02300 #define AR5K_PHY_TXPOWER_RATE2 0x9938
02301 #define AR5K_PHY_TXPOWER_RATE_MAX 0x993c
02302 #define AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE 0x00000040
02303 #define AR5K_PHY_TXPOWER_RATE3 0xa234
02304 #define AR5K_PHY_TXPOWER_RATE4 0xa238
02305
02306
02307
02308
02309 #define AR5K_PHY_FRAME_CTL_5210 0x9804
02310 #define AR5K_PHY_FRAME_CTL_5211 0x9944
02311 #define AR5K_PHY_FRAME_CTL (ah->ah_version == AR5K_AR5210 ? \
02312 AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211)
02313
02314 #define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038
02315 #define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3
02316 #define AR5K_PHY_FRAME_CTL_PREP_CHINFO 0x00010000
02317 #define AR5K_PHY_FRAME_CTL_EMU 0x80000000
02318 #define AR5K_PHY_FRAME_CTL_EMU_S 31
02319
02320 #define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000
02321 #define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000
02322 #define AR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000
02323 #define AR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000
02324 #define AR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000
02325 #define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000
02326 #define AR5K_PHY_FRAME_CTL_INI AR5K_PHY_FRAME_CTL_SERVICE_ERR | \
02327 AR5K_PHY_FRAME_CTL_TXURN_ERR | \
02328 AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \
02329 AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \
02330 AR5K_PHY_FRAME_CTL_PARITY_ERR | \
02331 AR5K_PHY_FRAME_CTL_TIMING_ERR
02332
02333
02334
02335
02336 #define AR5K_PHY_TX_PWR_ADJ 0x994c
02337 #define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA 0x00000fc0
02338 #define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA_S 6
02339 #define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX 0x00fc0000
02340 #define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX_S 18
02341
02342
02343
02344
02345 #define AR5K_PHY_RADAR 0x9954
02346 #define AR5K_PHY_RADAR_ENABLE 0x00000001
02347 #define AR5K_PHY_RADAR_DISABLE 0x00000000
02348 #define AR5K_PHY_RADAR_INBANDTHR 0x0000003e
02349
02350
02351 #define AR5K_PHY_RADAR_INBANDTHR_S 1
02352
02353 #define AR5K_PHY_RADAR_PRSSI_THR 0x00000fc0
02354
02355
02356 #define AR5K_PHY_RADAR_PRSSI_THR_S 6
02357
02358 #define AR5K_PHY_RADAR_PHEIGHT_THR 0x0003f000
02359
02360
02361 #define AR5K_PHY_RADAR_PHEIGHT_THR_S 12
02362
02363 #define AR5K_PHY_RADAR_RSSI_THR 0x00fc0000
02364
02365
02366 #define AR5K_PHY_RADAR_RSSI_THR_S 18
02367
02368 #define AR5K_PHY_RADAR_FIRPWR_THR 0x7f000000
02369
02370
02371
02372 #define AR5K_PHY_RADAR_FIRPWR_THRS 24
02373
02374
02375
02376
02377 #define AR5K_PHY_ANT_SWITCH_TABLE_0 0x9960
02378 #define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964
02379
02380
02381
02382
02383 #define AR5K_PHY_NFTHRES 0x9968
02384
02385
02386
02387
02388 #define AR5K_PHY_SIGMA_DELTA 0x996C
02389 #define AR5K_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
02390 #define AR5K_PHY_SIGMA_DELTA_ADC_SEL_S 0
02391 #define AR5K_PHY_SIGMA_DELTA_FILT2 0x000000f8
02392 #define AR5K_PHY_SIGMA_DELTA_FILT2_S 3
02393 #define AR5K_PHY_SIGMA_DELTA_FILT1 0x00001f00
02394 #define AR5K_PHY_SIGMA_DELTA_FILT1_S 8
02395 #define AR5K_PHY_SIGMA_DELTA_ADC_CLIP 0x01ffe000
02396 #define AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S 13
02397
02398
02399
02400
02401 #define AR5K_PHY_RESTART 0x9970
02402 #define AR5K_PHY_RESTART_DIV_GC 0x001c0000
02403 #define AR5K_PHY_RESTART_DIV_GC_S 18
02404
02405
02406
02407
02408 #define AR5K_PHY_RFBUS_REQ 0x997C
02409 #define AR5K_PHY_RFBUS_REQ_REQUEST 0x00000001
02410
02411
02412
02413
02414 #define AR5K_PHY_TIMING_7 0x9980
02415 #define AR5K_PHY_TIMING_8 0x9984
02416 #define AR5K_PHY_TIMING_8_PILOT_MASK_2 0x000fffff
02417 #define AR5K_PHY_TIMING_8_PILOT_MASK_2_S 0
02418
02419 #define AR5K_PHY_BIN_MASK2_1 0x9988
02420 #define AR5K_PHY_BIN_MASK2_2 0x998c
02421 #define AR5K_PHY_BIN_MASK2_3 0x9990
02422
02423 #define AR5K_PHY_BIN_MASK2_4 0x9994
02424 #define AR5K_PHY_BIN_MASK2_4_MASK_4 0x00003fff
02425 #define AR5K_PHY_BIN_MASK2_4_MASK_4_S 0
02426
02427 #define AR5K_PHY_TIMING_9 0x9998
02428 #define AR5K_PHY_TIMING_10 0x999c
02429 #define AR5K_PHY_TIMING_10_PILOT_MASK_2 0x000fffff
02430 #define AR5K_PHY_TIMING_10_PILOT_MASK_2_S 0
02431
02432
02433
02434
02435 #define AR5K_PHY_TIMING_11 0x99a0
02436 #define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE 0x000fffff
02437 #define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE_S 0
02438 #define AR5K_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000
02439 #define AR5K_PHY_TIMING_11_SPUR_FREQ_SD_S 20
02440 #define AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC 0x40000000
02441 #define AR5K_PHY_TIMING_11_USE_SPUR_IN_SELFCOR 0x80000000
02442
02443
02444
02445
02446 #define AR5K_BB_GAIN_BASE 0x9b00
02447 #define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2))
02448 #define AR5K_RF_GAIN_BASE 0x9a00
02449 #define AR5K_RF_GAIN(_n) (AR5K_RF_GAIN_BASE + ((_n) << 2))
02450
02451
02452
02453
02454 #define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10
02455 #define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14
02456 #define AR5K_PHY_IQRES_CAL_CORR 0x9c18
02457
02458
02459
02460
02461 #define AR5K_PHY_CURRENT_RSSI 0x9c1c
02462
02463
02464
02465
02466 #define AR5K_PHY_RFBUS_GRANT 0x9c20
02467 #define AR5K_PHY_RFBUS_GRANT_OK 0x00000001
02468
02469
02470
02471
02472 #define AR5K_PHY_ADC_TEST 0x9c24
02473 #define AR5K_PHY_ADC_TEST_I 0x00000001
02474 #define AR5K_PHY_ADC_TEST_Q 0x00000200
02475
02476
02477
02478
02479 #define AR5K_PHY_DAC_TEST 0x9c28
02480 #define AR5K_PHY_DAC_TEST_I 0x00000001
02481 #define AR5K_PHY_DAC_TEST_Q 0x00000200
02482
02483
02484
02485
02486 #define AR5K_PHY_PTAT 0x9c2c
02487
02488
02489
02490
02491 #define AR5K_PHY_BAD_TX_RATE 0x9c30
02492
02493
02494
02495
02496 #define AR5K_PHY_SPUR_PWR 0x9c34
02497 #define AR5K_PHY_SPUR_PWR_I 0x00000001
02498 #define AR5K_PHY_SPUR_PWR_Q 0x00000100
02499 #define AR5K_PHY_SPUR_PWR_FILT 0x00010000
02500
02501
02502
02503
02504 #define AR5K_PHY_CHAN_STATUS 0x9c38
02505 #define AR5K_PHY_CHAN_STATUS_BT_ACT 0x00000001
02506 #define AR5K_PHY_CHAN_STATUS_RX_CLR_RAW 0x00000002
02507 #define AR5K_PHY_CHAN_STATUS_RX_CLR_MAC 0x00000004
02508 #define AR5K_PHY_CHAN_STATUS_RX_CLR_PAP 0x00000008
02509
02510
02511
02512
02513 #define AR5K_PHY_HEAVY_CLIP_ENABLE 0x99e0
02514
02515
02516
02517
02518 #define AR5K_PHY_SCLOCK 0x99f0
02519 #define AR5K_PHY_SCLOCK_32MHZ 0x0000000c
02520 #define AR5K_PHY_SDELAY 0x99f4
02521 #define AR5K_PHY_SDELAY_32MHZ 0x000000ff
02522 #define AR5K_PHY_SPENDING 0x99f8
02523
02524
02525
02526
02527
02528
02529 #define AR5K_PHY_PAPD_I_BASE 0xa000
02530 #define AR5K_PHY_PAPD_I(_n) (AR5K_PHY_PAPD_I_BASE + ((_n) << 2))
02531
02532
02533
02534
02535 #define AR5K_PHY_PCDAC_TXPOWER_BASE 0xa180
02536 #define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2))
02537
02538
02539
02540
02541 #define AR5K_PHY_MODE 0x0a200
02542 #define AR5K_PHY_MODE_MOD 0x00000001
02543 #define AR5K_PHY_MODE_MOD_OFDM 0
02544 #define AR5K_PHY_MODE_MOD_CCK 1
02545 #define AR5K_PHY_MODE_FREQ 0x00000002
02546 #define AR5K_PHY_MODE_FREQ_5GHZ 0
02547 #define AR5K_PHY_MODE_FREQ_2GHZ 2
02548 #define AR5K_PHY_MODE_MOD_DYN 0x00000004
02549 #define AR5K_PHY_MODE_RAD 0x00000008
02550 #define AR5K_PHY_MODE_RAD_RF5111 0
02551 #define AR5K_PHY_MODE_RAD_RF5112 8
02552 #define AR5K_PHY_MODE_XR 0x00000010
02553 #define AR5K_PHY_MODE_HALF_RATE 0x00000020
02554 #define AR5K_PHY_MODE_QUARTER_RATE 0x00000040
02555
02556
02557
02558
02559 #define AR5K_PHY_CCKTXCTL 0xa204
02560 #define AR5K_PHY_CCKTXCTL_WORLD 0x00000000
02561 #define AR5K_PHY_CCKTXCTL_JAPAN 0x00000010
02562 #define AR5K_PHY_CCKTXCTL_SCRAMBLER_DIS 0x00000001
02563 #define AR5K_PHY_CCKTXCTK_DAC_SCALE 0x00000004
02564
02565
02566
02567
02568 #define AR5K_PHY_CCK_CROSSCORR 0xa208
02569 #define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR 0x0000003f
02570 #define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR_S 0
02571
02572
02573 #define AR5K_PHY_FAST_ANT_DIV 0xa208
02574 #define AR5K_PHY_FAST_ANT_DIV_EN 0x00002000
02575
02576
02577
02578
02579 #define AR5K_PHY_GAIN_2GHZ 0xa20c
02580 #define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000
02581 #define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S 18
02582 #define AR5K_PHY_GAIN_2GHZ_INI_5111 0x6480416c
02583
02584 #define AR5K_PHY_CCK_RX_CTL_4 0xa21c
02585 #define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT 0x01f80000
02586 #define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT_S 19
02587
02588 #define AR5K_PHY_DAG_CCK_CTL 0xa228
02589 #define AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR 0x00000200
02590 #define AR5K_PHY_DAG_CCK_CTL_RSSI_THR 0x0001fc00
02591 #define AR5K_PHY_DAG_CCK_CTL_RSSI_THR_S 10
02592
02593 #define AR5K_PHY_FAST_ADC 0xa24c
02594
02595 #define AR5K_PHY_BLUETOOTH 0xa254
02596
02597
02598
02599
02600
02601 #define AR5K_PHY_TPC_RG1 0xa258
02602 #define AR5K_PHY_TPC_RG1_NUM_PD_GAIN 0x0000c000
02603 #define AR5K_PHY_TPC_RG1_NUM_PD_GAIN_S 14
02604 #define AR5K_PHY_TPC_RG1_PDGAIN_1 0x00030000
02605 #define AR5K_PHY_TPC_RG1_PDGAIN_1_S 16
02606 #define AR5K_PHY_TPC_RG1_PDGAIN_2 0x000c0000
02607 #define AR5K_PHY_TPC_RG1_PDGAIN_2_S 18
02608 #define AR5K_PHY_TPC_RG1_PDGAIN_3 0x00300000
02609 #define AR5K_PHY_TPC_RG1_PDGAIN_3_S 20
02610
02611 #define AR5K_PHY_TPC_RG5 0xa26C
02612 #define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP 0x0000000F
02613 #define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP_S 0
02614 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1 0x000003F0
02615 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1_S 4
02616 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2 0x0000FC00
02617 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2_S 10
02618 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3 0x003F0000
02619 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3_S 16
02620 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4 0x0FC00000
02621 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S 22
02622
02623
02624
02625
02626 #define AR5K_PHY_PDADC_TXPOWER_BASE 0xa280
02627 #define AR5K_PHY_PDADC_TXPOWER(_n) (AR5K_PHY_PDADC_TXPOWER_BASE + ((_n) << 2))