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00049 #ifndef _ATH5K_H
00050 #define _ATH5K_H
00051
00052 #include <time.h>
00053 #include "ath5k_linux_layer.h"
00054 #include "mac80211.h"
00055
00056
00057
00058 #include "desc.h"
00059
00060
00061
00062
00063 #include "eeprom.h"
00064
00065
00066 #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007
00067 #define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011
00068 #define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012
00069 #define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013
00070 #define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013
00071 #define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013
00072 #define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207
00073 #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014
00074 #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107
00075 #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113
00076 #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112
00077 #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013
00078 #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12
00079 #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b
00080 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052
00081 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057
00082 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058
00083 #define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014
00084 #define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015
00085 #define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016
00086 #define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017
00087 #define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018
00088 #define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019
00089 #define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a
00090 #define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b
00091 #define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c
00092 #define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023
00093 #define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024
00094
00095
00096
00097
00098
00099 #define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__)
00100
00101 #define ATH5K_INFO(_sc, _fmt, ...) \
00102 printk("ath5k info:" _fmt, ##__VA_ARGS__)
00103
00104 #define ATH5K_WARN(_sc, _fmt, ...) \
00105 printk("ath5k warn:" _fmt, ##__VA_ARGS__)
00106
00107 #define ATH5K_ERR(_sc, _fmt, ...) \
00108 printk("ath5k error:" _fmt, ##__VA_ARGS__)
00109
00110
00111
00112
00113
00114
00115
00116
00117 #define AR5K_REG_SM(_val, _flags) \
00118 (((_val) << _flags##_S) & (_flags))
00119
00120
00121 #define AR5K_REG_MS(_val, _flags) \
00122 (((_val) & (_flags)) >> _flags##_S)
00123
00124
00125
00126
00127
00128
00129 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \
00130 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
00131 (((_val) << _flags##_S) & (_flags)), _reg)
00132
00133 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \
00134 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
00135 (_mask)) | (_flags), _reg)
00136
00137 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \
00138 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
00139
00140 #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \
00141 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
00142
00143
00144 #define AR5K_PHY_READ(ah, _reg) \
00145 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
00146
00147 #define AR5K_PHY_WRITE(ah, _reg, _val) \
00148 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
00149
00150
00151 #define AR5K_REG_READ_Q(ah, _reg, _queue) \
00152 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
00153
00154 #define AR5K_REG_WRITE_Q(ah, _reg, _queue) \
00155 ath5k_hw_reg_write(ah, (1 << _queue), _reg)
00156
00157 #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
00158 _reg |= 1 << _queue; \
00159 } while (0)
00160
00161 #define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
00162 _reg &= ~(1 << _queue); \
00163 } while (0)
00164
00165
00166 #define AR5K_REG_WAIT(_i) do { \
00167 if (_i % 64) \
00168 udelay(1); \
00169 } while (0)
00170
00171
00172 #define AR5K_INI_RFGAIN_5GHZ 0
00173 #define AR5K_INI_RFGAIN_2GHZ 1
00174
00175
00176 #define AR5K_INI_VAL_11A 0
00177 #define AR5K_INI_VAL_11A_TURBO 1
00178 #define AR5K_INI_VAL_11B 2
00179 #define AR5K_INI_VAL_11G 3
00180 #define AR5K_INI_VAL_11G_TURBO 4
00181 #define AR5K_INI_VAL_XR 0
00182 #define AR5K_INI_VAL_MAX 5
00183
00184
00185 #define AR5K_LOW_ID(_a)( \
00186 (_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \
00187 )
00188
00189 #define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8)
00190
00191
00192
00193
00194
00195 #define AR5K_TUNE_DMA_BEACON_RESP 2
00196 #define AR5K_TUNE_SW_BEACON_RESP 10
00197 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
00198 #define AR5K_TUNE_RADAR_ALERT false
00199 #define AR5K_TUNE_MIN_TX_FIFO_THRES 1
00200 #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1)
00201 #define AR5K_TUNE_REGISTER_TIMEOUT 20000
00202
00203
00204 #define AR5K_TUNE_RSSI_THRES 129
00205
00206
00207
00208
00209
00210 #define AR5K_TUNE_BMISS_THRES 7
00211 #define AR5K_TUNE_REGISTER_DWELL_TIME 20000
00212 #define AR5K_TUNE_BEACON_INTERVAL 100
00213 #define AR5K_TUNE_AIFS 2
00214 #define AR5K_TUNE_AIFS_11B 2
00215 #define AR5K_TUNE_AIFS_XR 0
00216 #define AR5K_TUNE_CWMIN 15
00217 #define AR5K_TUNE_CWMIN_11B 31
00218 #define AR5K_TUNE_CWMIN_XR 3
00219 #define AR5K_TUNE_CWMAX 1023
00220 #define AR5K_TUNE_CWMAX_11B 1023
00221 #define AR5K_TUNE_CWMAX_XR 7
00222 #define AR5K_TUNE_NOISE_FLOOR -72
00223 #define AR5K_TUNE_MAX_TXPOWER 63
00224 #define AR5K_TUNE_DEFAULT_TXPOWER 36
00225 #define AR5K_TUNE_TPC_TXPOWER false
00226 #define AR5K_TUNE_HWTXTRIES 0
00227
00228 #define AR5K_INIT_CARR_SENSE_EN 1
00229
00230
00231 #if defined(__BIG_ENDIAN)
00232 #define AR5K_INIT_CFG ( \
00233 AR5K_CFG_SWTD | AR5K_CFG_SWRD \
00234 )
00235 #else
00236 #define AR5K_INIT_CFG 0x00000000
00237 #endif
00238
00239
00240 #define AR5K_INIT_CYCRSSI_THR1 2
00241 #define AR5K_INIT_TX_LATENCY 502
00242 #define AR5K_INIT_USEC 39
00243 #define AR5K_INIT_USEC_TURBO 79
00244 #define AR5K_INIT_USEC_32 31
00245 #define AR5K_INIT_SLOT_TIME 396
00246 #define AR5K_INIT_SLOT_TIME_TURBO 480
00247 #define AR5K_INIT_ACK_CTS_TIMEOUT 1024
00248 #define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
00249 #define AR5K_INIT_PROG_IFS 920
00250 #define AR5K_INIT_PROG_IFS_TURBO 960
00251 #define AR5K_INIT_EIFS 3440
00252 #define AR5K_INIT_EIFS_TURBO 6880
00253 #define AR5K_INIT_SIFS 560
00254 #define AR5K_INIT_SIFS_TURBO 480
00255 #define AR5K_INIT_SH_RETRY 10
00256 #define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY
00257 #define AR5K_INIT_SSH_RETRY 32
00258 #define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY
00259 #define AR5K_INIT_TX_RETRY 10
00260
00261 #define AR5K_INIT_TRANSMIT_LATENCY ( \
00262 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
00263 (AR5K_INIT_USEC) \
00264 )
00265 #define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \
00266 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
00267 (AR5K_INIT_USEC_TURBO) \
00268 )
00269 #define AR5K_INIT_PROTO_TIME_CNTRL ( \
00270 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \
00271 (AR5K_INIT_PROG_IFS) \
00272 )
00273 #define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \
00274 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \
00275 (AR5K_INIT_PROG_IFS_TURBO) \
00276 )
00277
00278
00279 #define AR5K_TXQ_USEDEFAULT ((u32) -1)
00280
00281
00282
00283
00284 enum ath5k_version {
00285 AR5K_AR5210 = 0,
00286 AR5K_AR5211 = 1,
00287 AR5K_AR5212 = 2,
00288 };
00289
00290
00291 enum ath5k_radio {
00292 AR5K_RF5110 = 0,
00293 AR5K_RF5111 = 1,
00294 AR5K_RF5112 = 2,
00295 AR5K_RF2413 = 3,
00296 AR5K_RF5413 = 4,
00297 AR5K_RF2316 = 5,
00298 AR5K_RF2317 = 6,
00299 AR5K_RF2425 = 7,
00300 };
00301
00302
00303
00304
00305 struct ath5k_device_ids
00306 {
00307 unsigned short vendor, device;
00308 unsigned short driver_data;
00309 const char *name;
00310 };
00311
00312 enum ath5k_srev_type {
00313 AR5K_VERSION_MAC,
00314 AR5K_VERSION_RAD,
00315 };
00316
00317 struct ath5k_srev_name {
00318 const char *sr_name;
00319 enum ath5k_srev_type sr_type;
00320 u_int sr_val;
00321 };
00322
00323 #define AR5K_SREV_UNKNOWN 0xffff
00324
00325 #define AR5K_SREV_AR5210 0x00
00326 #define AR5K_SREV_AR5311 0x10
00327 #define AR5K_SREV_AR5311A 0x20
00328 #define AR5K_SREV_AR5311B 0x30
00329 #define AR5K_SREV_AR5211 0x40
00330 #define AR5K_SREV_AR5212 0x50
00331 #define AR5K_SREV_AR5212_V4 0x54
00332 #define AR5K_SREV_AR5213 0x55
00333 #define AR5K_SREV_AR5213A 0x59
00334 #define AR5K_SREV_AR2413 0x78
00335 #define AR5K_SREV_AR2414 0x70
00336 #define AR5K_SREV_AR5424 0x90
00337 #define AR5K_SREV_AR5413 0xa4
00338 #define AR5K_SREV_AR5414 0xa0
00339 #define AR5K_SREV_AR2415 0xb0
00340 #define AR5K_SREV_AR5416 0xc0
00341 #define AR5K_SREV_AR5418 0xca
00342 #define AR5K_SREV_AR2425 0xe0
00343 #define AR5K_SREV_AR2417 0xf0
00344
00345 #define AR5K_SREV_RAD_5110 0x00
00346 #define AR5K_SREV_RAD_5111 0x10
00347 #define AR5K_SREV_RAD_5111A 0x15
00348 #define AR5K_SREV_RAD_2111 0x20
00349 #define AR5K_SREV_RAD_5112 0x30
00350 #define AR5K_SREV_RAD_5112A 0x35
00351 #define AR5K_SREV_RAD_5112B 0x36
00352 #define AR5K_SREV_RAD_2112 0x40
00353 #define AR5K_SREV_RAD_2112A 0x45
00354 #define AR5K_SREV_RAD_2112B 0x46
00355 #define AR5K_SREV_RAD_2413 0x50
00356 #define AR5K_SREV_RAD_5413 0x60
00357 #define AR5K_SREV_RAD_2316 0x70
00358 #define AR5K_SREV_RAD_2317 0x80
00359 #define AR5K_SREV_RAD_5424 0xa0
00360 #define AR5K_SREV_RAD_2425 0xa2
00361 #define AR5K_SREV_RAD_5133 0xc0
00362
00363 #define AR5K_SREV_PHY_5211 0x30
00364 #define AR5K_SREV_PHY_5212 0x41
00365 #define AR5K_SREV_PHY_5212A 0x42
00366 #define AR5K_SREV_PHY_5212B 0x43
00367 #define AR5K_SREV_PHY_2413 0x45
00368 #define AR5K_SREV_PHY_5413 0x61
00369 #define AR5K_SREV_PHY_2425 0x70
00370
00371
00372 #define IEEE80211_MAX_LEN 2500
00373
00374
00375
00376
00377
00378
00379
00380
00381
00382
00383
00384
00385
00386
00387
00388
00389
00390
00391
00392 #define MODULATION_XR 0x00000200
00393
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00429
00430
00431 #define MODULATION_TURBO 0x00000080
00432
00433 enum ath5k_driver_mode {
00434 AR5K_MODE_11A = 0,
00435 AR5K_MODE_11A_TURBO = 1,
00436 AR5K_MODE_11B = 2,
00437 AR5K_MODE_11G = 3,
00438 AR5K_MODE_11G_TURBO = 4,
00439 AR5K_MODE_XR = 0,
00440 AR5K_MODE_MAX = 5
00441 };
00442
00443
00444
00445
00446
00447
00448
00449
00450
00451 struct ath5k_tx_status {
00452 u16 ts_seqnum;
00453 u16 ts_tstamp;
00454 u8 ts_status;
00455 u8 ts_rate[4];
00456 u8 ts_retry[4];
00457 u8 ts_final_idx;
00458 s8 ts_rssi;
00459 u8 ts_shortretry;
00460 u8 ts_longretry;
00461 u8 ts_virtcol;
00462 u8 ts_antenna;
00463 };
00464
00465 #define AR5K_TXSTAT_ALTRATE 0x80
00466 #define AR5K_TXERR_XRETRY 0x01
00467 #define AR5K_TXERR_FILT 0x02
00468 #define AR5K_TXERR_FIFO 0x04
00469
00479 enum ath5k_tx_queue {
00480 AR5K_TX_QUEUE_INACTIVE = 0,
00481 AR5K_TX_QUEUE_DATA,
00482 AR5K_TX_QUEUE_XR_DATA,
00483 AR5K_TX_QUEUE_BEACON,
00484 AR5K_TX_QUEUE_CAB,
00485 AR5K_TX_QUEUE_UAPSD,
00486 };
00487
00488 #define AR5K_NUM_TX_QUEUES 10
00489 #define AR5K_NUM_TX_QUEUES_NOQCU 2
00490
00491
00492
00493
00494
00495
00496
00497
00498 enum ath5k_tx_queue_subtype {
00499 AR5K_WME_AC_BK = 0,
00500 AR5K_WME_AC_BE,
00501 AR5K_WME_AC_VI,
00502 AR5K_WME_AC_VO,
00503 };
00504
00505
00506
00507
00508
00509
00510
00511 enum ath5k_tx_queue_id {
00512 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,
00513 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1,
00514 AR5K_TX_QUEUE_ID_DATA_MIN = 0,
00515 AR5K_TX_QUEUE_ID_DATA_MAX = 4,
00516 AR5K_TX_QUEUE_ID_DATA_SVP = 5,
00517 AR5K_TX_QUEUE_ID_CAB = 6,
00518 AR5K_TX_QUEUE_ID_BEACON = 7,
00519 AR5K_TX_QUEUE_ID_UAPSD = 8,
00520 AR5K_TX_QUEUE_ID_XR_DATA = 9,
00521 };
00522
00523
00524
00525
00526 #define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001
00527 #define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002
00528 #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004
00529 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008
00530 #define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010
00531 #define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020
00532 #define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040
00533 #define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080
00534 #define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100
00535 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200
00536 #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300
00537 #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800
00538 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000
00539 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000
00540
00541
00542
00543
00544 struct ath5k_txq_info {
00545 enum ath5k_tx_queue tqi_type;
00546 enum ath5k_tx_queue_subtype tqi_subtype;
00547 u16 tqi_flags;
00548 u32 tqi_aifs;
00549 s32 tqi_cw_min;
00550 s32 tqi_cw_max;
00551 u32 tqi_cbr_period;
00552 u32 tqi_cbr_overflow_limit;
00553 u32 tqi_burst_time;
00554 u32 tqi_ready_time;
00555 };
00556
00557
00558
00559
00560
00561
00562 enum ath5k_pkt_type {
00563 AR5K_PKT_TYPE_NORMAL = 0,
00564 AR5K_PKT_TYPE_ATIM = 1,
00565 AR5K_PKT_TYPE_PSPOLL = 2,
00566 AR5K_PKT_TYPE_BEACON = 3,
00567 AR5K_PKT_TYPE_PROBE_RESP = 4,
00568 AR5K_PKT_TYPE_PIFS = 5,
00569 };
00570
00571
00572
00573
00574 #define AR5K_TXPOWER_OFDM(_r, _v) ( \
00575 ((0 & 1) << ((_v) + 6)) | \
00576 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
00577 )
00578
00579 #define AR5K_TXPOWER_CCK(_r, _v) ( \
00580 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
00581 )
00582
00583
00584
00585
00586 enum ath5k_dmasize {
00587 AR5K_DMASIZE_4B = 0,
00588 AR5K_DMASIZE_8B,
00589 AR5K_DMASIZE_16B,
00590 AR5K_DMASIZE_32B,
00591 AR5K_DMASIZE_64B,
00592 AR5K_DMASIZE_128B,
00593 AR5K_DMASIZE_256B,
00594 AR5K_DMASIZE_512B
00595 };
00596
00597
00598
00599
00600
00601
00602
00603
00604
00605 struct ath5k_rx_status {
00606 u16 rs_datalen;
00607 u16 rs_tstamp;
00608 u8 rs_status;
00609 u8 rs_phyerr;
00610 s8 rs_rssi;
00611 u8 rs_keyix;
00612 u8 rs_rate;
00613 u8 rs_antenna;
00614 u8 rs_more;
00615 };
00616
00617 #define AR5K_RXERR_CRC 0x01
00618 #define AR5K_RXERR_PHY 0x02
00619 #define AR5K_RXERR_FIFO 0x04
00620 #define AR5K_RXERR_DECRYPT 0x08
00621 #define AR5K_RXERR_MIC 0x10
00622 #define AR5K_RXKEYIX_INVALID ((u8) - 1)
00623 #define AR5K_TXKEYIX_INVALID ((u32) - 1)
00624
00625
00626
00627
00628
00629
00630 #define AR5K_BEACON_PERIOD 0x0000ffff
00631 #define AR5K_BEACON_ENA 0x00800000
00632 #define AR5K_BEACON_RESET_TSF 0x01000000
00633
00634 #if 0
00635
00641 struct ath5k_beacon_state {
00642 u32 bs_next_beacon;
00643 u32 bs_next_dtim;
00644 u32 bs_interval;
00645 u8 bs_dtim_period;
00646 u8 bs_cfp_period;
00647 u16 bs_cfp_max_duration;
00648 u16 bs_cfp_du_remain;
00649 u16 bs_tim_offset;
00650 u16 bs_sleep_duration;
00651 u16 bs_bmiss_threshold;
00652 u32 bs_cfp_next;
00653 };
00654 #endif
00655
00656
00657
00658
00659
00660
00661
00662
00663
00664 #define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
00665
00666
00667
00668
00669
00670
00671 enum ath5k_rfgain {
00672 AR5K_RFGAIN_INACTIVE = 0,
00673 AR5K_RFGAIN_ACTIVE,
00674 AR5K_RFGAIN_READ_REQUESTED,
00675 AR5K_RFGAIN_NEED_CHANGE,
00676 };
00677
00678 struct ath5k_gain {
00679 u8 g_step_idx;
00680 u8 g_current;
00681 u8 g_target;
00682 u8 g_low;
00683 u8 g_high;
00684 u8 g_f_corr;
00685 u8 g_state;
00686 };
00687
00688
00689
00690
00691
00692 #define AR5K_SLOT_TIME_9 396
00693 #define AR5K_SLOT_TIME_20 880
00694 #define AR5K_SLOT_TIME_MAX 0xffff
00695
00696
00697 #define CHANNEL_CW_INT 0x0008
00698 #define CHANNEL_TURBO 0x0010
00699 #define CHANNEL_CCK 0x0020
00700 #define CHANNEL_OFDM 0x0040
00701 #define CHANNEL_2GHZ 0x0080
00702 #define CHANNEL_5GHZ 0x0100
00703 #define CHANNEL_PASSIVE 0x0200
00704 #define CHANNEL_DYN 0x0400
00705 #define CHANNEL_XR 0x0800
00706
00707 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
00708 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
00709 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
00710 #define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
00711 #define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
00712 #define CHANNEL_108A CHANNEL_T
00713 #define CHANNEL_108G CHANNEL_TG
00714 #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
00715
00716 #define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
00717 CHANNEL_TURBO)
00718
00719 #define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO)
00720 #define CHANNEL_MODES CHANNEL_ALL
00721
00722
00723
00724
00725
00726 #define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0)
00727 #define IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0)
00728
00729
00730
00731
00732
00733
00734 struct ath5k_athchan_2ghz {
00735 u32 a2_flags;
00736 u16 a2_athchan;
00737 };
00738
00739
00740
00741
00742
00743
00772 #define AR5K_MAX_RATES 32
00773
00774
00775 #define ATH5K_RATE_CODE_1M 0x1B
00776 #define ATH5K_RATE_CODE_2M 0x1A
00777 #define ATH5K_RATE_CODE_5_5M 0x19
00778 #define ATH5K_RATE_CODE_11M 0x18
00779
00780 #define ATH5K_RATE_CODE_6M 0x0B
00781 #define ATH5K_RATE_CODE_9M 0x0F
00782 #define ATH5K_RATE_CODE_12M 0x0A
00783 #define ATH5K_RATE_CODE_18M 0x0E
00784 #define ATH5K_RATE_CODE_24M 0x09
00785 #define ATH5K_RATE_CODE_36M 0x0D
00786 #define ATH5K_RATE_CODE_48M 0x08
00787 #define ATH5K_RATE_CODE_54M 0x0C
00788
00789 #define ATH5K_RATE_CODE_XR_500K 0x07
00790 #define ATH5K_RATE_CODE_XR_1M 0x02
00791 #define ATH5K_RATE_CODE_XR_2M 0x06
00792 #define ATH5K_RATE_CODE_XR_3M 0x01
00793
00794
00795 #define AR5K_SET_SHORT_PREAMBLE 0x04
00796
00797
00798
00799
00800
00801 #define AR5K_KEYCACHE_SIZE 8
00802
00803
00804
00805
00806
00807
00808
00809
00810 #define AR5K_RSSI_EP_MULTIPLIER (1<<7)
00811
00812 #define AR5K_ASSERT_ENTRY(_e, _s) do { \
00813 if (_e >= _s) \
00814 return (false); \
00815 } while (0)
00816
00817
00818
00819
00820
00873 enum ath5k_int {
00874 AR5K_INT_RXOK = 0x00000001,
00875 AR5K_INT_RXDESC = 0x00000002,
00876 AR5K_INT_RXERR = 0x00000004,
00877 AR5K_INT_RXNOFRM = 0x00000008,
00878 AR5K_INT_RXEOL = 0x00000010,
00879 AR5K_INT_RXORN = 0x00000020,
00880 AR5K_INT_TXOK = 0x00000040,
00881 AR5K_INT_TXDESC = 0x00000080,
00882 AR5K_INT_TXERR = 0x00000100,
00883 AR5K_INT_TXNOFRM = 0x00000200,
00884 AR5K_INT_TXEOL = 0x00000400,
00885 AR5K_INT_TXURN = 0x00000800,
00886 AR5K_INT_MIB = 0x00001000,
00887 AR5K_INT_SWI = 0x00002000,
00888 AR5K_INT_RXPHY = 0x00004000,
00889 AR5K_INT_RXKCM = 0x00008000,
00890 AR5K_INT_SWBA = 0x00010000,
00891 AR5K_INT_BRSSI = 0x00020000,
00892 AR5K_INT_BMISS = 0x00040000,
00893 AR5K_INT_FATAL = 0x00080000,
00894 AR5K_INT_BNR = 0x00100000,
00895 AR5K_INT_TIM = 0x00200000,
00896 AR5K_INT_DTIM = 0x00400000,
00897 AR5K_INT_DTIM_SYNC = 0x00800000,
00898 AR5K_INT_GPIO = 0x01000000,
00899 AR5K_INT_BCN_TIMEOUT = 0x02000000,
00900 AR5K_INT_CAB_TIMEOUT = 0x04000000,
00901 AR5K_INT_RX_DOPPLER = 0x08000000,
00902 AR5K_INT_QCBRORN = 0x10000000,
00903 AR5K_INT_QCBRURN = 0x20000000,
00904 AR5K_INT_QTRIG = 0x40000000,
00905 AR5K_INT_GLOBAL = 0x80000000,
00906
00907 AR5K_INT_COMMON = AR5K_INT_RXOK
00908 | AR5K_INT_RXDESC
00909 | AR5K_INT_RXERR
00910 | AR5K_INT_RXNOFRM
00911 | AR5K_INT_RXEOL
00912 | AR5K_INT_RXORN
00913 | AR5K_INT_TXOK
00914 | AR5K_INT_TXDESC
00915 | AR5K_INT_TXERR
00916 | AR5K_INT_TXNOFRM
00917 | AR5K_INT_TXEOL
00918 | AR5K_INT_TXURN
00919 | AR5K_INT_MIB
00920 | AR5K_INT_SWI
00921 | AR5K_INT_RXPHY
00922 | AR5K_INT_RXKCM
00923 | AR5K_INT_SWBA
00924 | AR5K_INT_BRSSI
00925 | AR5K_INT_BMISS
00926 | AR5K_INT_GPIO
00927 | AR5K_INT_GLOBAL,
00928
00929 AR5K_INT_NOCARD = 0xffffffff
00930 };
00931
00932
00933 enum ath5k_software_interrupt {
00934 AR5K_SWI_FULL_CALIBRATION = 0x01,
00935 AR5K_SWI_SHORT_CALIBRATION = 0x02,
00936 };
00937
00938
00939
00940
00941 enum ath5k_power_mode {
00942 AR5K_PM_UNDEFINED = 0,
00943 AR5K_PM_AUTO,
00944 AR5K_PM_AWAKE,
00945 AR5K_PM_FULL_SLEEP,
00946 AR5K_PM_NETWORK_SLEEP,
00947 };
00948
00949
00950
00951
00952
00953
00954 #define AR5K_LED_INIT 0
00955 #define AR5K_LED_SCAN 1
00956 #define AR5K_LED_AUTH 2
00957 #define AR5K_LED_ASSOC 3
00958 #define AR5K_LED_RUN 4
00959
00960
00961 #define AR5K_SOFTLED_PIN 0
00962 #define AR5K_SOFTLED_ON 0
00963 #define AR5K_SOFTLED_OFF 1
00964
00965
00966
00967
00968
00969
00970
00971 enum ath5k_capability_type {
00972 AR5K_CAP_REG_DMN = 0,
00973 AR5K_CAP_TKIP_MIC = 2,
00974 AR5K_CAP_TKIP_SPLIT = 3,
00975 AR5K_CAP_PHYCOUNTERS = 4,
00976 AR5K_CAP_DIVERSITY = 5,
00977 AR5K_CAP_NUM_TXQUEUES = 6,
00978 AR5K_CAP_VEOL = 7,
00979 AR5K_CAP_COMPRESSION = 8,
00980 AR5K_CAP_BURST = 9,
00981 AR5K_CAP_FASTFRAME = 10,
00982 AR5K_CAP_TXPOW = 11,
00983 AR5K_CAP_TPC = 12,
00984 AR5K_CAP_BSSIDMASK = 13,
00985 AR5K_CAP_MCAST_KEYSRCH = 14,
00986 AR5K_CAP_TSF_ADJUST = 15,
00987 AR5K_CAP_XR = 16,
00988 AR5K_CAP_WME_TKIPMIC = 17,
00989 AR5K_CAP_CHAN_HALFRATE = 18,
00990 AR5K_CAP_CHAN_QUARTERRATE = 19,
00991 AR5K_CAP_RFSILENT = 20,
00992 };
00993
00994
00995
00996 struct ath5k_capabilities {
00997
00998
00999
01000
01001 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
01002
01003
01004
01005
01006 struct {
01007 u16 range_2ghz_min;
01008 u16 range_2ghz_max;
01009 u16 range_5ghz_min;
01010 u16 range_5ghz_max;
01011 } cap_range;
01012
01013
01014
01015
01016 struct ath5k_eeprom_info cap_eeprom;
01017
01018
01019
01020
01021 struct {
01022 u8 q_tx_num;
01023 } cap_queues;
01024 };
01025
01026
01027
01028
01029
01030
01031
01032
01033
01034
01035 #define AR5K_MAX_GPIO 10
01036 #define AR5K_MAX_RF_BANKS 8
01037
01038
01039 struct ath5k_hw {
01040 u32 ah_magic;
01041
01042 struct ath5k_softc *ah_sc;
01043 void __iomem *ah_iobase;
01044
01045 enum ath5k_int ah_imr;
01046
01047 struct ieee80211_channel *ah_current_channel;
01048 bool ah_turbo;
01049 bool ah_calibration;
01050 bool ah_single_chip;
01051 bool ah_combined_mic;
01052
01053 enum ath5k_version ah_version;
01054 enum ath5k_radio ah_radio;
01055 u32 ah_phy;
01056 u32 ah_mac_srev;
01057 u16 ah_mac_version;
01058 u16 ah_mac_revision;
01059 u16 ah_phy_revision;
01060 u16 ah_radio_5ghz_revision;
01061 u16 ah_radio_2ghz_revision;
01062
01063 #define ah_modes ah_capabilities.cap_mode
01064 #define ah_ee_version ah_capabilities.cap_eeprom.ee_version
01065
01066 u32 ah_atim_window;
01067 u32 ah_aifs;
01068 u32 ah_cw_min;
01069 u32 ah_cw_max;
01070 u32 ah_limit_tx_retries;
01071
01072
01073 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
01074 u8 ah_ant_mode;
01075 u8 ah_tx_ant;
01076 u8 ah_def_ant;
01077 bool ah_software_retry;
01078
01079 u8 ah_sta_id[ETH_ALEN];
01080
01081
01082
01083
01084 u8 ah_bssid[ETH_ALEN];
01085 u8 ah_bssid_mask[ETH_ALEN];
01086
01087
01088 struct ath5k_capabilities ah_capabilities;
01089
01090 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];
01091 u32 ah_txq_status;
01092 u32 ah_txq_imr_txok;
01093 u32 ah_txq_imr_txerr;
01094 u32 ah_txq_imr_txurn;
01095 u32 ah_txq_imr_txdesc;
01096 u32 ah_txq_imr_txeol;
01097 u32 ah_txq_imr_cbrorn;
01098 u32 ah_txq_imr_cbrurn;
01099 u32 ah_txq_imr_qtrig;
01100 u32 ah_txq_imr_nofrm;
01101 u32 ah_txq_isr;
01102 u32 *ah_rf_banks;
01103 size_t ah_rf_banks_size;
01104 size_t ah_rf_regs_count;
01105 struct ath5k_gain ah_gain;
01106 u8 ah_offset[AR5K_MAX_RF_BANKS];
01107
01108
01109 struct {
01110
01111 u8 tmpL[AR5K_EEPROM_N_PD_GAINS]
01112 [AR5K_EEPROM_POWER_TABLE_SIZE];
01113 u8 tmpR[AR5K_EEPROM_N_PD_GAINS]
01114 [AR5K_EEPROM_POWER_TABLE_SIZE];
01115 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2];
01116 u16 txp_rates_power_table[AR5K_MAX_RATES];
01117 u8 txp_min_idx;
01118 bool txp_tpc;
01119
01120 s16 txp_min_pwr;
01121 s16 txp_max_pwr;
01122
01123 s16 txp_offset;
01124 s16 txp_ofdm;
01125 s16 txp_cck_ofdm_gainf_delta;
01126
01127 s16 txp_cck_ofdm_pwr_delta;
01128 } ah_txpower;
01129
01130 struct {
01131 bool r_enabled;
01132 int r_last_alert;
01133 struct ieee80211_channel r_last_channel;
01134 } ah_radar;
01135
01136
01137 s32 ah_noise_floor;
01138
01139
01140 struct timespec ah_cal_tstamp;
01141
01142
01143 struct timespec ah_cal_intval;
01144
01145
01146 u8 ah_swi_mask;
01147
01148
01149
01150
01151 int (*ah_setup_rx_desc)(struct ath5k_hw *ah, struct ath5k_desc *desc,
01152 u32 size, unsigned int flags);
01153 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
01154 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
01155 unsigned int, unsigned int, unsigned int, unsigned int,
01156 unsigned int, unsigned int, unsigned int);
01157 int (*ah_setup_mrr_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
01158 unsigned int, unsigned int, unsigned int, unsigned int,
01159 unsigned int, unsigned int);
01160 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
01161 struct ath5k_tx_status *);
01162 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
01163 struct ath5k_rx_status *);
01164 };
01165
01166
01167
01168
01169
01170
01171 extern int ath5k_hw_attach(struct ath5k_softc *sc);
01172 extern void ath5k_hw_detach(struct ath5k_hw *ah);
01173
01174
01175 extern int ath5k_init_leds(struct ath5k_softc *sc);
01176 extern void ath5k_led_enable(struct ath5k_softc *sc);
01177 extern void ath5k_led_off(struct ath5k_softc *sc);
01178 extern void ath5k_unregister_leds(struct ath5k_softc *sc);
01179
01180
01181 extern int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial);
01182 extern int ath5k_hw_on_hold(struct ath5k_hw *ah);
01183 extern int ath5k_hw_reset(struct ath5k_hw *ah, struct ieee80211_channel *channel, bool change_channel);
01184
01185 extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration);
01186
01187
01188 extern void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
01189 extern int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
01190 extern u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
01191 extern void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
01192 extern int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
01193 extern int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
01194 extern u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
01195 extern int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
01196 u32 phys_addr);
01197 extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
01198
01199 extern bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
01200 extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
01201 extern enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum
01202 ath5k_int new_mask);
01203 extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ieee80211_low_level_stats *stats);
01204
01205
01206 extern int ath5k_eeprom_init(struct ath5k_hw *ah);
01207 extern void ath5k_eeprom_detach(struct ath5k_hw *ah);
01208 extern int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
01209 extern bool ath5k_eeprom_is_hb63(struct ath5k_hw *ah);
01210
01211
01212 extern int ath5k_hw_set_opmode(struct ath5k_hw *ah);
01213
01214 extern void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac);
01215 extern int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
01216 extern void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id);
01217 extern int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
01218
01219 extern void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
01220 extern void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
01221
01222 extern void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
01223 extern int ath5k_hw_set_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
01224 extern int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
01225 extern u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
01226 extern void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
01227
01228 extern u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah);
01229 extern u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
01230 extern void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
01231 extern void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
01232 extern void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
01233
01234 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
01235
01236 extern int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout);
01237 extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah);
01238 extern int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout);
01239 extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah);
01240
01241
01242 extern int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, struct ath5k_txq_info *queue_info);
01243 extern int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
01244 const struct ath5k_txq_info *queue_info);
01245 extern int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
01246 enum ath5k_tx_queue queue_type,
01247 struct ath5k_txq_info *queue_info);
01248 extern u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
01249 extern void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
01250 extern int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
01251 extern unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah);
01252 extern int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
01253
01254
01255 extern int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
01256
01257
01258 extern void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
01259 extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
01260 extern int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
01261 extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
01262 extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
01263 extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level);
01264
01265
01266 extern void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
01267 extern void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
01268
01269
01270 int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
01271 extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result);
01272 extern int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
01273 extern int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
01274
01275
01276 extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
01277
01278
01279 extern int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
01280 struct ieee80211_channel *channel,
01281 unsigned int mode);
01282 extern int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq);
01283 extern enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
01284 extern int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
01285
01286 extern bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
01287 extern int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel);
01288
01289 extern int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct ieee80211_channel *channel);
01290 extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq);
01291 extern void ath5k_hw_calibration_poll(struct ath5k_hw *ah);
01292
01293 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
01294 struct ieee80211_channel *channel);
01295 void ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
01296 struct ieee80211_channel *channel);
01297
01298 extern u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
01299 extern int ath5k_hw_phy_disable(struct ath5k_hw *ah);
01300
01301 extern void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode);
01302 extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant);
01303 extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah);
01304
01305 extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, u8 ee_mode, u8 txpower);
01306 extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower);
01307
01308
01309
01310
01311
01312
01313
01314
01315
01316 static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
01317 {
01318 return turbo ? (usec * 80) : (usec * 40);
01319 }
01320
01321
01322
01323
01324
01325 static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
01326 {
01327 return turbo ? (clock / 80) : (clock / 40);
01328 }
01329
01330
01331
01332
01333 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
01334 {
01335 return ioread32(ah->ah_iobase + reg);
01336 }
01337
01338
01339
01340
01341 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
01342 {
01343 iowrite32(val, ah->ah_iobase + reg);
01344 }
01345
01346 #if defined(_ATH5K_RESET) || defined(_ATH5K_PHY)
01347
01348
01349
01350 static int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag,
01351 u32 val, bool is_set)
01352 {
01353 int i;
01354 u32 data;
01355
01356 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
01357 data = ath5k_hw_reg_read(ah, reg);
01358 if (is_set && (data & flag))
01359 break;
01360 else if ((data & flag) == val)
01361 break;
01362 udelay(15);
01363 }
01364
01365 return (i <= 0) ? -EAGAIN : 0;
01366 }
01367 #endif
01368
01369 static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
01370 {
01371 u32 retval = 0, bit, i;
01372
01373 for (i = 0; i < bits; i++) {
01374 bit = (val >> i) & 1;
01375 retval = (retval << 1) | bit;
01376 }
01377
01378 return retval;
01379 }
01380
01381 static inline int ath5k_pad_size(int hdrlen)
01382 {
01383 return (hdrlen < 24) ? 0 : hdrlen & 3;
01384 }
01385
01386 #endif