LPC214x.h
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00001 /******************************************************************************
00002  *   LPC214X.h:  Header file for Philips LPC214x Family Microprocessors
00003  *   The header file is the super set of all hardware definition of the 
00004  *   peripherals for the LPC214x family microprocessor.
00005  *
00006  *   Copyright(C) 2006, Philips Semiconductor
00007  *   All rights reserved.
00008 
00009  *   History
00010  *   2005.10.01  ver 1.00    Prelimnary version, first Release
00011  *   2005.10.13  ver 1.01    Removed CSPR and DC_REVISION register.
00012  *                           CSPR can not be accessed at the user level,
00013  *                           DC_REVISION is no long available.
00014  *                           All registers use "volatile unsigned long". 
00015 ******************************************************************************/
00016 
00017 #ifndef __LPC214x_H
00018 #define __LPC214x_H
00019 
00020 /* Vectored Interrupt Controller (VIC) */
00021 #define VIC_BASE_ADDR   0xFFFFF000
00022 
00023 #define VICIRQStatus   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000))
00024 #define VICFIQStatus   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004))
00025 #define VICRawIntr     (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008))
00026 #define VICIntSelect   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x00C))
00027 #define VICIntEnable   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x010))
00028 #define VICIntEnClr    (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x014))
00029 #define VICSoftInt     (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x018))
00030 #define VICSoftIntClr  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x01C))
00031 #define VICProtection  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x020))
00032 #define VICVectAddr    (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x030))
00033 #define VICDefVectAddr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x034))
00034 #define VICVectAddr0   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x100))
00035 #define VICVectAddr1   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x104))
00036 #define VICVectAddr2   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x108))
00037 #define VICVectAddr3   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x10C))
00038 #define VICVectAddr4   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x110))
00039 #define VICVectAddr5   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x114))
00040 #define VICVectAddr6   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x118))
00041 #define VICVectAddr7   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x11C))
00042 #define VICVectAddr8   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x120))
00043 #define VICVectAddr9   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x124))
00044 #define VICVectAddr10  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x128))
00045 #define VICVectAddr11  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x12C))
00046 #define VICVectAddr12  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x130))
00047 #define VICVectAddr13  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x134))
00048 #define VICVectAddr14  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x138))
00049 #define VICVectAddr15  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x13C))
00050 #define VICVectCntl0   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x200))
00051 #define VICVectCntl1   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x204))
00052 #define VICVectCntl2   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x208))
00053 #define VICVectCntl3   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x20C))
00054 #define VICVectCntl4   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x210))
00055 #define VICVectCntl5   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x214))
00056 #define VICVectCntl6   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x218))
00057 #define VICVectCntl7   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x21C))
00058 #define VICVectCntl8   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x220))
00059 #define VICVectCntl9   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x224))
00060 #define VICVectCntl10  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x228))
00061 #define VICVectCntl11  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x22C))
00062 #define VICVectCntl12  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x230))
00063 #define VICVectCntl13  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x234))
00064 #define VICVectCntl14  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x238))
00065 #define VICVectCntl15  (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x23C))
00066 
00067 /* Pin Connect Block */
00068 #define PINSEL_BASE_ADDR        0xE002C000
00069 #define PINSEL0        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00))
00070 #define PINSEL1        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04))
00071 #define PINSEL2        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x14))
00072 
00073 /* General Purpose Input/Output (GPIO) */
00074 #define GPIO_BASE_ADDR          0xE0028000
00075 #define IOPIN0         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00))
00076 #define IOSET0         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04))
00077 #define IODIR0         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08))
00078 #define IOCLR0         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x0C))
00079 #define IOPIN1         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10))
00080 #define IOSET1         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14))
00081 #define IODIR1         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18))
00082 #define IOCLR1         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C))
00083 
00084 /* Fast I/O setup */
00085 #define FIO_BASE_ADDR           0x3FFFC000
00086 #define FIO0DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) 
00087 #define FIO0MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10))
00088 #define FIO0PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14))
00089 #define FIO0SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18))
00090 #define FIO0CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C))
00091 #define FIO1DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20)) 
00092 #define FIO1MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30))
00093 #define FIO1PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34))
00094 #define FIO1SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38))
00095 #define FIO1CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C))
00096 
00097 /* System Control Block(SCB) modules include Memory Accelerator Module,
00098 Phase Locked Loop, VPB divider, Power Control, External Interrupt, 
00099 Reset, and Code Security/Debugging */
00100 
00101 #define SCB_BASE_ADDR   0xE01FC000
00102 
00103 /* Memory Accelerator Module (MAM) */
00104 #define MAMCR          (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000))
00105 #define MAMTIM         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x004))
00106 #define MEMMAP         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x040))
00107 
00108 /* Phase Locked Loop (PLL) */
00109 #define PLLCON         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x080))
00110 #define PLLCFG         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x084))
00111 #define PLLSTAT        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x088))
00112 #define PLLFEED        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x08C))
00113 
00114 /* PLL48 Registers */
00115 #define PLL48CON       (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A0))
00116 #define PLL48CFG       (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A4))
00117 #define PLL48STAT      (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A8))
00118 #define PLL48FEED      (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0AC))
00119 
00120 /* Power Control */
00121 #define PCON           (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C0))
00122 #define PCONP          (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C4))
00123 
00124 /* VPB Divider */
00125 #define VPBDIV         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x100))
00126 
00127 /* External Interrupts */
00128 #define EXTINT         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140))
00129 #define INTWAKE        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144))
00130 #define EXTMODE        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x148))
00131 #define EXTPOLAR       (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x14C))
00132 
00133 /* Reset */
00134 #define RSIR           (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180))
00135 
00136 /* System Controls and Status */
00137 #define SCS            (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0))     
00138 
00139 /* Timer 0 */
00140 #define TMR0_BASE_ADDR          0xE0004000
00141 #define T0IR           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00))
00142 #define T0TCR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04))
00143 #define T0TC           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08))
00144 #define T0PR           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C))
00145 #define T0PC           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10))
00146 #define T0MCR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14))
00147 #define T0MR0          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18))
00148 #define T0MR1          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C))
00149 #define T0MR2          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20))
00150 #define T0MR3          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24))
00151 #define T0CCR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28))
00152 #define T0CR0          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C))
00153 #define T0CR1          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30))
00154 #define T0CR2          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x34))
00155 #define T0CR3          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x38))
00156 #define T0EMR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C))
00157 #define T0CTCR         (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70))
00158 
00159 /* Timer 1 */
00160 #define TMR1_BASE_ADDR          0xE0008000
00161 #define T1IR           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00))
00162 #define T1TCR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04))
00163 #define T1TC           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08))
00164 #define T1PR           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C))
00165 #define T1PC           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10))
00166 #define T1MCR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14))
00167 #define T1MR0          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18))
00168 #define T1MR1          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C))
00169 #define T1MR2          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20))
00170 #define T1MR3          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24))
00171 #define T1CCR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28))
00172 #define T1CR0          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C))
00173 #define T1CR1          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x30))
00174 #define T1CR2          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x34))
00175 #define T1CR3          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x38))
00176 #define T1EMR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x3C))
00177 #define T1CTCR         (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70))
00178 
00179 /* Pulse Width Modulator (PWM) */
00180 #define PWM_BASE_ADDR           0xE0014000
00181 #define PWMIR          (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x00))
00182 #define PWMTCR         (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x04))
00183 #define PWMTC          (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x08))
00184 #define PWMPR          (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x0C))
00185 #define PWMPC          (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x10))
00186 #define PWMMCR         (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x14))
00187 #define PWMMR0         (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x18))
00188 #define PWMMR1         (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x1C))
00189 #define PWMMR2         (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x20))
00190 #define PWMMR3         (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x24))
00191 #define PWMMR4         (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x40))
00192 #define PWMMR5         (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x44))
00193 #define PWMMR6         (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x48))
00194 #define PWMEMR         (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x3C))
00195 #define PWMPCR         (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x4C))
00196 #define PWMLER         (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x50))
00197 
00198 /* Universal Asynchronous Receiver Transmitter 0 (UART0) */
00199 #define UART0_BASE_ADDR         0xE000C000
00200 #define U0RBR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
00201 #define U0THR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
00202 #define U0DLL          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
00203 #define U0DLM          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))
00204 #define U0IER          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))
00205 #define U0IIR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))
00206 #define U0FCR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))
00207 #define U0LCR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x0C))
00208 #define U0MCR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x10))
00209 #define U0LSR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x14))
00210 #define U0MSR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x18))
00211 #define U0SCR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x1C))
00212 #define U0ACR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x20))
00213 #define U0FDR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x28))
00214 #define U0TER          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30))
00215 
00216 /* Universal Asynchronous Receiver Transmitter 1 (UART1) */
00217 #define UART1_BASE_ADDR         0xE0010000
00218 #define U1RBR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
00219 #define U1THR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
00220 #define U1DLL          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
00221 #define U1DLM          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))
00222 #define U1IER          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))
00223 #define U1IIR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))
00224 #define U1FCR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))
00225 #define U1LCR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x0C))
00226 #define U1MCR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x10))
00227 #define U1LSR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x14))
00228 #define U1MSR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x18))
00229 #define U1SCR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x1C))
00230 #define U1ACR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x20))
00231 #define U1FDR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x28))
00232 #define U1TER          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30))
00233 
00234 /* I2C Interface 0 */
00235 #define I2C0_BASE_ADDR          0xE001C000
00236 #define I20CONSET      (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00))
00237 #define I20STAT        (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04))
00238 #define I20DAT         (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08))
00239 #define I20ADR         (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x0C))
00240 #define I20SCLH        (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x10))
00241 #define I20SCLL        (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x14))
00242 #define I20CONCLR      (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18))
00243 
00244 /* I2C Interface 1 */
00245 #define I2C1_BASE_ADDR          0xE005C000
00246 #define I21CONSET      (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00))
00247 #define I21STAT        (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04))
00248 #define I21DAT         (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08))
00249 #define I21ADR         (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x0C))
00250 #define I21SCLH        (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x10))
00251 #define I21SCLL        (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x14))
00252 #define I21CONCLR      (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18))
00253 
00254 /* SPI0 (Serial Peripheral Interface 0) */
00255 #define SPI0_BASE_ADDR          0xE0020000
00256 #define S0SPCR         (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00))
00257 #define S0SPSR         (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04))
00258 #define S0SPDR         (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08))
00259 #define S0SPCCR        (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x0C))
00260 #define S0SPINT        (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C))
00261 
00262 /* SSP Controller */
00263 #define SSP_BASE_ADDR           0xE0068000
00264 #define SSPCR0         (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x00))
00265 #define SSPCR1         (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x04))
00266 #define SSPDR          (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x08))
00267 #define SSPSR          (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x0C))
00268 #define SSPCPSR        (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x10))
00269 #define SSPIMSC        (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x14))
00270 #define SSPRIS         (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x18))
00271 #define SSPMIS         (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x1C))
00272 #define SSPICR         (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x20))
00273 
00274 /* Real Time Clock */
00275 #define RTC_BASE_ADDR           0xE0024000
00276 #define ILR            (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00))
00277 #define CTC            (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04))
00278 #define CCR            (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08))
00279 #define CIIR           (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x0C))
00280 #define AMR            (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x10))
00281 #define CTIME0         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x14))
00282 #define CTIME1         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x18))
00283 #define CTIME2         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x1C))
00284 #define SEC            (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x20))
00285 #define MIN            (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x24))
00286 #define HOUR           (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x28))
00287 #define DOM            (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x2C))
00288 #define DOW            (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x30))
00289 #define DOY            (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x34))
00290 #define MONTH          (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x38))
00291 #define YEAR           (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x3C))
00292 #define ALSEC          (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x60))
00293 #define ALMIN          (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x64))
00294 #define ALHOUR         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x68))
00295 #define ALDOM          (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x6C))
00296 #define ALDOW          (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x70))
00297 #define ALDOY          (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x74))
00298 #define ALMON          (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x78))
00299 #define ALYEAR         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x7C))
00300 #define PREINT         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x80))
00301 #define PREFRAC        (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x84))
00302 
00303 /* A/D Converter 0 (AD0) */
00304 #define AD0_BASE_ADDR           0xE0034000
00305 #define AD0CR          (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00))
00306 #define AD0GDR         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04))
00307 #define AD0STAT        (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x30))
00308 #define AD0INTEN       (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C))
00309 #define AD0DR0         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x10))
00310 #define AD0DR1         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x14))
00311 #define AD0DR2         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x18))
00312 #define AD0DR3         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x1C))
00313 #define AD0DR4         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x20))
00314 #define AD0DR5         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x24))
00315 #define AD0DR6         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x28))
00316 #define AD0DR7         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x2C))
00317 
00318 #define ADGSR          (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x08))
00319 /* A/D Converter 1 (AD1) */
00320 #define AD1_BASE_ADDR           0xE0060000
00321 #define AD1CR          (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x00))
00322 #define AD1GDR         (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x04))
00323 #define AD1STAT        (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x30))
00324 #define AD1INTEN       (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x0C))
00325 #define AD1DR0         (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x10))
00326 #define AD1DR1         (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x14))
00327 #define AD1DR2         (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x18))
00328 #define AD1DR3         (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x1C))
00329 #define AD1DR4         (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x20))
00330 #define AD1DR5         (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x24))
00331 #define AD1DR6         (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x28))
00332 #define AD1DR7         (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x2C))
00333 
00334 /* D/A Converter */
00335 #define DAC_BASE_ADDR           0xE006C000
00336 #define DACR           (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00))
00337 
00338 /* Watchdog */
00339 #define WDG_BASE_ADDR           0xE0000000
00340 #define WDMOD          (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00))
00341 #define WDTC           (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04))
00342 #define WDFEED         (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08))
00343 #define WDTV           (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x0C))
00344 
00345 /* USB Controller */
00346 #define USB_BASE_ADDR           0xE0090000                      /* USB Base Address */
00347 /* Device Interrupt Registers */
00348 #define DEV_INT_STAT    (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00))
00349 #define DEV_INT_EN      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04))
00350 #define DEV_INT_CLR     (*(volatile unsigned long *)(USB_BASE_ADDR + 0x08))
00351 #define DEV_INT_SET     (*(volatile unsigned long *)(USB_BASE_ADDR + 0x0C))
00352 #define DEV_INT_PRIO    (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C))
00353 
00354 /* Endpoint Interrupt Registers */
00355 #define EP_INT_STAT     (*(volatile unsigned long *)(USB_BASE_ADDR + 0x30))
00356 #define EP_INT_EN       (*(volatile unsigned long *)(USB_BASE_ADDR + 0x34))
00357 #define EP_INT_CLR      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x38))
00358 #define EP_INT_SET      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x3C))
00359 #define EP_INT_PRIO     (*(volatile unsigned long *)(USB_BASE_ADDR + 0x40))
00360 
00361 /* Endpoint Realization Registers */
00362 #define REALIZE_EP      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x44))
00363 #define EP_INDEX        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x48))
00364 #define MAXPACKET_SIZE  (*(volatile unsigned long *)(USB_BASE_ADDR + 0x4C))
00365 
00366 /* Command Reagisters */
00367 #define CMD_CODE        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x10))
00368 #define CMD_DATA        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x14))
00369 
00370 /* Data Transfer Registers */
00371 #define RX_DATA         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x18))
00372 #define TX_DATA         (*(volatile unsigned long *)(USB_BASE_ADDR + 0x1C))
00373 #define RX_PLENGTH      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x20))
00374 #define TX_PLENGTH      (*(volatile unsigned long *)(USB_BASE_ADDR + 0x24))
00375 #define USB_CTRL        (*(volatile unsigned long *)(USB_BASE_ADDR + 0x28))
00376 
00377 /* DMA Registers */
00378 #define DMA_REQ_STAT        (*((volatile unsigned long *)USB_BASE_ADDR + 0x50))
00379 #define DMA_REQ_CLR         (*((volatile unsigned long *)USB_BASE_ADDR + 0x54))
00380 #define DMA_REQ_SET         (*((volatile unsigned long *)USB_BASE_ADDR + 0x58))
00381 #define UDCA_HEAD           (*((volatile unsigned long *)USB_BASE_ADDR + 0x80))
00382 #define EP_DMA_STAT         (*((volatile unsigned long *)USB_BASE_ADDR + 0x84))
00383 #define EP_DMA_EN           (*((volatile unsigned long *)USB_BASE_ADDR + 0x88))
00384 #define EP_DMA_DIS          (*((volatile unsigned long *)USB_BASE_ADDR + 0x8C))
00385 #define DMA_INT_STAT        (*((volatile unsigned long *)USB_BASE_ADDR + 0x90))
00386 #define DMA_INT_EN          (*((volatile unsigned long *)USB_BASE_ADDR + 0x94))
00387 #define EOT_INT_STAT        (*((volatile unsigned long *)USB_BASE_ADDR + 0xA0))
00388 #define EOT_INT_CLR         (*((volatile unsigned long *)USB_BASE_ADDR + 0xA4))
00389 #define EOT_INT_SET         (*((volatile unsigned long *)USB_BASE_ADDR + 0xA8))
00390 #define NDD_REQ_INT_STAT    (*((volatile unsigned long *)USB_BASE_ADDR + 0xAC))
00391 #define NDD_REQ_INT_CLR     (*((volatile unsigned long *)USB_BASE_ADDR + 0xB0))
00392 #define NDD_REQ_INT_SET     (*((volatile unsigned long *)USB_BASE_ADDR + 0xB4))
00393 #define SYS_ERR_INT_STAT    (*((volatile unsigned long *)USB_BASE_ADDR + 0xB8))
00394 #define SYS_ERR_INT_CLR     (*((volatile unsigned long *)USB_BASE_ADDR + 0xBC))
00395 #define SYS_ERR_INT_SET     (*((volatile unsigned long *)USB_BASE_ADDR + 0xC0))    
00396 #define MODULE_ID           (*((volatile unsigned long *)USB_BASE_ADDR + 0xFC))
00397 
00398 #endif  // __LPC214x_H
00399

ccny_asctec_firmware
Author(s): Ivan Dryanovski, Roberto G. Valenti
autogenerated on Tue Jan 7 2014 11:04:32