vl53l1_nvm_map.h
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1 /*
2 * Copyright (c) 2017, STMicroelectronics - All Rights Reserved
3 *
4 * This file is part of VL53L1 Core and is dual licensed,
5 * either 'STMicroelectronics
6 * Proprietary license'
7 * or 'BSD 3-clause "New" or "Revised" License' , at your option.
8 *
9 ********************************************************************************
10 *
11 * 'STMicroelectronics Proprietary license'
12 *
13 ********************************************************************************
14 *
15 * License terms: STMicroelectronics Proprietary in accordance with licensing
16 * terms at www.st.com/sla0081
17 *
18 * STMicroelectronics confidential
19 * Reproduction and Communication of this document is strictly prohibited unless
20 * specifically authorized in writing by STMicroelectronics.
21 *
22 *
23 ********************************************************************************
24 *
25 * Alternatively, VL53L1 Core may be distributed under the terms of
26 * 'BSD 3-clause "New" or "Revised" License', in which case the following
27 * provisions apply instead of the ones mentioned above :
28 *
29 ********************************************************************************
30 *
31 * License terms: BSD 3-clause "New" or "Revised" License.
32 *
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34 * modification, are permitted provided that the following conditions are met:
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62 
69 /*
70  * Include platform specific and register map definitions
71  */
72 
73 
74 #ifndef _VL53L1_NVM_MAP_H_
75 #define _VL53L1_NVM_MAP_H_
76 
77 
78 #ifdef __cplusplus
79 extern "C"
80 {
81 #endif
82 
83 
88 #define VL53L1_NVM__IDENTIFICATION__MODEL_ID 0x0008
89 
103 #define VL53L1_NVM__IDENTIFICATION__MODULE_TYPE 0x000C
104 
118 #define VL53L1_NVM__IDENTIFICATION__REVISION_ID 0x000D
119 
133 #define VL53L1_NVM__IDENTIFICATION__MODULE_ID 0x000E
134 
148 #define VL53L1_NVM__I2C_VALID 0x0010
149 
163 #define VL53L1_NVM__I2C_SLAVE__DEVICE_ADDRESS 0x0011
164 
178 #define VL53L1_NVM__EWS__OSC_MEASURED__FAST_OSC_FREQUENCY 0x0014
179 
193 #define VL53L1_NVM__EWS__FAST_OSC_TRIM_MAX 0x0016
194 
208 #define VL53L1_NVM__EWS__FAST_OSC_FREQ_SET 0x0017
209 
223 #define VL53L1_NVM__EWS__SLOW_OSC_CALIBRATION 0x0018
224 
238 #define VL53L1_NVM__FMT__OSC_MEASURED__FAST_OSC_FREQUENCY 0x001C
239 
253 #define VL53L1_NVM__FMT__FAST_OSC_TRIM_MAX 0x001E
254 
268 #define VL53L1_NVM__FMT__FAST_OSC_FREQ_SET 0x001F
269 
283 #define VL53L1_NVM__FMT__SLOW_OSC_CALIBRATION 0x0020
284 
298 #define VL53L1_NVM__VHV_CONFIG_UNLOCK 0x0028
299 
313 #define VL53L1_NVM__REF_SELVDDPIX 0x0029
314 
328 #define VL53L1_NVM__REF_SELVQUENCH 0x002A
329 
343 #define VL53L1_NVM__REGAVDD1V2_SEL_REGDVDD1V2_SEL 0x002B
344 
359 #define VL53L1_NVM__VHV_CONFIG__TIMEOUT_MACROP_LOOP_BOUND 0x002C
360 
375 #define VL53L1_NVM__VHV_CONFIG__COUNT_THRESH 0x002D
376 
390 #define VL53L1_NVM__VHV_CONFIG__OFFSET 0x002E
391 
405 #define VL53L1_NVM__VHV_CONFIG__INIT 0x002F
406 
421 #define VL53L1_NVM__LASER_SAFETY__VCSEL_TRIM_LL 0x0030
422 
436 #define VL53L1_NVM__LASER_SAFETY__VCSEL_SELION_LL 0x0031
437 
451 #define VL53L1_NVM__LASER_SAFETY__VCSEL_SELION_MAX_LL 0x0032
452 
466 #define VL53L1_NVM__LASER_SAFETY__MULT_LL 0x0034
467 
481 #define VL53L1_NVM__LASER_SAFETY__CLIP_LL 0x0035
482 
496 #define VL53L1_NVM__LASER_SAFETY__VCSEL_TRIM_LD 0x0038
497 
511 #define VL53L1_NVM__LASER_SAFETY__VCSEL_SELION_LD 0x0039
512 
526 #define VL53L1_NVM__LASER_SAFETY__VCSEL_SELION_MAX_LD 0x003A
527 
541 #define VL53L1_NVM__LASER_SAFETY__MULT_LD 0x003C
542 
556 #define VL53L1_NVM__LASER_SAFETY__CLIP_LD 0x003D
557 
571 #define VL53L1_NVM__LASER_SAFETY_LOCK_BYTE 0x0040
572 
586 #define VL53L1_NVM__LASER_SAFETY_UNLOCK_BYTE 0x0044
587 
601 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_0_ 0x0048
602 
616 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_1_ 0x0049
617 
631 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_2_ 0x004A
632 
646 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_3_ 0x004B
647 
661 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_4_ 0x004C
662 
676 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_5_ 0x004D
677 
691 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_6_ 0x004E
692 
706 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_7_ 0x004F
707 
721 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_8_ 0x0050
722 
736 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_9_ 0x0051
737 
751 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_10_ 0x0052
752 
766 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_11_ 0x0053
767 
781 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_12_ 0x0054
782 
796 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_13_ 0x0055
797 
811 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_14_ 0x0056
812 
826 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_15_ 0x0057
827 
841 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_16_ 0x0058
842 
856 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_17_ 0x0059
857 
871 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_18_ 0x005A
872 
886 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_19_ 0x005B
887 
901 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_20_ 0x005C
902 
916 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_21_ 0x005D
917 
931 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_22_ 0x005E
932 
946 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_23_ 0x005F
947 
961 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_24_ 0x0060
962 
976 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_25_ 0x0061
977 
991 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_26_ 0x0062
992 
1006 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_27_ 0x0063
1007 
1021 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_28_ 0x0064
1022 
1036 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_29_ 0x0065
1037 
1051 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_30_ 0x0066
1052 
1066 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_31_ 0x0067
1067 
1081 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC1_0_ 0x0068
1082 
1096 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC1_1_ 0x0069
1097 
1111 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC1_2_ 0x006A
1112 
1126 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC1_3_ 0x006B
1127 
1141 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC1_4_ 0x006C
1142 
1156 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC1_5_ 0x006D
1157 
1171 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC2_0_ 0x0070
1172 
1186 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC2_1_ 0x0071
1187 
1201 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC2_2_ 0x0072
1202 
1216 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC2_3_ 0x0073
1217 
1231 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC2_4_ 0x0074
1232 
1246 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC2_5_ 0x0075
1247 
1261 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC3_0_ 0x0078
1262 
1276 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC3_1_ 0x0079
1277 
1291 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC3_2_ 0x007A
1292 
1306 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC3_3_ 0x007B
1307 
1321 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC3_4_ 0x007C
1322 
1336 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC3_5_ 0x007D
1337 
1351 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_0_ 0x0080
1352 
1366 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_1_ 0x0081
1367 
1381 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_2_ 0x0082
1382 
1396 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_3_ 0x0083
1397 
1411 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_4_ 0x0084
1412 
1426 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_5_ 0x0085
1427 
1441 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_6_ 0x0086
1442 
1456 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_7_ 0x0087
1457 
1471 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_8_ 0x0088
1472 
1486 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_9_ 0x0089
1487 
1501 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_10_ 0x008A
1502 
1516 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_11_ 0x008B
1517 
1531 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_12_ 0x008C
1532 
1546 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_13_ 0x008D
1547 
1561 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_14_ 0x008E
1562 
1576 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_15_ 0x008F
1577 
1591 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_16_ 0x0090
1592 
1606 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_17_ 0x0091
1607 
1621 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_18_ 0x0092
1622 
1636 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_19_ 0x0093
1637 
1651 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_20_ 0x0094
1652 
1666 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_21_ 0x0095
1667 
1681 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_22_ 0x0096
1682 
1696 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_23_ 0x0097
1697 
1711 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_24_ 0x0098
1712 
1726 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_25_ 0x0099
1727 
1741 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_26_ 0x009A
1742 
1756 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_27_ 0x009B
1757 
1771 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_28_ 0x009C
1772 
1786 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_29_ 0x009D
1787 
1801 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_30_ 0x009E
1802 
1816 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_31_ 0x009F
1817 
1831 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC1_0_ 0x00A0
1832 
1846 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC1_1_ 0x00A1
1847 
1861 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC1_2_ 0x00A2
1862 
1876 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC1_3_ 0x00A3
1877 
1891 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC1_4_ 0x00A4
1892 
1906 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC1_5_ 0x00A5
1907 
1921 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC2_0_ 0x00A8
1922 
1936 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC2_1_ 0x00A9
1937 
1951 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC2_2_ 0x00AA
1952 
1966 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC2_3_ 0x00AB
1967 
1981 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC2_4_ 0x00AC
1982 
1996 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC2_5_ 0x00AD
1997 
2011 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC3_0_ 0x00B0
2012 
2026 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC3_1_ 0x00B1
2027 
2041 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC3_2_ 0x00B2
2042 
2056 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC3_3_ 0x00B3
2057 
2071 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC3_4_ 0x00B4
2072 
2086 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC3_5_ 0x00B5
2087 
2101 #define VL53L1_NVM__FMT__ROI_CONFIG__MODE_ROI_CENTRE_SPAD 0x00B8
2102 
2116 #define VL53L1_NVM__FMT__ROI_CONFIG__MODE_ROI_XY_SIZE 0x00B9
2117 
2132 #define VL53L1_NVM__FMT__REF_SPAD_APPLY__NUM_REQUESTED_REF_SPAD 0x00BC
2133 
2147 #define VL53L1_NVM__FMT__REF_SPAD_MAN__REF_LOCATION 0x00BD
2148 
2162 #define VL53L1_NVM__FMT__MM_CONFIG__INNER_OFFSET_MM 0x00C0
2163 
2177 #define VL53L1_NVM__FMT__MM_CONFIG__OUTER_OFFSET_MM 0x00C2
2178 
2192 #define VL53L1_NVM__FMT__ALGO__PART_TO_PART_RANGE_OFFSET_MM 0x00C4
2193 
2207 #define VL53L1_NVM__FMT__ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS 0x00C8
2208 
2222 #define VL53L1_NVM__FMT__ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS 0x00CA
2223 
2237 #define VL53L1_NVM__FMT__ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS 0x00CC
2238 
2252 #define VL53L1_NVM__FMT__SPARE_HOST_CONFIG__NVM_CONFIG_SPARE_0 0x00CE
2253 
2267 #define VL53L1_NVM__FMT__SPARE_HOST_CONFIG__NVM_CONFIG_SPARE_1 0x00CF
2268 
2282 #define VL53L1_NVM__CUSTOMER_NVM_SPACE_PROGRAMMED 0x00E0
2283 
2297 #define VL53L1_NVM__CUST__I2C_SLAVE__DEVICE_ADDRESS 0x00E4
2298 
2312 #define VL53L1_NVM__CUST__REF_SPAD_APPLY__NUM_REQUESTED_REF_SPAD 0x00E8
2313 
2327 #define VL53L1_NVM__CUST__REF_SPAD_MAN__REF_LOCATION 0x00E9
2328 
2342 #define VL53L1_NVM__CUST__MM_CONFIG__INNER_OFFSET_MM 0x00EC
2343 
2357 #define VL53L1_NVM__CUST__MM_CONFIG__OUTER_OFFSET_MM 0x00EE
2358 
2372 #define VL53L1_NVM__CUST__ALGO__PART_TO_PART_RANGE_OFFSET_MM 0x00F0
2373 
2387 #define VL53L1_NVM__CUST__ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS 0x00F4
2388 
2402 #define VL53L1_NVM__CUST__ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS 0x00F6
2403 
2417 #define VL53L1_NVM__CUST__ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS 0x00F8
2418 
2432 #define VL53L1_NVM__CUST__SPARE_HOST_CONFIG__NVM_CONFIG_SPARE_0 0x00FA
2433 
2447 #define VL53L1_NVM__CUST__SPARE_HOST_CONFIG__NVM_CONFIG_SPARE_1 0x00FB
2448 
2462 #define VL53L1_NVM__FMT__FGC__BYTE_0 0x01DC
2463 
2477 #define VL53L1_NVM__FMT__FGC__BYTE_1 0x01DD
2478 
2492 #define VL53L1_NVM__FMT__FGC__BYTE_2 0x01DE
2493 
2507 #define VL53L1_NVM__FMT__FGC__BYTE_3 0x01DF
2508 
2522 #define VL53L1_NVM__FMT__FGC__BYTE_4 0x01E0
2523 
2537 #define VL53L1_NVM__FMT__FGC__BYTE_5 0x01E1
2538 
2552 #define VL53L1_NVM__FMT__FGC__BYTE_6 0x01E2
2553 
2568 #define VL53L1_NVM__FMT__FGC__BYTE_7 0x01E3
2569 
2583 #define VL53L1_NVM__FMT__FGC__BYTE_8 0x01E4
2584 
2598 #define VL53L1_NVM__FMT__FGC__BYTE_9 0x01E5
2599 
2613 #define VL53L1_NVM__FMT__FGC__BYTE_10 0x01E6
2614 
2628 #define VL53L1_NVM__FMT__FGC__BYTE_11 0x01E7
2629 
2643 #define VL53L1_NVM__FMT__FGC__BYTE_12 0x01E8
2644 
2658 #define VL53L1_NVM__FMT__FGC__BYTE_13 0x01E9
2659 
2674 #define VL53L1_NVM__FMT__FGC__BYTE_14 0x01EA
2675 
2689 #define VL53L1_NVM__FMT__FGC__BYTE_15 0x01EB
2690 
2704 #define VL53L1_NVM__FMT__TEST_PROGRAM_MAJOR_MINOR 0x01EC
2705 
2720 #define VL53L1_NVM__FMT__MAP_MAJOR_MINOR 0x01ED
2721 
2736 #define VL53L1_NVM__FMT__YEAR_MONTH 0x01EE
2737 
2752 #define VL53L1_NVM__FMT__DAY_MODULE_DATE_PHASE 0x01EF
2753 
2768 #define VL53L1_NVM__FMT__TIME 0x01F0
2769 
2783 #define VL53L1_NVM__FMT__TESTER_ID 0x01F2
2784 
2798 #define VL53L1_NVM__FMT__SITE_ID 0x01F3
2799 
2813 #define VL53L1_NVM__EWS__TEST_PROGRAM_MAJOR_MINOR 0x01F4
2814 
2829 #define VL53L1_NVM__EWS__PROBE_CARD_MAJOR_MINOR 0x01F5
2830 
2845 #define VL53L1_NVM__EWS__TESTER_ID 0x01F6
2846 
2860 #define VL53L1_NVM__EWS__LOT__BYTE_0 0x01F8
2861 
2875 #define VL53L1_NVM__EWS__LOT__BYTE_1 0x01F9
2876 
2890 #define VL53L1_NVM__EWS__LOT__BYTE_2 0x01FA
2891 
2906 #define VL53L1_NVM__EWS__LOT__BYTE_3 0x01FB
2907 
2921 #define VL53L1_NVM__EWS__LOT__BYTE_4 0x01FC
2922 
2936 #define VL53L1_NVM__EWS__LOT__BYTE_5 0x01FD
2937 
2951 #define VL53L1_NVM__EWS__WAFER 0x01FD
2952 
2966 #define VL53L1_NVM__EWS__XCOORD 0x01FE
2967 
2981 #define VL53L1_NVM__EWS__YCOORD 0x01FF
2982 
2997 #define VL53L1_NVM__FMT__OPTICAL_CENTRE_DATA_INDEX 0x00B8
2998 #define VL53L1_NVM__FMT__OPTICAL_CENTRE_DATA_SIZE 4
2999 
3000 #define VL53L1_NVM__FMT__CAL_PEAK_RATE_MAP_DATA_INDEX 0x015C
3001 #define VL53L1_NVM__FMT__CAL_PEAK_RATE_MAP_DATA_SIZE 56
3002 
3003 #define VL53L1_NVM__FMT__ADDITIONAL_OFFSET_CAL_DATA_INDEX 0x0194
3004 #define VL53L1_NVM__FMT__ADDITIONAL_OFFSET_CAL_DATA_SIZE 8
3005 
3006 #define VL53L1_NVM__FMT__RANGE_RESULTS__140MM_MM_PRE_RANGE 0x019C
3007 #define VL53L1_NVM__FMT__RANGE_RESULTS__140MM_DARK 0x01AC
3008 #define VL53L1_NVM__FMT__RANGE_RESULTS__400MM_DARK 0x01BC
3009 #define VL53L1_NVM__FMT__RANGE_RESULTS__400MM_AMBIENT 0x01CC
3010 #define VL53L1_NVM__FMT__RANGE_RESULTS__SIZE_BYTES 16
3011 
3018 #ifdef __cplusplus
3019 }
3020 #endif
3021 
3022 #endif


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autogenerated on Fri Aug 2 2024 08:35:54