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74 #ifndef _VL53L1_NVM_MAP_H_
75 #define _VL53L1_NVM_MAP_H_
88 #define VL53L1_NVM__IDENTIFICATION__MODEL_ID 0x0008
103 #define VL53L1_NVM__IDENTIFICATION__MODULE_TYPE 0x000C
118 #define VL53L1_NVM__IDENTIFICATION__REVISION_ID 0x000D
133 #define VL53L1_NVM__IDENTIFICATION__MODULE_ID 0x000E
148 #define VL53L1_NVM__I2C_VALID 0x0010
163 #define VL53L1_NVM__I2C_SLAVE__DEVICE_ADDRESS 0x0011
178 #define VL53L1_NVM__EWS__OSC_MEASURED__FAST_OSC_FREQUENCY 0x0014
193 #define VL53L1_NVM__EWS__FAST_OSC_TRIM_MAX 0x0016
208 #define VL53L1_NVM__EWS__FAST_OSC_FREQ_SET 0x0017
223 #define VL53L1_NVM__EWS__SLOW_OSC_CALIBRATION 0x0018
238 #define VL53L1_NVM__FMT__OSC_MEASURED__FAST_OSC_FREQUENCY 0x001C
253 #define VL53L1_NVM__FMT__FAST_OSC_TRIM_MAX 0x001E
268 #define VL53L1_NVM__FMT__FAST_OSC_FREQ_SET 0x001F
283 #define VL53L1_NVM__FMT__SLOW_OSC_CALIBRATION 0x0020
298 #define VL53L1_NVM__VHV_CONFIG_UNLOCK 0x0028
313 #define VL53L1_NVM__REF_SELVDDPIX 0x0029
328 #define VL53L1_NVM__REF_SELVQUENCH 0x002A
343 #define VL53L1_NVM__REGAVDD1V2_SEL_REGDVDD1V2_SEL 0x002B
359 #define VL53L1_NVM__VHV_CONFIG__TIMEOUT_MACROP_LOOP_BOUND 0x002C
375 #define VL53L1_NVM__VHV_CONFIG__COUNT_THRESH 0x002D
390 #define VL53L1_NVM__VHV_CONFIG__OFFSET 0x002E
405 #define VL53L1_NVM__VHV_CONFIG__INIT 0x002F
421 #define VL53L1_NVM__LASER_SAFETY__VCSEL_TRIM_LL 0x0030
436 #define VL53L1_NVM__LASER_SAFETY__VCSEL_SELION_LL 0x0031
451 #define VL53L1_NVM__LASER_SAFETY__VCSEL_SELION_MAX_LL 0x0032
466 #define VL53L1_NVM__LASER_SAFETY__MULT_LL 0x0034
481 #define VL53L1_NVM__LASER_SAFETY__CLIP_LL 0x0035
496 #define VL53L1_NVM__LASER_SAFETY__VCSEL_TRIM_LD 0x0038
511 #define VL53L1_NVM__LASER_SAFETY__VCSEL_SELION_LD 0x0039
526 #define VL53L1_NVM__LASER_SAFETY__VCSEL_SELION_MAX_LD 0x003A
541 #define VL53L1_NVM__LASER_SAFETY__MULT_LD 0x003C
556 #define VL53L1_NVM__LASER_SAFETY__CLIP_LD 0x003D
571 #define VL53L1_NVM__LASER_SAFETY_LOCK_BYTE 0x0040
586 #define VL53L1_NVM__LASER_SAFETY_UNLOCK_BYTE 0x0044
601 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_0_ 0x0048
616 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_1_ 0x0049
631 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_2_ 0x004A
646 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_3_ 0x004B
661 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_4_ 0x004C
676 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_5_ 0x004D
691 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_6_ 0x004E
706 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_7_ 0x004F
721 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_8_ 0x0050
736 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_9_ 0x0051
751 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_10_ 0x0052
766 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_11_ 0x0053
781 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_12_ 0x0054
796 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_13_ 0x0055
811 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_14_ 0x0056
826 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_15_ 0x0057
841 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_16_ 0x0058
856 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_17_ 0x0059
871 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_18_ 0x005A
886 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_19_ 0x005B
901 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_20_ 0x005C
916 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_21_ 0x005D
931 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_22_ 0x005E
946 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_23_ 0x005F
961 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_24_ 0x0060
976 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_25_ 0x0061
991 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_26_ 0x0062
1006 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_27_ 0x0063
1021 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_28_ 0x0064
1036 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_29_ 0x0065
1051 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_30_ 0x0066
1066 #define VL53L1_NVM__EWS__SPAD_ENABLES_RTN_31_ 0x0067
1081 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC1_0_ 0x0068
1096 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC1_1_ 0x0069
1111 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC1_2_ 0x006A
1126 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC1_3_ 0x006B
1141 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC1_4_ 0x006C
1156 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC1_5_ 0x006D
1171 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC2_0_ 0x0070
1186 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC2_1_ 0x0071
1201 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC2_2_ 0x0072
1216 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC2_3_ 0x0073
1231 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC2_4_ 0x0074
1246 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC2_5_ 0x0075
1261 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC3_0_ 0x0078
1276 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC3_1_ 0x0079
1291 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC3_2_ 0x007A
1306 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC3_3_ 0x007B
1321 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC3_4_ 0x007C
1336 #define VL53L1_NVM__EWS__SPAD_ENABLES_REF__LOC3_5_ 0x007D
1351 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_0_ 0x0080
1366 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_1_ 0x0081
1381 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_2_ 0x0082
1396 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_3_ 0x0083
1411 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_4_ 0x0084
1426 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_5_ 0x0085
1441 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_6_ 0x0086
1456 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_7_ 0x0087
1471 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_8_ 0x0088
1486 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_9_ 0x0089
1501 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_10_ 0x008A
1516 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_11_ 0x008B
1531 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_12_ 0x008C
1546 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_13_ 0x008D
1561 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_14_ 0x008E
1576 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_15_ 0x008F
1591 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_16_ 0x0090
1606 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_17_ 0x0091
1621 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_18_ 0x0092
1636 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_19_ 0x0093
1651 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_20_ 0x0094
1666 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_21_ 0x0095
1681 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_22_ 0x0096
1696 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_23_ 0x0097
1711 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_24_ 0x0098
1726 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_25_ 0x0099
1741 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_26_ 0x009A
1756 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_27_ 0x009B
1771 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_28_ 0x009C
1786 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_29_ 0x009D
1801 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_30_ 0x009E
1816 #define VL53L1_NVM__FMT__SPAD_ENABLES_RTN_31_ 0x009F
1831 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC1_0_ 0x00A0
1846 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC1_1_ 0x00A1
1861 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC1_2_ 0x00A2
1876 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC1_3_ 0x00A3
1891 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC1_4_ 0x00A4
1906 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC1_5_ 0x00A5
1921 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC2_0_ 0x00A8
1936 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC2_1_ 0x00A9
1951 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC2_2_ 0x00AA
1966 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC2_3_ 0x00AB
1981 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC2_4_ 0x00AC
1996 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC2_5_ 0x00AD
2011 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC3_0_ 0x00B0
2026 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC3_1_ 0x00B1
2041 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC3_2_ 0x00B2
2056 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC3_3_ 0x00B3
2071 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC3_4_ 0x00B4
2086 #define VL53L1_NVM__FMT__SPAD_ENABLES_REF__LOC3_5_ 0x00B5
2101 #define VL53L1_NVM__FMT__ROI_CONFIG__MODE_ROI_CENTRE_SPAD 0x00B8
2116 #define VL53L1_NVM__FMT__ROI_CONFIG__MODE_ROI_XY_SIZE 0x00B9
2132 #define VL53L1_NVM__FMT__REF_SPAD_APPLY__NUM_REQUESTED_REF_SPAD 0x00BC
2147 #define VL53L1_NVM__FMT__REF_SPAD_MAN__REF_LOCATION 0x00BD
2162 #define VL53L1_NVM__FMT__MM_CONFIG__INNER_OFFSET_MM 0x00C0
2177 #define VL53L1_NVM__FMT__MM_CONFIG__OUTER_OFFSET_MM 0x00C2
2192 #define VL53L1_NVM__FMT__ALGO__PART_TO_PART_RANGE_OFFSET_MM 0x00C4
2207 #define VL53L1_NVM__FMT__ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS 0x00C8
2222 #define VL53L1_NVM__FMT__ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS 0x00CA
2237 #define VL53L1_NVM__FMT__ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS 0x00CC
2252 #define VL53L1_NVM__FMT__SPARE_HOST_CONFIG__NVM_CONFIG_SPARE_0 0x00CE
2267 #define VL53L1_NVM__FMT__SPARE_HOST_CONFIG__NVM_CONFIG_SPARE_1 0x00CF
2282 #define VL53L1_NVM__CUSTOMER_NVM_SPACE_PROGRAMMED 0x00E0
2297 #define VL53L1_NVM__CUST__I2C_SLAVE__DEVICE_ADDRESS 0x00E4
2312 #define VL53L1_NVM__CUST__REF_SPAD_APPLY__NUM_REQUESTED_REF_SPAD 0x00E8
2327 #define VL53L1_NVM__CUST__REF_SPAD_MAN__REF_LOCATION 0x00E9
2342 #define VL53L1_NVM__CUST__MM_CONFIG__INNER_OFFSET_MM 0x00EC
2357 #define VL53L1_NVM__CUST__MM_CONFIG__OUTER_OFFSET_MM 0x00EE
2372 #define VL53L1_NVM__CUST__ALGO__PART_TO_PART_RANGE_OFFSET_MM 0x00F0
2387 #define VL53L1_NVM__CUST__ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS 0x00F4
2402 #define VL53L1_NVM__CUST__ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS 0x00F6
2417 #define VL53L1_NVM__CUST__ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS 0x00F8
2432 #define VL53L1_NVM__CUST__SPARE_HOST_CONFIG__NVM_CONFIG_SPARE_0 0x00FA
2447 #define VL53L1_NVM__CUST__SPARE_HOST_CONFIG__NVM_CONFIG_SPARE_1 0x00FB
2462 #define VL53L1_NVM__FMT__FGC__BYTE_0 0x01DC
2477 #define VL53L1_NVM__FMT__FGC__BYTE_1 0x01DD
2492 #define VL53L1_NVM__FMT__FGC__BYTE_2 0x01DE
2507 #define VL53L1_NVM__FMT__FGC__BYTE_3 0x01DF
2522 #define VL53L1_NVM__FMT__FGC__BYTE_4 0x01E0
2537 #define VL53L1_NVM__FMT__FGC__BYTE_5 0x01E1
2552 #define VL53L1_NVM__FMT__FGC__BYTE_6 0x01E2
2568 #define VL53L1_NVM__FMT__FGC__BYTE_7 0x01E3
2583 #define VL53L1_NVM__FMT__FGC__BYTE_8 0x01E4
2598 #define VL53L1_NVM__FMT__FGC__BYTE_9 0x01E5
2613 #define VL53L1_NVM__FMT__FGC__BYTE_10 0x01E6
2628 #define VL53L1_NVM__FMT__FGC__BYTE_11 0x01E7
2643 #define VL53L1_NVM__FMT__FGC__BYTE_12 0x01E8
2658 #define VL53L1_NVM__FMT__FGC__BYTE_13 0x01E9
2674 #define VL53L1_NVM__FMT__FGC__BYTE_14 0x01EA
2689 #define VL53L1_NVM__FMT__FGC__BYTE_15 0x01EB
2704 #define VL53L1_NVM__FMT__TEST_PROGRAM_MAJOR_MINOR 0x01EC
2720 #define VL53L1_NVM__FMT__MAP_MAJOR_MINOR 0x01ED
2736 #define VL53L1_NVM__FMT__YEAR_MONTH 0x01EE
2752 #define VL53L1_NVM__FMT__DAY_MODULE_DATE_PHASE 0x01EF
2768 #define VL53L1_NVM__FMT__TIME 0x01F0
2783 #define VL53L1_NVM__FMT__TESTER_ID 0x01F2
2798 #define VL53L1_NVM__FMT__SITE_ID 0x01F3
2813 #define VL53L1_NVM__EWS__TEST_PROGRAM_MAJOR_MINOR 0x01F4
2829 #define VL53L1_NVM__EWS__PROBE_CARD_MAJOR_MINOR 0x01F5
2845 #define VL53L1_NVM__EWS__TESTER_ID 0x01F6
2860 #define VL53L1_NVM__EWS__LOT__BYTE_0 0x01F8
2875 #define VL53L1_NVM__EWS__LOT__BYTE_1 0x01F9
2890 #define VL53L1_NVM__EWS__LOT__BYTE_2 0x01FA
2906 #define VL53L1_NVM__EWS__LOT__BYTE_3 0x01FB
2921 #define VL53L1_NVM__EWS__LOT__BYTE_4 0x01FC
2936 #define VL53L1_NVM__EWS__LOT__BYTE_5 0x01FD
2951 #define VL53L1_NVM__EWS__WAFER 0x01FD
2966 #define VL53L1_NVM__EWS__XCOORD 0x01FE
2981 #define VL53L1_NVM__EWS__YCOORD 0x01FF
2997 #define VL53L1_NVM__FMT__OPTICAL_CENTRE_DATA_INDEX 0x00B8
2998 #define VL53L1_NVM__FMT__OPTICAL_CENTRE_DATA_SIZE 4
3000 #define VL53L1_NVM__FMT__CAL_PEAK_RATE_MAP_DATA_INDEX 0x015C
3001 #define VL53L1_NVM__FMT__CAL_PEAK_RATE_MAP_DATA_SIZE 56
3003 #define VL53L1_NVM__FMT__ADDITIONAL_OFFSET_CAL_DATA_INDEX 0x0194
3004 #define VL53L1_NVM__FMT__ADDITIONAL_OFFSET_CAL_DATA_SIZE 8
3006 #define VL53L1_NVM__FMT__RANGE_RESULTS__140MM_MM_PRE_RANGE 0x019C
3007 #define VL53L1_NVM__FMT__RANGE_RESULTS__140MM_DARK 0x01AC
3008 #define VL53L1_NVM__FMT__RANGE_RESULTS__400MM_DARK 0x01BC
3009 #define VL53L1_NVM__FMT__RANGE_RESULTS__400MM_AMBIENT 0x01CC
3010 #define VL53L1_NVM__FMT__RANGE_RESULTS__SIZE_BYTES 16
vl53l1x
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autogenerated on Fri Aug 2 2024 08:35:54