core_cmInstr.h
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1 /**************************************************************************/
24 #ifndef __CORE_CMINSTR_H
25 #define __CORE_CMINSTR_H
26 
27 
28 /* ########################## Core Instruction Access ######################### */
34 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
35 /* ARM armcc specific functions */
36 
37 #if (__ARMCC_VERSION < 400677)
38  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
39 #endif
40 
41 
46 #define __NOP __nop
47 
48 
54 #define __WFI __wfi
55 
56 
62 #define __WFE __wfe
63 
64 
69 #define __SEV __sev
70 
71 
78 #define __ISB() __isb(0xF)
79 
80 
86 #define __DSB() __dsb(0xF)
87 
88 
94 #define __DMB() __dmb(0xF)
95 
96 
104 #define __REV __rev
105 
106 
114 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
115 {
116  rev16 r0, r0
117  bx lr
118 }
119 
120 
128 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
129 {
130  revsh r0, r0
131  bx lr
132 }
133 
134 
143 #define __ROR __ror
144 
145 
146 #if (__CORTEX_M >= 0x03)
147 
155 #define __RBIT __rbit
156 
157 
165 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
166 
167 
175 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
176 
177 
185 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
186 
187 
197 #define __STREXB(value, ptr) __strex(value, ptr)
198 
199 
209 #define __STREXH(value, ptr) __strex(value, ptr)
210 
211 
221 #define __STREXW(value, ptr) __strex(value, ptr)
222 
223 
229 #define __CLREX __clrex
230 
231 
240 #define __SSAT __ssat
241 
242 
251 #define __USAT __usat
252 
253 
261 #define __CLZ __clz
262 
263 #endif /* (__CORTEX_M >= 0x03) */
264 
265 
266 
267 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
268 /* IAR iccarm specific functions */
269 
270 #include <cmsis_iar.h>
271 
272 
273 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
274 /* TI CCS specific functions */
275 
276 #include <cmsis_ccs.h>
277 
278 
279 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
280 /* GNU gcc specific functions */
281 
286 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
287 {
288  __ASM volatile ("nop");
289 }
290 
291 
297 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
298 {
299  __ASM volatile ("wfi");
300 }
301 
302 
308 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
309 {
310  __ASM volatile ("wfe");
311 }
312 
313 
318 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
319 {
320  __ASM volatile ("sev");
321 }
322 
323 
330 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
331 {
332  __ASM volatile ("isb");
333 }
334 
335 
341 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
342 {
343  __ASM volatile ("dsb");
344 }
345 
346 
352 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
353 {
354  __ASM volatile ("dmb");
355 }
356 
357 
365 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
366 {
367  uint32_t result;
368 
369  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
370  return(result);
371 }
372 
373 
381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
382 {
383  uint32_t result;
384 
385  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
386  return(result);
387 }
388 
389 
397 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
398 {
399  uint32_t result;
400 
401  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
402  return(result);
403 }
404 
405 
414 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
415 {
416 
417  __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
418  return(op1);
419 }
420 
421 
422 #if (__CORTEX_M >= 0x03)
423 
431 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
432 {
433  uint32_t result;
434 
435  __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
436  return(result);
437 }
438 
439 
447 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
448 {
449  uint8_t result;
450 
451  __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
452  return(result);
453 }
454 
455 
463 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
464 {
465  uint16_t result;
466 
467  __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
468  return(result);
469 }
470 
471 
479 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
480 {
481  uint32_t result;
482 
483  __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
484  return(result);
485 }
486 
487 
497 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
498 {
499  uint32_t result;
500 
501  __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
502  return(result);
503 }
504 
505 
515 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
516 {
517  uint32_t result;
518 
519  __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
520  return(result);
521 }
522 
523 
533 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
534 {
535  uint32_t result;
536 
537  __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
538  return(result);
539 }
540 
541 
547 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
548 {
549  __ASM volatile ("clrex");
550 }
551 
552 
561 #define __SSAT(ARG1,ARG2) \
562 ({ \
563  uint32_t __RES, __ARG1 = (ARG1); \
564  __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
565  __RES; \
566  })
567 
568 
577 #define __USAT(ARG1,ARG2) \
578 ({ \
579  uint32_t __RES, __ARG1 = (ARG1); \
580  __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
581  __RES; \
582  })
583 
584 
592 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
593 {
594  uint8_t result;
595 
596  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
597  return(result);
598 }
599 
600 #endif /* (__CORTEX_M >= 0x03) */
601 
602 
603 
604 
605 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
606 /* TASKING carm specific functions */
607 
608 /*
609  * The CMSIS functions have been implemented as intrinsics in the compiler.
610  * Please use "carm -?i" to get an up to date list of all intrinsics,
611  * Including the CMSIS ones.
612  */
613 
614 #endif
615  /* end of group CMSIS_Core_InstructionInterface */
617 
618 #endif /* __CORE_CMINSTR_H */
uavcan::uint32_t
std::uint32_t uint32_t
Definition: std.hpp:26
uavcan::uint16_t
std::uint16_t uint16_t
Definition: std.hpp:25
uavcan::int32_t
std::int32_t int32_t
Definition: std.hpp:31
uavcan::uint8_t
std::uint8_t uint8_t
Definition: std.hpp:24
__attribute__
__attribute__((gnu_inline)) inline void spi_start(uint8_t data)
Definition: spi.h:74


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autogenerated on Fri Dec 13 2024 03:10:02