system_MIMXRT1052.h
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1 /*
2 ** ###################################################################
3 ** Processors: MIMXRT1052CVJ5B
4 ** MIMXRT1052CVL5B
5 ** MIMXRT1052DVJ6B
6 ** MIMXRT1052DVL6B
7 **
8 ** Compilers: Freescale C/C++ for Embedded ARM
9 ** GNU C Compiler
10 ** IAR ANSI C/C++ Compiler for ARM
11 ** Keil ARM C/C++ Compiler
12 ** MCUXpresso Compiler
13 **
14 ** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 | IMXRT1050SRM Rev.2
15 ** Version: rev. 1.3, 2019-04-29
16 ** Build: b191113
17 **
18 ** Abstract:
19 ** Provides a system configuration function and a global variable that
20 ** contains the system frequency. It configures the device and initializes
21 ** the oscillator (PLL) that is part of the microcontroller device.
22 **
23 ** Copyright 2016 Freescale Semiconductor, Inc.
24 ** Copyright 2016-2019 NXP
25 ** All rights reserved.
26 **
27 ** SPDX-License-Identifier: BSD-3-Clause
28 **
29 ** http: www.nxp.com
30 ** mail: support@nxp.com
31 **
32 ** Revisions:
33 ** - rev. 0.1 (2017-01-10)
34 ** Initial version.
35 ** - rev. 1.0 (2018-09-21)
36 ** Update interrupt vector table and dma request source.
37 ** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
38 ** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
39 ** - rev. 1.1 (2018-11-16)
40 ** Update header files to align with IMXRT1050RM Rev.1.
41 ** - rev. 1.2 (2018-11-27)
42 ** Update header files to align with IMXRT1050RM Rev.2.1.
43 ** - rev. 1.3 (2019-04-29)
44 ** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module.
45 **
46 ** ###################################################################
47 */
48 
60 #ifndef _SYSTEM_MIMXRT1052_H_
61 #define _SYSTEM_MIMXRT1052_H_
63 #ifdef __cplusplus
64 extern "C" {
65 #endif
66 
67 #include <stdint.h>
68 
69 
70 #ifndef DISABLE_WDOG
71  #define DISABLE_WDOG 1
72 #endif
73 
74 /* Define clock source values */
75 
76 #define CPU_XTAL_CLK_HZ 24000000UL /* Value of the external crystal or oscillator clock frequency in Hz */
77 
78 #define CPU_CLK1_HZ 0UL /* Value of the CLK1 (select the CLK1_N/CLK1_P as source) frequency in Hz */
79  /* If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 will be returned. */
80 
81 #define DEFAULT_SYSTEM_CLOCK 528000000UL /* Default System clock value */
82 
83 
93 extern uint32_t SystemCoreClock;
94 
102 void SystemInit (void);
103 
111 void SystemCoreClockUpdate (void);
112 
123 void SystemInitHook (void);
124 
125 #ifdef __cplusplus
126 }
127 #endif
128 
129 #endif /* _SYSTEM_MIMXRT1052_H_ */
SystemInit
void SystemInit(void)
Setup the microcontroller system.
Definition: system_MIMXRT1052.c:75
SystemCoreClock
uint32_t SystemCoreClock
System clock frequency (core clock)
Definition: system_MIMXRT1052.c:69
SystemCoreClockUpdate
void SystemCoreClockUpdate(void)
Updates the SystemCoreClock variable.
Definition: system_MIMXRT1052.c:138
SystemInitHook
void SystemInitHook(void)
SystemInit function hook.

picovoice_driver
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autogenerated on Fri Apr 1 2022 02:14:55