stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_HAL_PWR_H
22 #define STM32H7xx_HAL_PWR_H
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif /* __cplusplus */
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx_hal_def.h"
30 
39 /* Exported types ------------------------------------------------------------*/
40 
48 typedef struct
49 {
50  uint32_t PVDLevel;
55  uint32_t Mode;
59 }PWR_PVDTypeDef;
60 
65 /* Exported constants --------------------------------------------------------*/
73 #define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0
75 #define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1
77 #define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2
79 #define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3
81 #define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4
83 #define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5
85 #define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6
87 #define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7
96 #define PWR_PVD_MODE_NORMAL (0x00000000U)
97 #define PWR_PVD_MODE_IT_RISING (0x00010001U)
98 #define PWR_PVD_MODE_IT_FALLING (0x00010002U)
99 #define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U)
100 #define PWR_PVD_MODE_EVENT_RISING (0x00020001U)
101 #define PWR_PVD_MODE_EVENT_FALLING (0x00020002U)
102 #define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U)
110 #define PWR_MAINREGULATOR_ON (0U)
111 #define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS
112 
119 #define PWR_SLEEPENTRY_WFI (0x01U)
120 #define PWR_SLEEPENTRY_WFE (0x02U)
121 
128 #define PWR_STOPENTRY_WFI (0x01U)
129 #define PWR_STOPENTRY_WFE (0x02U)
130 
137 #if defined(PWR_SRDCR_VOS)
138 #define PWR_REGULATOR_VOLTAGE_SCALE0 (PWR_SRDCR_VOS_1 | PWR_SRDCR_VOS_0)
139 #define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_SRDCR_VOS_1)
140 #define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_SRDCR_VOS_0)
141 #define PWR_REGULATOR_VOLTAGE_SCALE3 (0U)
142 #else
143 #define PWR_REGULATOR_VOLTAGE_SCALE0 (0U)
144 #define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)
145 #define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_D3CR_VOS_1)
146 #define PWR_REGULATOR_VOLTAGE_SCALE3 (PWR_D3CR_VOS_0)
147 #endif /* PWR_SRDCR_VOS */
148 
155 /* PWR CPU flag */
156 #define PWR_FLAG_STOP (0x01U)
157 #if defined (PWR_CPUCR_SBF_D2)
158 #define PWR_FLAG_SB_D1 (0x02U)
159 #define PWR_FLAG_SB_D2 (0x03U)
160 #endif /* defined (PWR_CPUCR_SBF_D2) */
161 #define PWR_FLAG_SB (0x04U)
162 #if defined (DUAL_CORE)
163 #define PWR_FLAG_CPU_HOLD (0x05U)
164 #define PWR_FLAG_CPU2_HOLD (0x06U)
165 #define PWR_FLAG2_STOP (0x07U)
166 #define PWR_FLAG2_SB_D1 (0x08U)
167 #define PWR_FLAG2_SB_D2 (0x09U)
168 #define PWR_FLAG2_SB (0x0AU)
169 #endif /* defined (DUAL_CORE) */
170 #define PWR_FLAG_PVDO (0x0BU)
171 #define PWR_FLAG_AVDO (0x0CU)
172 #define PWR_FLAG_ACTVOSRDY (0x0DU)
173 #define PWR_FLAG_ACTVOS (0x0EU)
174 #define PWR_FLAG_BRR (0x0FU)
175 #define PWR_FLAG_VOSRDY (0x10U)
176 #if defined (SMPS)
177 #define PWR_FLAG_SMPSEXTRDY (0x11U)
178 #else
179 #define PWR_FLAG_SCUEN (0x11U)
180 #endif /* defined (SMPS) */
181 #if defined (PWR_CSR1_MMCVDO)
182 #define PWR_FLAG_MMCVDO (0x12U)
183 #endif /* defined (PWR_CSR1_MMCVDO) */
184 #define PWR_FLAG_USB33RDY (0x13U)
185 #define PWR_FLAG_TEMPH (0x14U)
186 #define PWR_FLAG_TEMPL (0x15U)
187 #define PWR_FLAG_VBATH (0x16U)
188 #define PWR_FLAG_VBATL (0x17U)
189 
190 /* PWR Wake up flag */
191 #define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1
192 #define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2
193 #define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3
194 #define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4
195 #define PWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5
196 #define PWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6
197 
204 #define PWR_EWUP_MASK (0x0FFF3F3FU)
205 
212 /* Exported macro ------------------------------------------------------------*/
248 #if defined (PWR_SRDCR_VOS) /* STM32H7Axxx and STM32H7Bxxx lines */
249 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
250 do { \
251  __IO uint32_t tmpreg = 0x00; \
252  /* Configure the Voltage Scaling */ \
253  MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, (__REGULATOR__)); \
254  /* Delay after setting the voltage scaling */ \
255  tmpreg = READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS); \
256  UNUSED(tmpreg); \
257 } while(0)
258 #else /* 3 power domains devices */
259 #if defined(SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */
260 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
261 do { \
262  __IO uint32_t tmpreg = 0x00; \
263  /* Check the voltage scaling to be configured */ \
264  if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0) \
265  { \
266  /* Configure the Voltage Scaling 1 */ \
267  MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); \
268  /* Delay after setting the voltage scaling */ \
269  tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
270  /* Enable the PWR overdrive */ \
271  SET_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
272  /* Delay after setting the syscfg boost setting */ \
273  tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
274  } \
275  else \
276  { \
277  /* Disable the PWR overdrive */ \
278  CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
279  /* Delay after setting the syscfg boost setting */ \
280  tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
281  /* Configure the Voltage Scaling x */ \
282  MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \
283  /* Delay after setting the voltage scaling */ \
284  tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
285  } \
286  UNUSED(tmpreg); \
287 } while(0)
288 #else /* STM32H72xxx and STM32H73xxx lines */
289 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
290 do { \
291  __IO uint32_t tmpreg = 0x00; \
292  /* Configure the Voltage Scaling */ \
293  MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \
294  /* Delay after setting the voltage scaling */ \
295  tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
296  UNUSED(tmpreg); \
297 } while(0)
298 #endif /* defined(SYSCFG_PWRCR_ODEN) */
299 #endif /* defined (PWR_SRDCR_VOS) */
300 
378 #if defined (DUAL_CORE) /* Dual core lines */
379 #define __HAL_PWR_GET_FLAG(__FLAG__) \
380 (((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
381  ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
382  ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
383  ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\
384  ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) :\
385  ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\
386  ((__FLAG__) == PWR_FLAG_CPU_HOLD) ? ((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F) :\
387  ((__FLAG__) == PWR_FLAG_CPU2_HOLD) ? ((PWR->CPUCR & PWR_CPUCR_HOLD2F) == PWR_CPUCR_HOLD2F) :\
388  ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
389  ((__FLAG__) == PWR_FLAG2_SB) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF) == PWR_CPU2CR_SBF) :\
390  ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\
391  ((__FLAG__) == PWR_FLAG2_STOP) ? ((PWR->CPU2CR & PWR_CPU2CR_STOPF) == PWR_CPU2CR_STOPF) :\
392  ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\
393  ((__FLAG__) == PWR_FLAG2_SB_D1) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1) :\
394  ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\
395  ((__FLAG__) == PWR_FLAG2_SB_D2) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2) :\
396  ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\
397  ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\
398  ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\
399  ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
400  ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
401 #else /* Single core lines */
402 #if defined (PWR_CPUCR_SBF_D2) /* STM32H72x, STM32H73x, STM32H74x and STM32H75x lines */
403 #if defined (SMPS) /* STM32H725 and STM32H735 lines */
404 #define __HAL_PWR_GET_FLAG(__FLAG__) \
405 (((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
406  ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
407  ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
408  ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\
409  ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_FLAG_SMPSEXTRDY) == PWR_FLAG_SMPSEXTRDY) :\
410  ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\
411  ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
412  ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\
413  ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\
414  ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\
415  ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\
416  ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\
417  ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\
418  ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
419  ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
420 #else /* STM32H723, STM32H733, STM32H742, STM32H743, STM32H750 and STM32H753 lines */
421 #define __HAL_PWR_GET_FLAG(__FLAG__) \
422 (((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
423  ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
424  ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
425  ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\
426  ((__FLAG__) == PWR_FLAG_SCUEN) ? ((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) :\
427  ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\
428  ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
429  ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\
430  ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\
431  ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\
432  ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\
433  ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\
434  ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\
435  ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
436  ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
437 #endif /* defined (SMPS) */
438 #else /* STM32H7Axxx and STM32H7Bxxx lines */
439 #if defined (SMPS) /* STM32H7AxxQ and STM32H7BxxQ lines */
440 #define __HAL_PWR_GET_FLAG(__FLAG__) \
441 (((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
442  ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
443  ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
444  ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\
445  ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY) == PWR_SRDCR_VOSRDY) :\
446  ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\
447  ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
448  ((__FLAG__) == PWR_FLAG_MMCVDO) ? ((PWR->CSR1 & PWR_CSR1_MMCVDO) == PWR_CSR1_MMCVDO) :\
449  ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) :\
450  ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\
451  ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\
452  ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\
453  ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
454  ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
455 #else /* STM32H7Axx and STM32H7Bxx lines */
456 #define __HAL_PWR_GET_FLAG(__FLAG__) \
457 (((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
458  ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
459  ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
460  ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\
461  ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY) == PWR_SRDCR_VOSRDY) :\
462  ((__FLAG__) == PWR_FLAG_SCUEN) ? ((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) :\
463  ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\
464  ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\
465  ((__FLAG__) == PWR_FLAG_MMCVDO) ? ((PWR->CSR1 & PWR_CSR1_MMCVDO) == PWR_CSR1_MMCVDO) :\
466  ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\
467  ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\
468  ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\
469  ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\
470  ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
471 #endif /* SMPS */
472 #endif /* PWR_CPUCR_SBF_D2 */
473 #endif /* DUAL_CORE */
474 
488 #define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1)
489 
490 #if defined (DUAL_CORE)
491 
501 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) \
502 do { \
503  SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); \
504  SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \
505 } while(0)
506 #else
507 
517 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
518 #endif /* defined (DUAL_CORE) */
519 
533 #define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__))
534 
539 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
540 
541 #if defined (DUAL_CORE)
542 
546 #define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
547 #endif /* defined (DUAL_CORE) */
548 
553 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
554 
555 #if defined (DUAL_CORE)
556 
560 #define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
561 #endif /* defined (DUAL_CORE) */
562 
567 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
568 
569 #if defined (DUAL_CORE)
570 
574 #define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
575 #endif /* defined (DUAL_CORE) */
576 
581 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
582 
583 #if defined (DUAL_CORE)
584 
588 #define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
589 #endif /* defined (DUAL_CORE) */
590 
595 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
596 
601 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
602 
607 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
608 
613 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
614 
619 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
620 do { \
621  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
622  __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
623 } while(0);
624 
629 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
630 do { \
631  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
632  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
633 } while(0);
634 
639 #define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
640 
641 #if defined (DUAL_CORE)
642 
646 #define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
647 #endif /* defined (DUAL_CORE) */
648 
653 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)
654 
655 #if defined (DUAL_CORE)
656 
660 #define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD)
661 #endif /* defined (DUAL_CORE) */
662 
667 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
668 
672 /* Include PWR HAL Extension module */
673 #include "stm32h7xx_hal_pwr_ex.h"
674 
675 /* Exported functions --------------------------------------------------------*/
683 /* Initialization and de-initialization functions *****************************/
684 void HAL_PWR_DeInit (void);
685 void HAL_PWR_EnableBkUpAccess (void);
686 void HAL_PWR_DisableBkUpAccess (void);
694 /* Peripheral Control functions **********************************************/
695 /* PVD configuration */
696 void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD);
697 void HAL_PWR_EnablePVD (void);
698 void HAL_PWR_DisablePVD (void);
699 
700 /* WakeUp pins configuration */
701 void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity);
702 void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx);
703 
704 /* Low Power modes entry */
705 void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry);
706 void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry);
707 void HAL_PWR_EnterSTANDBYMode (void);
708 
709 /* Power PVD IRQ Handler */
710 void HAL_PWR_PVD_IRQHandler (void);
711 void HAL_PWR_PVDCallback (void);
712 
713 /* Cortex System Control functions *******************************************/
714 void HAL_PWR_EnableSleepOnExit (void);
715 void HAL_PWR_DisableSleepOnExit (void);
716 void HAL_PWR_EnableSEVOnPend (void);
717 void HAL_PWR_DisableSEVOnPend (void);
726 /* Private types -------------------------------------------------------------*/
727 /* Private variables ---------------------------------------------------------*/
728 /* Private constants ---------------------------------------------------------*/
736 #define PWR_EXTI_LINE_PVD EXTI_IMR1_IM16
745 /* Private macros ------------------------------------------------------------*/
746 
753 /* Check PVD level parameter */
754 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) ||\
755  ((LEVEL) == PWR_PVDLEVEL_1) ||\
756  ((LEVEL) == PWR_PVDLEVEL_2) ||\
757  ((LEVEL) == PWR_PVDLEVEL_3) ||\
758  ((LEVEL) == PWR_PVDLEVEL_4) ||\
759  ((LEVEL) == PWR_PVDLEVEL_5) ||\
760  ((LEVEL) == PWR_PVDLEVEL_6) ||\
761  ((LEVEL) == PWR_PVDLEVEL_7))
762 
763 /* Check PVD mode parameter */
764 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING) ||\
765  ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\
766  ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\
767  ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\
768  ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\
769  ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\
770  ((MODE) == PWR_PVD_MODE_NORMAL))
771 
772 /* Check low power regulator parameter */
773 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) ||\
774  ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
775 
776 /* Check low power mode entry parameter */
777 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\
778  ((ENTRY) == PWR_SLEEPENTRY_WFE))
779 
780 /* Check low power mode entry parameter */
781 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\
782  ((ENTRY) == PWR_STOPENTRY_WFE))
783 
784 /* Check voltage scale level parameter */
785 #define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \
786  ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
787  ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
788  ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
789 
805 #ifdef __cplusplus
806 }
807 #endif /* __cplusplus */
808 
809 #endif /* STM32H7xx_HAL_PWR_H */
810 
811 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_PWR_EnterSTOPMode
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
HAL_PWR_EnablePVD
void HAL_PWR_EnablePVD(void)
HAL_PWR_EnterSTANDBYMode
void HAL_PWR_EnterSTANDBYMode(void)
PWR_PVDTypeDef
PWR PVD configuration structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:48
HAL_PWR_DisableBkUpAccess
void HAL_PWR_DisableBkUpAccess(void)
HAL_PWR_DisableSEVOnPend
void HAL_PWR_DisableSEVOnPend(void)
HAL_PWR_PVDCallback
void HAL_PWR_PVDCallback(void)
HAL_PWR_EnableBkUpAccess
void HAL_PWR_EnableBkUpAccess(void)
stm32h7xx_hal_pwr_ex.h
Header file of PWR HAL Extension module.
HAL_PWR_EnableSleepOnExit
void HAL_PWR_EnableSleepOnExit(void)
HAL_PWR_DisablePVD
void HAL_PWR_DisablePVD(void)
HAL_PWR_PVD_IRQHandler
void HAL_PWR_PVD_IRQHandler(void)
HAL_PWR_ConfigPVD
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
HAL_PWR_DeInit
void HAL_PWR_DeInit(void)
HAL_PWR_DisableWakeUpPin
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_PWR_EnableSEVOnPend
void HAL_PWR_EnableSEVOnPend(void)
HAL_PWR_EnterSLEEPMode
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
HAL_PWR_DisableSleepOnExit
void HAL_PWR_DisableSleepOnExit(void)
Mode
Definition: porcupine/demo/c/dr_libs/tests/external/miniaudio/extras/stb_vorbis.c:745
HAL_PWR_EnableWakeUpPin
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)

picovoice_driver
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autogenerated on Fri Apr 1 2022 02:14:54