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56 #if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64) && \
57 (defined(__GNUC__) || defined(__clang__))
59 #include "../internal.h"
68 #define mul_add(r, a, word, carry) \
70 register BN_ULONG high, low; \
71 __asm__("mulq %3" : "=a"(low), "=d"(high) : "a"(word), "m"(a) : "cc"); \
72 __asm__("addq %2,%0; adcq %3,%1" \
73 : "+r"(carry), "+d"(high) \
76 __asm__("addq %2,%0; adcq %3,%1" \
77 : "+m"(r), "+d"(high) \
78 : "r"(carry), "g"(0) \
83 #define mul(r, a, word, carry) \
85 register BN_ULONG high, low; \
86 __asm__("mulq %3" : "=a"(low), "=d"(high) : "a"(word), "g"(a) : "cc"); \
87 __asm__("addq %2,%0; adcq %3,%1" \
88 : "+r"(carry), "+d"(high) \
95 #define sqr(r0, r1, a) __asm__("mulq %2" : "=a"(r0), "=d"(r1) : "a"(a) : "cc");
139 mul(rp[0], ap[0], w,
c1);
140 mul(rp[1], ap[1], w,
c1);
141 mul(rp[2], ap[2], w,
c1);
142 mul(rp[3], ap[3], w,
c1);
148 mul(rp[0], ap[0], w,
c1);
152 mul(rp[1], ap[1], w,
c1);
156 mul(rp[2], ap[2], w,
c1);
188 BN_ULONG
bn_add_words(BN_ULONG *rp,
const BN_ULONG *ap,
const BN_ULONG *bp,
202 " movq (%4,%2,8),%0 \n"
203 " adcq (%5,%2,8),%0 \n"
204 " movq %0,(%3,%2,8) \n"
209 :
"=&r"(
ret),
"+c"(
n),
"+r"(
i)
210 :
"r"(rp),
"r"(ap),
"r"(bp)
216 BN_ULONG
bn_sub_words(BN_ULONG *rp,
const BN_ULONG *ap,
const BN_ULONG *bp,
230 " movq (%4,%2,8),%0 \n"
231 " sbbq (%5,%2,8),%0 \n"
232 " movq %0,(%3,%2,8) \n"
237 :
"=&r"(
ret),
"+c"(
n),
"+r"(
i)
238 :
"r"(rp),
"r"(ap),
"r"(bp)
251 #define mul_add_c(a, b, c0, c1, c2) \
254 __asm__("mulq %3" : "=a"(t1), "=d"(t2) : "a"(a), "m"(b) : "cc"); \
255 __asm__("addq %3,%0; adcq %4,%1; adcq %5,%2" \
256 : "+r"(c0), "+r"(c1), "+r"(c2) \
257 : "r"(t1), "r"(t2), "g"(0) \
261 #define sqr_add_c(a, i, c0, c1, c2) \
264 __asm__("mulq %2" : "=a"(t1), "=d"(t2) : "a"((a)[i]) : "cc"); \
265 __asm__("addq %3,%0; adcq %4,%1; adcq %5,%2" \
266 : "+r"(c0), "+r"(c1), "+r"(c2) \
267 : "r"(t1), "r"(t2), "g"(0) \
271 #define mul_add_c2(a, b, c0, c1, c2) \
274 __asm__("mulq %3" : "=a"(t1), "=d"(t2) : "a"(a), "m"(b) : "cc"); \
275 __asm__("addq %3,%0; adcq %4,%1; adcq %5,%2" \
276 : "+r"(c0), "+r"(c1), "+r"(c2) \
277 : "r"(t1), "r"(t2), "g"(0) \
279 __asm__("addq %3,%0; adcq %4,%1; adcq %5,%2" \
280 : "+r"(c0), "+r"(c1), "+r"(c2) \
281 : "r"(t1), "r"(t2), "g"(0) \
285 #define sqr_add_c2(a, i, j, c0, c1, c2) mul_add_c2((a)[i], (a)[j], c0, c1, c2)
287 void bn_mul_comba8(BN_ULONG
r[16],
const BN_ULONG
a[8],
const BN_ULONG
b[8]) {
389 void bn_mul_comba4(BN_ULONG
r[8],
const BN_ULONG
a[4],
const BN_ULONG
b[4]) {
541 #endif // !NO_ASM && X86_64 && (__GNUC__ || __clang__)
#define sqr_add_c2(a, i, j, c0, c1, c2)
#define sqr_add_c(a, i, c0, c1, c2)
UniquePtr< SSL_SESSION > ret
#define mul_add_c(a, b, c0, c1, c2)
#define mul_add(r, a, w, c)
grpc
Author(s):
autogenerated on Thu Mar 13 2025 03:01:54