arm_arch.h
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52 
53 #ifndef OPENSSL_HEADER_ARM_ARCH_H
54 #define OPENSSL_HEADER_ARM_ARCH_H
55 
56 #if !defined(__ARM_ARCH__)
57 # if defined(__CC_ARM)
58 # define __ARM_ARCH__ __TARGET_ARCH_ARM
59 # if defined(__BIG_ENDIAN)
60 # define __ARMEB__
61 # else
62 # define __ARMEL__
63 # endif
64 # elif defined(__GNUC__)
65 # if defined(__aarch64__)
66 # define __ARM_ARCH__ 8
67 # if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
68 # define __ARMEB__
69 # else
70 # define __ARMEL__
71 # endif
72  // Why doesn't gcc define __ARM_ARCH__? Instead it defines
73  // bunch of below macros. See all_architectires[] table in
74  // gcc/config/arm/arm.c. On a side note it defines
75  // __ARMEL__/__ARMEB__ for little-/big-endian.
76 # elif defined(__ARM_ARCH)
77 # define __ARM_ARCH__ __ARM_ARCH
78 # elif defined(__ARM_ARCH_8A__)
79 # define __ARM_ARCH__ 8
80 # elif defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || \
81  defined(__ARM_ARCH_7R__)|| defined(__ARM_ARCH_7M__) || \
82  defined(__ARM_ARCH_7EM__)
83 # define __ARM_ARCH__ 7
84 # elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || \
85  defined(__ARM_ARCH_6K__)|| defined(__ARM_ARCH_6M__) || \
86  defined(__ARM_ARCH_6Z__)|| defined(__ARM_ARCH_6ZK__) || \
87  defined(__ARM_ARCH_6T2__)
88 # define __ARM_ARCH__ 6
89 # elif defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) || \
90  defined(__ARM_ARCH_5E__)|| defined(__ARM_ARCH_5TE__) || \
91  defined(__ARM_ARCH_5TEJ__)
92 # define __ARM_ARCH__ 5
93 # elif defined(__ARM_ARCH_4__) || defined(__ARM_ARCH_4T__)
94 # define __ARM_ARCH__ 4
95 # else
96 # error "unsupported ARM architecture"
97 # endif
98 # endif
99 #endif
100 
101 // Even when building for 32-bit ARM, support for aarch64 crypto instructions
102 // will be included.
103 #define __ARM_MAX_ARCH__ 8
104 
105 // ARMV7_NEON is true when a NEON unit is present in the current CPU.
106 #define ARMV7_NEON (1 << 0)
107 
108 // ARMV8_AES indicates support for hardware AES instructions.
109 #define ARMV8_AES (1 << 2)
110 
111 // ARMV8_SHA1 indicates support for hardware SHA-1 instructions.
112 #define ARMV8_SHA1 (1 << 3)
113 
114 // ARMV8_SHA256 indicates support for hardware SHA-256 instructions.
115 #define ARMV8_SHA256 (1 << 4)
116 
117 // ARMV8_PMULL indicates support for carryless multiplication.
118 #define ARMV8_PMULL (1 << 5)
119 
120 #if defined(__ASSEMBLER__)
121 
122 // Support macros for
123 // - Armv8.3-A Pointer Authentication and
124 // - Armv8.5-A Branch Target Identification
125 // features which require emitting a .note.gnu.property section with the
126 // appropriate architecture-dependent feature bits set.
127 //
128 // |AARCH64_SIGN_LINK_REGISTER| and |AARCH64_VALIDATE_LINK_REGISTER| expand to
129 // PACIxSP and AUTIxSP, respectively. |AARCH64_SIGN_LINK_REGISTER| should be
130 // used immediately before saving the LR register (x30) to the stack.
131 // |AARCH64_VALIDATE_LINK_REGISTER| should be used immediately after restoring
132 // it. Note |AARCH64_SIGN_LINK_REGISTER|'s modifications to LR must be undone
133 // with |AARCH64_VALIDATE_LINK_REGISTER| before RET. The SP register must also
134 // have the same value at the two points. For example:
135 //
136 // .global f
137 // f:
138 // AARCH64_SIGN_LINK_REGISTER
139 // stp x29, x30, [sp, #-96]!
140 // mov x29, sp
141 // ...
142 // ldp x29, x30, [sp], #96
143 // AARCH64_VALIDATE_LINK_REGISTER
144 // ret
145 //
146 // |AARCH64_VALID_CALL_TARGET| expands to BTI 'c'. Either it, or
147 // |AARCH64_SIGN_LINK_REGISTER|, must be used at every point that may be an
148 // indirect call target. In particular, all symbols exported from a file must
149 // begin with one of these macros. For example, a leaf function that does not
150 // save LR can instead use |AARCH64_VALID_CALL_TARGET|:
151 //
152 // .globl return_zero
153 // return_zero:
154 // AARCH64_VALID_CALL_TARGET
155 // mov x0, #0
156 // ret
157 //
158 // A non-leaf function which does not immediately save LR may need both macros
159 // because |AARCH64_SIGN_LINK_REGISTER| appears late. For example, the function
160 // may jump to an alternate implementation before setting up the stack:
161 //
162 // .globl with_early_jump
163 // with_early_jump:
164 // AARCH64_VALID_CALL_TARGET
165 // cmp x0, #128
166 // b.lt .Lwith_early_jump_128
167 // AARCH64_SIGN_LINK_REGISTER
168 // stp x29, x30, [sp, #-96]!
169 // mov x29, sp
170 // ...
171 // ldp x29, x30, [sp], #96
172 // AARCH64_VALIDATE_LINK_REGISTER
173 // ret
174 //
175 // .Lwith_early_jump_128:
176 // ...
177 // ret
178 //
179 // These annotations are only required with indirect calls. Private symbols that
180 // are only the target of direct calls do not require annotations. Also note
181 // that |AARCH64_VALID_CALL_TARGET| is only valid for indirect calls (BLR), not
182 // indirect jumps (BR). Indirect jumps in assembly are currently not supported
183 // and would require a macro for BTI 'j'.
184 //
185 // Although not necessary, it is safe to use these macros in 32-bit ARM
186 // assembly. This may be used to simplify dual 32-bit and 64-bit files.
187 //
188 // References:
189 // - "ELF for the ArmĀ® 64-bit Architecture"
190 // https://github.com/ARM-software/abi-aa/blob/master/aaelf64/aaelf64.rst
191 // - "Providing protection for complex software"
192 // https://developer.arm.com/architectures/learn-the-architecture/providing-protection-for-complex-software
193 
194 #if defined(__ARM_FEATURE_BTI_DEFAULT) && __ARM_FEATURE_BTI_DEFAULT == 1
195 #define GNU_PROPERTY_AARCH64_BTI (1 << 0) // Has Branch Target Identification
196 #define AARCH64_VALID_CALL_TARGET hint #34 // BTI 'c'
197 #else
198 #define GNU_PROPERTY_AARCH64_BTI 0 // No Branch Target Identification
199 #define AARCH64_VALID_CALL_TARGET
200 #endif
201 
202 #if defined(__ARM_FEATURE_PAC_DEFAULT) && \
203  (__ARM_FEATURE_PAC_DEFAULT & 1) == 1 // Signed with A-key
204 #define GNU_PROPERTY_AARCH64_POINTER_AUTH \
205  (1 << 1) // Has Pointer Authentication
206 #define AARCH64_SIGN_LINK_REGISTER hint #25 // PACIASP
207 #define AARCH64_VALIDATE_LINK_REGISTER hint #29 // AUTIASP
208 #elif defined(__ARM_FEATURE_PAC_DEFAULT) && \
209  (__ARM_FEATURE_PAC_DEFAULT & 2) == 2 // Signed with B-key
210 #define GNU_PROPERTY_AARCH64_POINTER_AUTH \
211  (1 << 1) // Has Pointer Authentication
212 #define AARCH64_SIGN_LINK_REGISTER hint #27 // PACIBSP
213 #define AARCH64_VALIDATE_LINK_REGISTER hint #31 // AUTIBSP
214 #else
215 #define GNU_PROPERTY_AARCH64_POINTER_AUTH 0 // No Pointer Authentication
216 #if GNU_PROPERTY_AARCH64_BTI != 0
217 #define AARCH64_SIGN_LINK_REGISTER AARCH64_VALID_CALL_TARGET
218 #else
219 #define AARCH64_SIGN_LINK_REGISTER
220 #endif
221 #define AARCH64_VALIDATE_LINK_REGISTER
222 #endif
223 
224 #if GNU_PROPERTY_AARCH64_POINTER_AUTH != 0 || GNU_PROPERTY_AARCH64_BTI != 0
225 .pushsection .note.gnu.property, "a";
226 .balign 8;
227 .long 4;
228 .long 0x10;
229 .long 0x5;
230 .asciz "GNU";
231 .long 0xc0000000; /* GNU_PROPERTY_AARCH64_FEATURE_1_AND */
232 .long 4;
233 .long (GNU_PROPERTY_AARCH64_POINTER_AUTH | GNU_PROPERTY_AARCH64_BTI);
234 .long 0;
235 .popsection;
236 #endif
237 
238 #endif /* defined __ASSEMBLER__ */
239 
240 #endif // OPENSSL_HEADER_ARM_ARCH_H


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autogenerated on Thu Mar 13 2025 02:58:33