nmuart.c
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1 
35 #include "common/include/nm_common.h"
36 
37 #ifdef CONF_WINC_USE_UART
38 
39 #include "driver/source/nmuart.h"
40 #include "bus_wrapper/include/nm_bus_wrapper.h"
41 
42 #define HDR_SZ 12
43 
44 static uint8 get_cs(uint8* b, uint8 sz){
45  int i;
46  uint8 cs = 0;
47  for(i = 0; i < sz; i++)
48  cs ^= b[i];
49  return cs;
50 }
51 
52 /*
53 * @fn nm_uart_sync_cmd
54 * @brief Check COM Port
55 * @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
56 * @author Dina El Sissy
57 * @date 13 AUG 2012
58 * @version 1.0
59 */
60 sint8 nm_uart_sync_cmd(void)
61 {
62  tstrNmUartDefault strUart;
63  sint8 s8Ret = M2M_ERR_BUS_FAIL;
64  uint8 b [HDR_SZ+1];
65  uint8 onchip = 0;
66  int escape = 3;
67 
68  // send query char up to 3 times
69  while (escape-- && (s8Ret != M2M_SUCCESS))
70  {
71  b[0] = 0x12;
72  strUart.pu8Buf = b;
73  strUart.u16Sz = 1;
74 
75  // then read back all chars in the buffer if any, is last char what we are looking for
76  s8Ret = nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart);
77  if (M2M_SUCCESS == s8Ret)
78  {
79  uint8 lastchar;
80 
81  // drain buffer
82  while (M2M_SUCCESS == s8Ret)
83  {
84  lastchar = b[0];
85  s8Ret = nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart);
86  }
87 
88  switch (lastchar)
89  {
90  case 0x5a:
91  onchip = 1;
92  M2M_INFO("Built-in WINCxx00 UART Found\n");
93  s8Ret = M2M_SUCCESS;
94  break;
95  case 0x5b:
96  onchip = 0;
97  M2M_INFO("WINCxx00 Serial Bridge Found\n");
98  s8Ret = M2M_SUCCESS;
99  break;
100  case 0x5c:
101  onchip = 2;
102  M2M_INFO("WINCxx00 Serial Bridge + AT CMD app Found\n");
103  s8Ret = M2M_SUCCESS;
104  break;
105  case 0x12:
106  M2M_INFO("failed to read Serial Bridge ID response\n");
107  s8Ret = M2M_ERR_BUS_FAIL;
108  break;
109  default:
110  M2M_INFO("Non Serial Bridge Found\n");
111  s8Ret = M2M_ERR_BUS_FAIL;
112  break;
113  }
114  }
115  else
116  {
117  M2M_ERR("failed to send Serial Bridge ID Query\n");
118  }
119  }
120 
121  if(s8Ret == M2M_SUCCESS)
122  s8Ret = (sint8)onchip;
123 
124  return s8Ret;
125 }
126 
127 /*
128 * @fn nm_uart_reboot_cmd
129 * @brief Sends a command to the MCU to force reboot
130 * @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
131 * @version 1.0
132 */
133 
134 sint8 nm_uart_reboot_cmd(void)
135 {
136  tstrNmUartDefault strUart;
137  sint8 s8Ret = M2M_SUCCESS;
138  uint8 b[HDR_SZ + 1];
139  uint8 rsz;
140  uint8 onchip = 0;
141 
142  /*read reg*/
143  b[0] = 0x13;
144 
145  rsz = 1;
146  strUart.pu8Buf = b;
147  strUart.u16Sz = 1;
148 
149  if (M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
150  {
151  M2M_ERR("failed to send reboot cmd\n");
152  s8Ret = M2M_ERR_BUS_FAIL;
153  }
154  return s8Ret;
155 }
156 
157 
158  sint8 nm_uart_read_reg_with_ret(uint32 u32Addr, uint32* pu32RetVal)
159 {
160  tstrNmUartDefault strUart;
161  sint8 s8Ret = M2M_SUCCESS;
162  uint8 b [HDR_SZ+1];
163  uint8 rsz;
164 
165  /*read reg*/
166  b[0] = 0xa5;
167  b[1] = 0;
168  b[2] = 0;
169  b[3] = 0;
170  b[4] = 0;
171  b[5] = (uint8)(u32Addr & 0x000000ff);
172  b[6] = (uint8)((u32Addr & 0x0000ff00)>>8);
173  b[7] = (uint8)((u32Addr & 0x00ff0000)>>16);
174  b[8] = (uint8)((u32Addr & 0xff000000)>>24);
175  b[9] = 0;
176  b[10] = 0;
177  b[11] = 0;
178  b[12] = 0;
179 
180  b[2] = get_cs(&b[1],HDR_SZ);
181 
182  rsz = 4;
183  strUart.pu8Buf = b;
184  strUart.u16Sz = sizeof(b);
185 
186  if(M2M_SUCCESS == nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
187  {
188  if(!nm_bus_get_chip_type())
189  {
190  strUart.u16Sz = 1;
191  if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
192  {
193  s8Ret = M2M_ERR_BUS_FAIL;
194  }
195  if(b[0] == 0xAC)
196  {
197  M2M_DBG("Successfully sent the command\n");
198  strUart.u16Sz = rsz;
199  if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
200  {
201  s8Ret = M2M_ERR_BUS_FAIL;
202  }
203  }
204  else
205  {
206  s8Ret = M2M_ERR_BUS_FAIL;
207  }
208  }
209  else
210  {
211  strUart.u16Sz = rsz;
212  if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
213  {
214  s8Ret = M2M_ERR_BUS_FAIL;
215  }
216  }
217  }
218  else
219  {
220  M2M_ERR("failed to send cfg bytes\n");
221  s8Ret = M2M_ERR_BUS_FAIL;
222  }
223 
224  *pu32RetVal = ((uint32)b[0] << 24) | ((uint32)b[1] << 16) | ((uint32)b[2] << 8) | b[3];
225 
226  return s8Ret;
227 }
228 
229 /*
230 * @fn nm_uart_read_reg
231 * @brief Read register
232 * @param [in] u32Addr
233 * Register address
234 * @return Register value
235 * @author Dina El Sissy
236 * @date 13 AUG 2012
237 * @version 1.0
238 */
239 uint32 nm_uart_read_reg(uint32 u32Addr)
240 {
241  uint32 val;
242  nm_uart_read_reg_with_ret(u32Addr , &val);
243  return val;
244 }
245 
246 /*
247 * @fn nm_uart_write_reg
248 * @brief write register
249 * @param [in] u32Addr
250 * Register address
251 * @param [in] u32Val
252 * Value to be written to the register
253 * @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
254 * @author Dina El Sissy
255 * @date 13 AUG 2012
256 * @version 1.0
257 */
258 sint8 nm_uart_write_reg(uint32 u32Addr, uint32 u32Val)
259 {
260  tstrNmUartDefault strUart;
261  sint8 s8Ret = M2M_SUCCESS;
262  uint8 b[HDR_SZ+1];
263 
264  /*write reg*/
265  b[0] = 0xa5;
266  b[1] = 1;
267  b[2] = 0;
268  b[3] = 0;
269  b[4] = 0;
270  b[5] = (uint8)(u32Addr & 0x000000ff);
271  b[6] = (uint8)((u32Addr & 0x0000ff00)>>8);
272  b[7] = (uint8)((u32Addr & 0x00ff0000)>>16);
273  b[8] = (uint8)((u32Addr & 0xff000000)>>24);
274  b[9] = (uint8)(u32Val & 0x000000ff);
275  b[10] = (uint8)((u32Val & 0x0000ff00)>>8);
276  b[11] = (uint8)((u32Val & 0x00ff0000)>>16);
277  b[12] = (uint8)((u32Val & 0xff000000)>>24);
278 
279  b[2] = get_cs(&b[1],HDR_SZ);
280 
281  get_cs(&b[1],HDR_SZ);
282 
283  strUart.pu8Buf = b;
284  strUart.u16Sz = sizeof(b);
285 
286  if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
287  {
288  M2M_ERR("write error\n");
289  s8Ret = M2M_ERR_BUS_FAIL;
290  }
291  else
292  {
293  if(!nm_bus_get_chip_type())
294  {
295  //check for the ack from the SAMD21 for the packet reception.
296  strUart.u16Sz = 1;
297  if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
298  {
299  s8Ret = M2M_ERR_BUS_FAIL;
300  }
301  if(b[0] == 0xAC)
302  {
303  M2M_DBG("Successfully sent the reg write command\n");
304  }
305  else
306  {
307  M2M_ERR("write error\n");
308  s8Ret = M2M_ERR_BUS_FAIL;
309  }
310  }
311  }
312 
313  return s8Ret;
314 }
315 
316 
331 sint8 nm_uart_read_block(uint32 u32Addr, uint8 *pu8Buf, uint16 u16Sz)
332 {
333  tstrNmUartDefault strUart;
334  sint8 s8Ret = M2M_SUCCESS;
335  uint8 au8Buf[HDR_SZ+1];
336 
337  au8Buf[0] = 0xa5;
338  au8Buf[1] = 2;
339  au8Buf[2] = 0;
340  au8Buf[3] = (uint8)(u16Sz & 0x00ff);
341  au8Buf[4] = (uint8)((u16Sz & 0xff00)>>8);
342  au8Buf[5] = (uint8)(u32Addr & 0x000000ff);
343  au8Buf[6] = (uint8)((u32Addr & 0x0000ff00)>>8);
344  au8Buf[7] = (uint8)((u32Addr & 0x00ff0000)>>16);
345  au8Buf[8] = (uint8)((u32Addr & 0xff000000)>>24);
346  au8Buf[9] = 0;
347  au8Buf[10] = 0;
348  au8Buf[11] = 0;
349  au8Buf[12] = 0;
350 
351  au8Buf[2] = get_cs(&au8Buf[1],HDR_SZ);
352 
353  strUart.pu8Buf = au8Buf;
354  strUart.u16Sz = sizeof(au8Buf);
355 
356  if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
357  {
358  M2M_ERR("write error\n");
359  s8Ret = M2M_ERR_BUS_FAIL;
360  }
361  else
362  {
363  if(!nm_bus_get_chip_type())
364  {
365  //check for the ack from the SAMD21 for the packet reception.
366  strUart.u16Sz = 1;
367  if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
368  {
369  s8Ret = M2M_ERR_BUS_FAIL;
370  }
371  if(au8Buf[0] == 0xAC)
372  {
373  M2M_DBG("Successfully sent the block read command\n");
374  strUart.pu8Buf = pu8Buf;
375  strUart.u16Sz = u16Sz;
376 
377  if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
378  {
379  M2M_ERR("read error\n");
380  s8Ret = M2M_ERR_BUS_FAIL;
381  }
382  }
383  else
384  {
385  M2M_ERR("write error (Error sending the block read command)\n");
386  s8Ret = M2M_ERR_BUS_FAIL;
387  }
388  }
389  else
390  {
391  strUart.pu8Buf = pu8Buf;
392  strUart.u16Sz = u16Sz;
393 
394  if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
395  {
396  M2M_ERR("read error\n");
397  s8Ret = M2M_ERR_BUS_FAIL;
398  }
399  }
400  }
401 
402  return s8Ret;
403 }
404 
419 sint8 nm_uart_write_block(uint32 u32Addr, uint8 *puBuf, uint16 u16Sz)
420 {
421  tstrNmUartDefault strUart;
422  sint8 s8Ret = M2M_SUCCESS;
423  static uint8 au8Buf[HDR_SZ+1];
424 
425  au8Buf[0] = 0xa5;
426  au8Buf[1] = 3;
427  au8Buf[2] = 0;
428  au8Buf[3] = (uint8)(u16Sz & 0x00ff);
429  au8Buf[4] = (uint8)((u16Sz & 0xff00)>>8);
430  au8Buf[5] = (uint8)(u32Addr & 0x000000ff);
431  au8Buf[6] = (uint8)((u32Addr & 0x0000ff00)>>8);
432  au8Buf[7] = (uint8)((u32Addr & 0x00ff0000)>>16);
433  au8Buf[8] = (uint8)((u32Addr & 0xff000000)>>24);
434  au8Buf[9] = 0;
435  au8Buf[10] = 0;
436  au8Buf[11] = 0;
437  au8Buf[12] = 0;
438 
439  au8Buf[2] = get_cs(&au8Buf[1],HDR_SZ);
440 
441  strUart.pu8Buf = au8Buf;
442  strUart.u16Sz = sizeof(au8Buf);
443 
444  if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
445  {
446  M2M_ERR("write error\n");
447  s8Ret = M2M_ERR_BUS_FAIL;
448  }
449  else
450  {
451  if(!nm_bus_get_chip_type())
452  {
453  //check for the ack from the SAMD21 for the packet reception.
454  strUart.u16Sz = 1;
455  if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
456  {
457  s8Ret = M2M_ERR_BUS_FAIL;
458  }
459  if(au8Buf[0] == 0xAC)
460  {
461  M2M_DBG("Successfully sent the block Write command\n");
462  strUart.pu8Buf = puBuf;
463  strUart.u16Sz = u16Sz;
464 
465  if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
466  {
467  M2M_ERR("write error\n");
468  s8Ret = M2M_ERR_BUS_FAIL;
469  }
470  else
471  {
472  //check for the ack from the SAMD21 for the payload reception.
473  strUart.pu8Buf = au8Buf;
474  strUart.u16Sz = 1;
475  if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
476  {
477  s8Ret = M2M_ERR_BUS_FAIL;
478  }
479  if(au8Buf[0] == 0xAC)
480  {
481  M2M_DBG("Successfully sent the data payload\n");
482  }
483  else
484  {
485  M2M_ERR("write error\n");
486  s8Ret = M2M_ERR_BUS_FAIL;
487  }
488  }
489  }
490  else
491  {
492  M2M_ERR("write error (Error sending the block write command)\n");
493  s8Ret = M2M_ERR_BUS_FAIL;
494  }
495  }
496  else
497  {
498  strUart.pu8Buf = puBuf;
499  strUart.u16Sz = u16Sz;
500 
501  if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
502  {
503  M2M_ERR("write error\n");
504  s8Ret = M2M_ERR_BUS_FAIL;
505  }
506  }
507  }
508  return s8Ret;
509 }
510 
521 sint8 nm_uart_reconfigure(void *ptr)
522 {
523  tstrNmUartDefault strUart;
524  sint8 s8Ret = M2M_SUCCESS;
525  uint8 b[HDR_SZ+1];
526 
527  if (ptr == NULL)
528  {
529  M2M_ERR("port not open\n");
530  return M2M_ERR_BUS_FAIL;
531  }
532 
533  /*write reg*/
534  b[0] = 0xa5;
535  b[1] = 5;
536  b[2] = 0;
537  b[3] = 0;
538  b[4] = 0;
539  b[5] = 0;
540  b[6] = 0;
541  b[7] = 0;
542  b[8] = 0;
543  b[9] = (uint8)((*(unsigned long *)ptr) & 0x000000ff);
544  b[10] = (uint8)(((*(unsigned long *)ptr) & 0x0000ff00)>>8);
545  b[11] = (uint8)(((*(unsigned long *)ptr) & 0x00ff0000)>>16);
546  b[12] = (uint8)(((*(unsigned long *)ptr) & 0xff000000)>>24);
547 
548  b[2] = get_cs(&b[1],HDR_SZ);
549 
550  get_cs(&b[1],HDR_SZ);
551 
552  strUart.pu8Buf = b;
553  strUart.u16Sz = sizeof(b);
554 
555  if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
556  {
557  M2M_ERR("write error\n");
558  s8Ret = M2M_ERR_BUS_FAIL;
559  }
560  else
561  {
562  if(!nm_bus_get_chip_type())
563  {
564  //check for the ack from the SAMD21 for the packet reception.
565  strUart.u16Sz = 1;
566  if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
567  {
568  s8Ret = M2M_ERR_BUS_FAIL;
569  }
570  if(b[0] == 0xAC)
571  {
572  M2M_DBG("Successfully sent the UART reconfigure command\n");
573  }
574  else
575  {
576  M2M_ERR("write error\n");
577  s8Ret = M2M_ERR_BUS_FAIL;
578  }
579  }
580  }
581 
582  return s8Ret;
583 }
584 #endif
585 /* EOF */
nm_uart_reboot_cmd
sint8 nm_uart_reboot_cmd(void)
Sends a command to the MCU to force the reboot of the WINC.
NM_BUS_IOCTL_R
#define NM_BUS_IOCTL_R
Definition: nm_bus_wrapper.h:49
nm_common.h
This module contains common APIs declarations.
sint8
signed char sint8
Range of values between -128 to 127.
Definition: nm_bsp.h:111
nm_uart_read_block
sint8 nm_uart_read_block(uint32 u32Addr, uint8 *puBuf, uint16 u16Sz)
M2M_SUCCESS
#define M2M_SUCCESS
Definition: nm_common.h:51
nm_uart_read_reg_with_ret
sint8 nm_uart_read_reg_with_ret(uint32 u32Addr, uint32 *pu32RetVal)
NULL
#define NULL
Definition: nm_bsp.h:52
nm_bus_wrapper.h
This module contains WINC3400 bus wrapper APIs declarations.
uint16
unsigned short uint16
Range of values between 0 to 65535.
Definition: nm_bsp.h:96
M2M_DBG
#define M2M_DBG(...)
Definition: nm_debug.h:81
nm_uart_write_reg
sint8 nm_uart_write_reg(uint32 u32Addr, uint32 u32Val)
nm_uart_write_block
sint8 nm_uart_write_block(uint32 u32Addr, uint8 *puBuf, uint16 u16Sz)
M2M_ERR
#define M2M_ERR(...)
Definition: nm_debug.h:80
nm_uart_reconfigure
sint8 nm_uart_reconfigure(void *ptr)
nmuart.h
This module contains WINC3400 UART protocol bus APIs implementation.
M2M_INFO
#define M2M_INFO(...)
Definition: nm_debug.h:83
uint32
unsigned long uint32
Range of values between 0 to 4294967295.
Definition: nm_bsp.h:103
uint8
unsigned char uint8
Range of values between 0 to 255.
Definition: nm_bsp.h:89
nm_uart_read_reg
uint32 nm_uart_read_reg(uint32 u32Addr)
nm_bus_ioctl
sint8 nm_bus_ioctl(uint8 u8Cmd, void *pvParameter)
Definition: nm_bus_wrapper_same70.c:285
tstrNmUartDefault
Structure holding UART default operation parameters.
Definition: nm_bus_wrapper.h:113
nm_uart_sync_cmd
sint8 nm_uart_sync_cmd(void)
NM_BUS_IOCTL_W
#define NM_BUS_IOCTL_W
Definition: nm_bus_wrapper.h:50
M2M_ERR_BUS_FAIL
#define M2M_ERR_BUS_FAIL
Definition: nm_common.h:57

inertial_sense_ros
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autogenerated on Sun Feb 28 2021 03:17:58