37 #ifndef _M2M_ATE_MODE_H_    38 #define _M2M_ATE_MODE_H_    49 #define M2M_ATE_MAX_NUM_OF_RATES                (20)    52 #define M2M_ATE_MAX_FRAME_LENGTH                (1024)    55 #define M2M_ATE_MIN_FRAME_LENGTH                (1)    60 #define M2M_ATE_SUCCESS                                 (M2M_SUCCESS)    63 #define M2M_ATE_ERR_VALIDATE                    (M2M_ERR_FAIL)      66 #define M2M_ATE_ERR_TX_ALREADY_RUNNING  (-1)    69 #define M2M_ATE_ERR_RX_ALREADY_RUNNING  (-2)                        72 #define M2M_ATE_ERR_UNHANDLED_CASE              (-3)        75 #define M2M_ATE_RX_DISABLE_DA                   0x0    76 #define M2M_ATE_RX_ENABLE_DA                    0x1    78 #define M2M_ATE_RX_DISABLE_SA                   0x0    79 #define M2M_ATE_RX_ENABLE_SA                    0x1    81 #define M2M_ATE_DISABLE_SELF_MACADDR            0x0    82 #define M2M_ATE_SET_SELF_MACADDR                0x1    91         M2M_ATE_FW_STATE_STOP                   = 0x00,
    94         M2M_ATE_FW_STATE_RUN                    = 0x01,
   104         M2M_ATE_TX_RATE_1_Mbps_INDEX    = 0x00,
   105         M2M_ATE_TX_RATE_2_Mbps_INDEX    = 0x01,
   106         M2M_ATE_TX_RATE_55_Mbps_INDEX   = 0x02,
   107         M2M_ATE_TX_RATE_11_Mbps_INDEX   = 0x03,
   110         M2M_ATE_TX_RATE_6_Mbps_INDEX    = 0x04,
   111         M2M_ATE_TX_RATE_9_Mbps_INDEX    = 0x05,
   112         M2M_ATE_TX_RATE_12_Mbps_INDEX   = 0x06,
   113         M2M_ATE_TX_RATE_18_Mbps_INDEX   = 0x07,
   114         M2M_ATE_TX_RATE_24_Mbps_INDEX   = 0x08,
   115         M2M_ATE_TX_RATE_36_Mbps_INDEX   = 0x09,
   116         M2M_ATE_TX_RATE_48_Mbps_INDEX   = 0x0A,
   117         M2M_ATE_TX_RATE_54_Mbps_INDEX   = 0x0B,
   120         M2M_ATE_TX_RATE_MCS_0_INDEX             = 0x0C,
   121         M2M_ATE_TX_RATE_MCS_1_INDEX             = 0x0D,
   122         M2M_ATE_TX_RATE_MCS_2_INDEX             = 0x0E,
   123         M2M_ATE_TX_RATE_MCS_3_INDEX             = 0x0F,
   124         M2M_ATE_TX_RATE_MCS_4_INDEX             = 0x10,
   125         M2M_ATE_TX_RATE_MCS_5_INDEX             = 0x11,
   126         M2M_ATE_TX_RATE_MCS_6_INDEX             = 0x12,
   127         M2M_ATE_TX_RATE_MCS_7_INDEX             = 0x13,
   130 }tenuM2mAteTxIndexOfRates;
   137         M2M_ATE_TX_DUTY_1                               = 0x01,
   138         M2M_ATE_TX_DUTY_2                               = 0x02,
   139         M2M_ATE_TX_DUTY_3                               = 0x03,
   140         M2M_ATE_TX_DUTY_4                               = 0x04,
   141         M2M_ATE_TX_DUTY_5                               = 0x05,
   142         M2M_ATE_TX_DUTY_6                               = 0x06,
   143         M2M_ATE_TX_DUTY_7                               = 0x07,
   144         M2M_ATE_TX_DUTY_8                               = 0x08,
   145         M2M_ATE_TX_DUTY_9                               = 0x09,
   146         M2M_ATE_TX_DUTY_10                              = 0xA0,
   147 }tenuM2mAteTxDutyCycle;
   150 #define M2M_ATE_TX_DUTY_MAX_VALUE       M2M_ATE_TX_DUTY_1   153 #define M2M_ATE_TX_DUTY_MIN_VALUE       M2M_ATE_TX_DUTY_10   162         M2M_ATE_TX_DPD_DYNAMIC  = 0x00,
   163         M2M_ATE_TX_DPD_BYPASS   = 0x01,
   164         M2M_ATE_TX_DPD_ENABLED  = 0x02,
   165 }tenuM2mAteTxDpdControl;
   172         M2M_ATE_TX_GAIN_DYNAMIC = 0x00,
   173         M2M_ATE_TX_GAIN_BYPASS  = 0x01,
   174         M2M_ATE_TX_GAIN_FCC             = 0x02,
   175         M2M_ATE_TX_GAIN_TELEC   = 0x03,
   176 }tenuM2mAteTxGainSetting;
   183         M2M_ATE_PMU_DISBLE      = 0x00,
   184         M2M_ATE_PMU_ENABLE      = 0x01,
   185 }tenuM2mAtePMUSetting;
   192         M2M_ATE_TX_SRC_MAC      = 0x00,
   193         M2M_ATE_TX_SRC_PHY      = 0x01,
   201         M2M_ATE_TX_MODE_NORM    = 0x00,
   202         M2M_ATE_TX_MODE_CW              = 0x01,
   210         M2M_ATE_CHANNEL_1       = 0x01,
   211         M2M_ATE_CHANNEL_2       = 0x02,
   212         M2M_ATE_CHANNEL_3       = 0x03,
   213         M2M_ATE_CHANNEL_4       = 0x04,
   214         M2M_ATE_CHANNEL_5       = 0x05,
   215         M2M_ATE_CHANNEL_6       = 0x06,
   216         M2M_ATE_CHANNEL_7       = 0x07,
   217         M2M_ATE_CHANNEL_8       = 0x08,
   218         M2M_ATE_CHANNEL_9       = 0x09,
   219         M2M_ATE_CHANNEL_10      = 0x0A,
   220         M2M_ATE_CHANNEL_11      = 0x0B,
   221         M2M_ATE_CHANNEL_12      = 0x0C,
   222         M2M_ATE_CHANNEL_13      = 0x0D,
   223         M2M_ATE_CHANNEL_14      = 0x0E,
   240 } tstrM2mAteRxStatus;
   280         uint8     use_efuse_xo_offset;
   283         uint8 peer_mac_addr[6];
   302         uint8     use_efuse_xo_offset;
   305         uint8    self_mac_addr[6];
   308         uint8    sa_mac_addr[6];
   311         uint8    mac_filter_en_da;
   314         uint8    mac_filter_en_sa;
   317         uint8   override_self_mac_addr;
   351 sint8 m2m_ate_deinit(
void);
   381 sint8 m2m_ate_get_fw_state(
void);
   411 sint8 m2m_ate_get_tx_status(
void);
   427 sint8 m2m_ate_start_tx(tstrM2mAteTx *);
   441 sint8 m2m_ate_stop_tx(
void);
   455 sint8 m2m_ate_get_rx_status(
void);
   471 sint8 m2m_ate_start_rx(tstrM2mAteRx *);
   485 sint8 m2m_ate_stop_rx(
void);
   501 sint8 m2m_ate_read_rx_status(tstrM2mAteRxStatus *);
   515 sint8 m2m_ate_set_dig_gain(
double dGaindB);
   529 sint8 m2m_ate_get_dig_gain(
double * pdGaindB);
   571 sint8 m2m_ate_get_tot_gain(
double * pTotGaindB);
   580 #endif //_M2M_ATE_FW_ This module contains common APIs declarations. 
 
signed char sint8
Range of values between -128 to 127. 
 
WINC3400 IoT Application Interface Internal Types. 
 
unsigned short uint16
Range of values between 0 to 65535. 
 
unsigned long uint32
Range of values between 0 to 4294967295. 
 
unsigned char uint8
Range of values between 0 to 255.