m2m_ate_mode.c
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1 
35 #ifdef _M2M_ATE_FW_
36 /*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*
37 INCLUDES
38 *=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
39 #include "driver/include/m2m_ate_mode.h"
40 #include "driver/source/nmasic.h"
41 #include "driver/source/nmdrv.h"
42 #include "m2m_hif.h"
43 #include "driver/source/nmbus.h"
44 #include "bsp/include/nm_bsp.h"
45 
46 /*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*
47 MACROS
48 *=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
49 #define rInterrupt_CORTUS_0 (0x10a8)
50 #define rInterrupt_CORTUS_1 (0x10ac)
51 #define rInterrupt_CORTUS_2 (0x10b0)
52 
53 #define rBurstTx_NMI_TX_RATE (0x161d00)
54 #define rBurstTx_NMI_NUM_TX_FRAMES (0x161d04)
55 #define rBurstTx_NMI_TX_FRAME_LEN (0x161d08)
56 #define rBurstTx_NMI_TX_CW_PARAM (0x161d0c)
57 #define rBurstTx_NMI_TX_GAIN (0x161d10)
58 #define rBurstTx_NMI_TX_DPD_CTRL (0x161d14)
59 #define rBurstTx_NMI_USE_PMU (0x161d18)
60 #define rBurstTx_NMI_TEST_CH (0x161d1c)
61 #define rBurstTx_NMI_TX_PHY_CONT (0x161d20)
62 #define rBurstTx_NMI_TX_CW_MODE (0x161d24)
63 #define rBurstTx_NMI_TEST_XO_OFF (0x161d28)
64 #define rBurstTx_NMI_USE_EFUSE_XO_OFF (0x161d2c)
65 
66 #define rBurstTx_NMI_MAC_FILTER_ENABLE_DA (0x161d30)
67 #define rBurstTx_NMI_MAC_ADDR_LO_PEER (0x161d34)
68 #define rBurstTx_NMI_MAC_ADDR_LO_SELF (0x161d38)
69 #define rBurstTx_NMI_MAC_ADDR_HI_PEER (0x161d3c)
70 #define rBurstTx_NMI_MAC_ADDR_HI_SELF (0x161d40)
71 #define rBurstTx_NMI_RX_PKT_CNT_SUCCESS (0x161d44)
72 #define rBurstTx_NMI_RX_PKT_CNT_FAIL (0x161d48)
73 #define rBurstTx_NMI_SET_SELF_MAC_ADDR (0x161d4c)
74 #define rBurstTx_NMI_MAC_ADDR_LO_SA (0x161d50)
75 #define rBurstTx_NMI_MAC_ADDR_HI_SA (0x161d54)
76 #define rBurstTx_NMI_MAC_FILTER_ENABLE_SA (0x161d58)
77 
78 #define rBurstRx_NMI_RX_ALL_PKTS_CONT (0x9898)
79 #define rBurstRx_NMI_RX_ERR_PKTS_CONT (0x988c)
80 
81 #define TX_DGAIN_MAX_NUM_REGS (4)
82 #define TX_DGAIN_REG_BASE_ADDRESS (0x1240)
83 #define TX_GAIN_CODE_MAX_NUM_REGS (3)
84 #define TX_GAIN_CODE_BASE_ADDRESS (0x1250)
85 #define TX_PA_MAX_NUM_REGS (3)
86 #define TX_PA_BASE_ADDRESS (0x1e58)
87 /*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*
88 VARIABLES
89 *=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
90 volatile static uint8 gu8AteIsRunning = 0;
91 volatile static uint8 gu8RxState = 0;
92 volatile static uint8 gu8TxState = 0;
93 volatile static uint32 gaAteFwTxRates[M2M_ATE_MAX_NUM_OF_RATES] =
94 {
95  0x01, 0x02, 0x05, 0x0B, /*B-Rats*/
96  0x06, 0x09, 0x0C, 0x12, 0x18, 0x24, 0x30, 0x36, /*G-Rats*/
97  0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87 /*N-Rats*/
98 };
99 
100 
101 /*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*
102 STATIC FUNCTIONS
103 *=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
104 static void m2m_ate_set_rx_status(uint8 u8Value)
105 {
106  gu8RxState = u8Value;
107 }
108 
109 static void m2m_ate_set_tx_status(uint8 u8Value)
110 {
111  gu8TxState = u8Value;
112 }
113 
114 /*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*
115 FUNCTION IMPLEMENTATION
116 *=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
127 sint8 m2m_ate_init(uint32 req_serial_number)
128 {
129  sint8 s8Ret = M2M_SUCCESS;
130  uint8 u8WifiMode = M2M_WIFI_MODE_CONFIG;
131 
132  s8Ret = nm_drv_init(&u8WifiMode, req_serial_number);
133 
134  return s8Ret;
135 }
136 
147 sint8 m2m_ate_deinit(void)
148 {
149  return nm_drv_deinit(NULL);
150 }
151 
166 sint8 m2m_ate_set_fw_state(uint8 u8State)
167 {
168  sint8 s8Ret = M2M_SUCCESS;
169  uint32_t u32Val = 0;
170 
171  if((M2M_ATE_FW_STATE_STOP == u8State) && (M2M_ATE_FW_STATE_STOP != gu8AteIsRunning))
172  {
173  u32Val = nm_read_reg(rNMI_GLB_RESET);
174  u32Val &= ~(1 << 10);
175  s8Ret = nm_write_reg(rNMI_GLB_RESET, u32Val);
176  gu8AteIsRunning = M2M_ATE_FW_STATE_STOP;
177  }
178  else if((M2M_ATE_FW_STATE_RUN == u8State) && (M2M_ATE_FW_STATE_RUN != gu8AteIsRunning))
179  {
180  /* 0x1118[0]=0 at power-on-reset: pad-based control. */
181  /* Switch cortus reset register to register control. 0x1118[0]=1. */
182  u32Val = nm_read_reg(rNMI_BOOT_RESET_MUX);
183  u32Val |= (1 << 0);
184  s8Ret = nm_write_reg(rNMI_BOOT_RESET_MUX, u32Val);
185  if(M2M_SUCCESS != s8Ret)
186  {
187  goto __EXIT;
188  }
194  s8Ret = nm_write_reg(0xc0000, 0x71);
195  if(M2M_SUCCESS != s8Ret)
196  {
197  goto __EXIT;
198  }
199 
200  u32Val = nm_read_reg(rNMI_GLB_RESET);
201  if((u32Val & (1ul << 10)) == (1ul << 10))
202  {
203  u32Val &= ~(1ul << 10);
204  s8Ret = nm_write_reg(rNMI_GLB_RESET, u32Val);
205  if(M2M_SUCCESS != s8Ret)
206  {
207  goto __EXIT;
208  }
209  }
210 
211  u32Val |= (1ul << 10);
212  s8Ret = nm_write_reg(rNMI_GLB_RESET, u32Val);
213  if(M2M_SUCCESS != s8Ret)
214  {
215  goto __EXIT;
216  }
217  gu8AteIsRunning = M2M_ATE_FW_STATE_RUN;
218  }
219  else
220  {
221  s8Ret = M2M_ATE_ERR_UNHANDLED_CASE;
222  }
223 
224 __EXIT:
225  if((M2M_SUCCESS == s8Ret) && (M2M_ATE_FW_STATE_RUN == gu8AteIsRunning))
226  {
227  nm_bsp_sleep(500); /*wait for ATE firmware start up*/
228  }
229  return s8Ret;
230 }
231 
244 sint8 m2m_ate_get_fw_state(void)
245 {
246  return gu8AteIsRunning;
247 }
248 
263 uint32 m2m_ate_get_tx_rate(uint8 u8Index)
264 {
265  if(M2M_ATE_MAX_NUM_OF_RATES <= u8Index)
266  {
267  return 0;
268  }
269  return gaAteFwTxRates[u8Index];
270 }
271 
284 sint8 m2m_ate_get_tx_status(void)
285 {
286  return gu8TxState;
287 }
288 
303 sint8 m2m_ate_start_tx(tstrM2mAteTx * strM2mAteTx)
304 {
305  sint8 s8Ret = M2M_SUCCESS;
306  uint8 u8LoopCntr = 0;
307  uint32_t val32;
308 
309 
310  if(NULL == strM2mAteTx)
311  {
312  s8Ret = M2M_ATE_ERR_VALIDATE;
313  goto __EXIT;
314  }
315 
316  if(0 != m2m_ate_get_tx_status())
317  {
318  s8Ret = M2M_ATE_ERR_TX_ALREADY_RUNNING;
319  goto __EXIT;
320  }
321 
322  if(0 != m2m_ate_get_rx_status())
323  {
324  s8Ret = M2M_ATE_ERR_RX_ALREADY_RUNNING;
325  goto __EXIT;
326  }
327 
328  if( (strM2mAteTx->channel_num < M2M_ATE_CHANNEL_1) ||
329  (strM2mAteTx->channel_num > M2M_ATE_CHANNEL_14) ||
330  (strM2mAteTx->tx_gain_sel < M2M_ATE_TX_GAIN_DYNAMIC) ||
331  (strM2mAteTx->tx_gain_sel > M2M_ATE_TX_GAIN_TELEC) ||
332  (strM2mAteTx->frame_len > M2M_ATE_MAX_FRAME_LENGTH) ||
333  (strM2mAteTx->frame_len < M2M_ATE_MIN_FRAME_LENGTH)
334  )
335  {
336  s8Ret = M2M_ATE_ERR_VALIDATE;
337  goto __EXIT;
338  }
339 
340  if( (strM2mAteTx->duty_cycle < M2M_ATE_TX_DUTY_MAX_VALUE /*1*/) ||
341  (strM2mAteTx->duty_cycle > M2M_ATE_TX_DUTY_MIN_VALUE /*10*/ ) ||
342  (strM2mAteTx->dpd_ctrl < M2M_ATE_TX_DPD_DYNAMIC) ||
343  (strM2mAteTx->dpd_ctrl > M2M_ATE_TX_DPD_ENABLED) ||
344  (strM2mAteTx->use_pmu < M2M_ATE_PMU_DISBLE) ||
345  (strM2mAteTx->use_pmu > M2M_ATE_PMU_ENABLE) ||
346  (strM2mAteTx->phy_burst_tx < M2M_ATE_TX_SRC_MAC) ||
347  (strM2mAteTx->phy_burst_tx > M2M_ATE_TX_SRC_PHY) ||
348  (strM2mAteTx->cw_tx < M2M_ATE_TX_MODE_NORM) ||
349  (strM2mAteTx->cw_tx > M2M_ATE_TX_MODE_CW)
350  )
351  {
352  s8Ret = M2M_ATE_ERR_VALIDATE;
353  goto __EXIT;
354  }
355 
356  for(u8LoopCntr=0; u8LoopCntr<M2M_ATE_MAX_NUM_OF_RATES; u8LoopCntr++)
357  {
358  if(gaAteFwTxRates[u8LoopCntr] == strM2mAteTx->data_rate)
359  {
360  break;
361  }
362  }
363 
364  if(M2M_ATE_MAX_NUM_OF_RATES == u8LoopCntr)
365  {
366  s8Ret = M2M_ATE_ERR_VALIDATE;
367  goto __EXIT;
368  }
369 
370 
371 
372  s8Ret += nm_write_reg(rBurstTx_NMI_USE_PMU, strM2mAteTx->use_pmu);
373  s8Ret += nm_write_reg(rBurstTx_NMI_TX_PHY_CONT, strM2mAteTx->phy_burst_tx);
374  s8Ret += nm_write_reg(rBurstTx_NMI_NUM_TX_FRAMES, strM2mAteTx->num_frames);
375  s8Ret += nm_write_reg(rBurstTx_NMI_TX_GAIN, strM2mAteTx->tx_gain_sel);
376  s8Ret += nm_write_reg(rBurstTx_NMI_TEST_CH, strM2mAteTx->channel_num);
377  s8Ret += nm_write_reg(rBurstTx_NMI_TX_FRAME_LEN, strM2mAteTx->frame_len);
378  s8Ret += nm_write_reg(rBurstTx_NMI_TX_CW_PARAM, strM2mAteTx->duty_cycle);
379  s8Ret += nm_write_reg(rBurstTx_NMI_TX_DPD_CTRL, strM2mAteTx->dpd_ctrl);
380  s8Ret += nm_write_reg(rBurstTx_NMI_TX_RATE, strM2mAteTx->data_rate);
381  s8Ret += nm_write_reg(rBurstTx_NMI_TX_CW_MODE, strM2mAteTx->cw_tx);
382  s8Ret += nm_write_reg(rBurstTx_NMI_TEST_XO_OFF, strM2mAteTx->xo_offset_x1000);
383  s8Ret += nm_write_reg(rBurstTx_NMI_USE_EFUSE_XO_OFF, strM2mAteTx->use_efuse_xo_offset);
384 
385  val32 = strM2mAteTx->peer_mac_addr[5] << 0;
386  val32 |= strM2mAteTx->peer_mac_addr[4] << 8;
387  val32 |= strM2mAteTx->peer_mac_addr[3] << 16;
388  nm_write_reg(rBurstTx_NMI_MAC_ADDR_LO_PEER, val32 );
389 
390  val32 = strM2mAteTx->peer_mac_addr[2] << 0;
391  val32 |= strM2mAteTx->peer_mac_addr[1] << 8;
392  val32 |= strM2mAteTx->peer_mac_addr[0] << 16;
393  nm_write_reg(rBurstTx_NMI_MAC_ADDR_HI_PEER, val32 );
394 
395  if(M2M_SUCCESS == s8Ret)
396  {
397  s8Ret += nm_write_reg(rInterrupt_CORTUS_0, 1); /*Interrupt Cortus*/
398  m2m_ate_set_tx_status(1);
399  nm_bsp_sleep(200); /*Recommended*/
400  }
401 
402 __EXIT:
403  return s8Ret;
404 }
405 
418 sint8 m2m_ate_stop_tx(void)
419 {
420  sint8 s8Ret = M2M_SUCCESS;
421 
422  s8Ret = nm_write_reg(rInterrupt_CORTUS_1, 1);
423  if(M2M_SUCCESS == s8Ret)
424  {
425  m2m_ate_set_tx_status(0);
426  }
427 
428  return s8Ret;
429 }
430 
443 sint8 m2m_ate_get_rx_status(void)
444 {
445  return gu8RxState;
446 }
447 
462 sint8 m2m_ate_start_rx(tstrM2mAteRx * strM2mAteRxStr)
463 {
464  sint8 s8Ret = M2M_SUCCESS;
465  uint32 val32;
466  if(NULL == strM2mAteRxStr)
467  {
468  s8Ret = M2M_ATE_ERR_VALIDATE;
469  goto __EXIT;
470  }
471 
472  if(0 != m2m_ate_get_tx_status())
473  {
474  s8Ret = M2M_ATE_ERR_TX_ALREADY_RUNNING;
475  goto __EXIT;
476  }
477 
478  if(0 != m2m_ate_get_rx_status())
479  {
480  s8Ret = M2M_ATE_ERR_RX_ALREADY_RUNNING;
481  goto __EXIT;
482  }
483 
484  if( (strM2mAteRxStr->channel_num < M2M_ATE_CHANNEL_1) ||
485  (strM2mAteRxStr->channel_num > M2M_ATE_CHANNEL_14)||
486  (strM2mAteRxStr->use_pmu < M2M_ATE_PMU_DISBLE) ||
487  (strM2mAteRxStr->use_pmu > M2M_ATE_PMU_ENABLE)
488  )
489  {
490  s8Ret = M2M_ATE_ERR_VALIDATE;
491  goto __EXIT;
492  }
493 
494  s8Ret += nm_write_reg(rBurstTx_NMI_TEST_CH, strM2mAteRxStr->channel_num);
495  s8Ret += nm_write_reg(rBurstTx_NMI_USE_PMU, strM2mAteRxStr->use_pmu);
496  s8Ret += nm_write_reg(rBurstTx_NMI_TEST_XO_OFF, strM2mAteRxStr->xo_offset_x1000);
497  s8Ret += nm_write_reg(rBurstTx_NMI_USE_EFUSE_XO_OFF, strM2mAteRxStr->use_efuse_xo_offset);
498 
499  if(strM2mAteRxStr->override_self_mac_addr)
500  {
501  val32 = strM2mAteRxStr->self_mac_addr[5] << 0;
502  val32 |= strM2mAteRxStr->self_mac_addr[4] << 8;
503  val32 |= strM2mAteRxStr->self_mac_addr[3] << 16;
504  nm_write_reg(rBurstTx_NMI_MAC_ADDR_LO_SELF, val32 );
505 
506  val32 = strM2mAteRxStr->self_mac_addr[2] << 0;
507  val32 |= strM2mAteRxStr->self_mac_addr[1] << 8;
508  val32 |= strM2mAteRxStr->self_mac_addr[0] << 16;
509  nm_write_reg(rBurstTx_NMI_MAC_ADDR_HI_SELF, val32 );
510  }
511 
512  if(strM2mAteRxStr->mac_filter_en_sa)
513  {
514  val32 = strM2mAteRxStr->sa_mac_addr[5] << 0;
515  val32 |= strM2mAteRxStr->sa_mac_addr[4] << 8;
516  val32 |= strM2mAteRxStr->sa_mac_addr[3] << 16;
517  nm_write_reg(rBurstTx_NMI_MAC_ADDR_LO_SA, val32 );
518 
519  val32 = strM2mAteRxStr->sa_mac_addr[2] << 0;
520  val32 |= strM2mAteRxStr->sa_mac_addr[1] << 8;
521  val32 |= strM2mAteRxStr->sa_mac_addr[0] << 16;
522  nm_write_reg(rBurstTx_NMI_MAC_ADDR_HI_SA, val32 );
523  }
524 
525  nm_write_reg(rBurstTx_NMI_MAC_FILTER_ENABLE_DA, strM2mAteRxStr->mac_filter_en_da);
526  nm_write_reg(rBurstTx_NMI_MAC_FILTER_ENABLE_SA, strM2mAteRxStr->mac_filter_en_sa);
527  nm_write_reg(rBurstTx_NMI_SET_SELF_MAC_ADDR, strM2mAteRxStr->override_self_mac_addr);
528 
529  if(M2M_SUCCESS == s8Ret)
530  {
531  s8Ret += nm_write_reg(rInterrupt_CORTUS_2, 1); /*Interrupt Cortus*/
532  m2m_ate_set_rx_status(1);
533  nm_bsp_sleep(10); /*Recommended*/
534  }
535 
536 __EXIT:
537  return s8Ret;
538 }
539 
552 sint8 m2m_ate_stop_rx(void)
553 {
554  m2m_ate_set_rx_status(0);
555  nm_bsp_sleep(200); /*Recommended*/
556  return M2M_SUCCESS;
557 }
558 
573 sint8 m2m_ate_read_rx_status(tstrM2mAteRxStatus *strM2mAteRxStatus)
574 {
575  sint8 s8Ret = M2M_SUCCESS;
576 
577  if(NULL == strM2mAteRxStatus)
578  {
579  s8Ret = M2M_ATE_ERR_VALIDATE;
580  goto __EXIT;
581  }
582 
583  if(0 != m2m_ate_get_tx_status())
584  {
585  s8Ret = M2M_ATE_ERR_TX_ALREADY_RUNNING;
586  goto __EXIT;
587  }
588 
589  if (nm_read_reg(rBurstTx_NMI_MAC_FILTER_ENABLE_DA) || nm_read_reg(rBurstTx_NMI_MAC_FILTER_ENABLE_SA))
590  {
591  strM2mAteRxStatus->num_rx_pkts = nm_read_reg(rBurstTx_NMI_RX_PKT_CNT_SUCCESS) + nm_read_reg(rBurstTx_NMI_RX_PKT_CNT_FAIL);
592  strM2mAteRxStatus->num_good_pkts = nm_read_reg(rBurstTx_NMI_RX_PKT_CNT_SUCCESS);
593  strM2mAteRxStatus->num_err_pkts = nm_read_reg(rBurstTx_NMI_RX_PKT_CNT_FAIL);
594  }
595  else
596  {
597  strM2mAteRxStatus->num_rx_pkts = nm_read_reg(rBurstRx_NMI_RX_ALL_PKTS_CONT) + nm_read_reg(0x989c);
598  strM2mAteRxStatus->num_err_pkts = nm_read_reg(rBurstRx_NMI_RX_ERR_PKTS_CONT);
599  strM2mAteRxStatus->num_good_pkts = strM2mAteRxStatus->num_rx_pkts - strM2mAteRxStatus->num_err_pkts;
600  }
601 
602 __EXIT:
603  return s8Ret;
604 }
617 sint8 m2m_ate_set_dig_gain(double dGaindB)
618 {
619  uint32_t dGain, val32;
620  dGain = (uint32_t)(pow(10, dGaindB/20.0) * 1024.0);
621 
622  val32 = nm_read_reg(0x160cd0);
623  val32 &= ~(0x1ffful << 0);
624  val32 |= (((uint32_t)dGain) << 0);
625  nm_write_reg(0x160cd0, val32);
626  return M2M_SUCCESS;
627 }
640 sint8 m2m_ate_get_dig_gain(double * pdGaindB)
641 {
642  uint32 dGain, val32;
643 
644  if(!pdGaindB) return M2M_ERR_INVALID_ARG;
645 
646  val32 = nm_read_reg(0x160cd0);
647 
648  dGain = (val32 >> 0) & 0x1ffful;
649  *pdGaindB = 20.0*log10((double)dGain / 1024.0);
650 
651  return M2M_SUCCESS;
652 }
665 sint8 m2m_ate_get_pa_gain(uint32 *paGain)
666 {
667  uint32 val32;
668 
669  if(!paGain)
670  return M2M_ERR_INVALID_ARG;
671 
672  val32 = nm_read_reg(0x1e9c);
673 
674  * paGain = (val32 >> 8) & 0x3f;
675 
676  return M2M_SUCCESS;
677 }
690 sint8 m2m_ate_get_ppa_gain(uint32 * ppaGain)
691 {
692  uint32 val32;
693 
694  if(!ppaGain) return M2M_ERR_INVALID_ARG;
695 
696  val32 = nm_read_reg(0x1ea0);
697 
698  * ppaGain = (val32 >> 5) & 0x7;
699 
700  return M2M_SUCCESS;
701 }
714 sint8 m2m_ate_get_tot_gain(double * pTotGaindB)
715 {
716  double totGaindB, dGaindB;
717  uint32 paGain,ppaGain,m_cmbPAGainStep,m_cmbPPAGainStep;
718 
719 
720  m2m_ate_get_pa_gain(&paGain);
721  m2m_ate_get_ppa_gain(&ppaGain);
722  m2m_ate_get_dig_gain(&dGaindB);
723 
724  switch(paGain){
725  case 0x1:
726  m_cmbPAGainStep = 5;
727  break;
728  case 0x3:
729  m_cmbPAGainStep = 4;
730  break;
731  case 0x7:
732  m_cmbPAGainStep = 3;
733  break;
734  case 0xf:
735  m_cmbPAGainStep = 2;
736  break;
737  case 0x1f:
738  m_cmbPAGainStep = 1;
739  break;
740  case 0x3f:
741  m_cmbPAGainStep = 0;
742  break;
743  default:
744  m_cmbPAGainStep = 0;
745  break;
746  }
747 
748 
749  switch(ppaGain){
750  case 0x1:
751  m_cmbPPAGainStep = 2;
752  break;
753  case 0x3:
754  m_cmbPPAGainStep = 1;
755  break;
756  case 0x7:
757  m_cmbPPAGainStep = 0;
758  break;
759  default:
760  m_cmbPPAGainStep = 3;
761  break;
762  }
763 
764  totGaindB = dGaindB + 18 - m_cmbPAGainStep*3;
765  totGaindB += 9 - m_cmbPPAGainStep*3;
766 
767  *pTotGaindB = totGaindB;
768 
769  return M2M_SUCCESS;
770 }
771 #endif //_M2M_ATE_FW_
sint8
signed char sint8
Range of values between -128 to 127.
Definition: nm_bsp.h:111
nmdrv.h
This module contains WINC3400 M2M driver APIs declarations.
rNMI_BOOT_RESET_MUX
#define rNMI_BOOT_RESET_MUX
Definition: nmasic.h:44
M2M_SUCCESS
#define M2M_SUCCESS
Definition: nm_common.h:51
NULL
#define NULL
Definition: nm_bsp.h:52
m2m_ate_mode.h
WINC3400 Peripherals Application Interface.
nmasic.h
This module contains WINC3400 ASIC specific internal APIs.
nm_bsp_sleep
void nm_bsp_sleep(uint32 u32TimeMsec)
Definition: nm_bsp_same70.c:117
nm_write_reg
sint8 nm_write_reg(uint32 u32Addr, uint32 u32Val)
Definition: nmbus.c:155
rNMI_GLB_RESET
#define rNMI_GLB_RESET
Definition: nmasic.h:43
M2M_ERR_INVALID_ARG
#define M2M_ERR_INVALID_ARG
Definition: nm_common.h:69
nmbus.h
This module contains WINC3400 bus APIs implementation.
nm_drv_deinit
sint8 nm_drv_deinit(void *arg)
Definition: nmdrv.c:370
nm_drv_init
sint8 nm_drv_init(void *arg, uint32 req_serial_number)
Definition: nmdrv.c:351
uint32
unsigned long uint32
Range of values between 0 to 4294967295.
Definition: nm_bsp.h:103
nm_bsp.h
This module contains WINC3400 BSP APIs declarations.
uint8
unsigned char uint8
Range of values between 0 to 255.
Definition: nm_bsp.h:89
M2M_WIFI_MODE_CONFIG
Definition: m2m_types.h:971
m2m_hif.h
This module contains M2M host interface APIs implementation.
nm_read_reg
uint32 nm_read_reg(uint32 u32Addr)
Definition: nmbus.c:104

inertial_sense_ros
Author(s):
autogenerated on Sun Feb 28 2021 03:17:57