Type definitions and defines for Cortex-M processor based devices. More...
Collaboration diagram for Defines and Type Definitions:
|
Modules | |
| Status and Control Registers | |
| Core Register type definitions. | |
| Nested Vectored Interrupt Controller (NVIC) | |
| Type definitions for the NVIC Registers. | |
| System Control Block (SCB) | |
| Type definitions for the System Control Block Registers. | |
| System Controls not in SCB (SCnSCB) | |
| Type definitions for the System Control and ID Register not in the SCB. | |
| System Tick Timer (SysTick) | |
| Type definitions for the System Timer Registers. | |
| Instrumentation Trace Macrocell (ITM) | |
| Type definitions for the Instrumentation Trace Macrocell (ITM) | |
| Data Watchpoint and Trace (DWT) | |
| Type definitions for the Data Watchpoint and Trace (DWT) | |
| Trace Port Interface (TPI) | |
| Type definitions for the Trace Port Interface (TPI) | |
| Core Debug Registers (CoreDebug) | |
| Type definitions for the Core Debug Registers. | |
| Core Definitions | |
| Definitions for base addresses, unions, and structures. | |
Detailed Description
Type definitions and defines for Cortex-M processor based devices.