conf_mcan.h
Go to the documentation of this file.
1 
33 /*
34  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
35  */
36 #ifndef CONF_MCAN_H_INCLUDED
37 #define CONF_MCAN_H_INCLUDED
38 
39 /*
40  * Below is the message RAM setting, it will be stored in the system RAM.
41  * Please adjust the message size according to your application.
42  */
44 #define CONF_MCAN0_RX_FIFO_0_NUM 16
45 
46 #define CONF_MCAN0_RX_FIFO_1_NUM 16
47 
48 #define CONF_MCAN0_RX_BUFFER_NUM 16
49 
50 #define CONF_MCAN0_TX_BUFFER_NUM 4
51 
52 #define CONF_MCAN0_TX_FIFO_QUEUE_NUM 4
53 
54 #define CONF_MCAN0_TX_EVENT_FIFO 8
55 
56 #define CONF_MCAN0_RX_STANDARD_ID_FILTER_NUM 32
57 
58 #define CONF_MCAN0_RX_EXTENDED_ID_FILTER_NUM 16
59 
60 #define CONF_MCAN1_RX_FIFO_0_NUM 16
61 
62 #define CONF_MCAN1_RX_FIFO_1_NUM 16
63 
64 #define CONF_MCAN1_RX_BUFFER_NUM 0 //16
65 
66 #define CONF_MCAN1_TX_BUFFER_NUM 0
67 
68 #define CONF_MCAN1_TX_FIFO_QUEUE_NUM 8
69 
70 #define CONF_MCAN1_TX_EVENT_FIFO 8
71 
72 #define CONF_MCAN1_RX_STANDARD_ID_FILTER_NUM 32
73 
74 #define CONF_MCAN1_RX_EXTENDED_ID_FILTER_NUM 16
75 
77 #define CONF_MCAN_ELEMENT_DATA_SIZE 8
78 
86 #define CONF_MCAN_NBTP_NBRP_VALUE 1
87 
88 #define CONF_MCAN_NBTP_NSJW_VALUE 3
89 
90 #define CONF_MCAN_NBTP_NTSEG1_VALUE 10
91 
92 #define CONF_MCAN_NBTP_NTSEG2_VALUE 7
93 
94 /*
95  * The setting of the data bit rate is based on the GCLK_MCAN is 48M which you can
96  * change in the conf_clock.h. Below is the default configuration. The
97  * time quanta is 48MHz / (5+1) = 8MHz. And each bit is (1 + FTSEG1 + 1 + FTSEG2 + 1) = 16 time
98  * quanta which means the bit rate is 8MHz/16=500KHz.
99  */
101 #define CONF_MCAN_FBTP_FBRP_VALUE 5
102 
103 #define CONF_MCAN_FBTP_FSJW_VALUE 3
104 
105 #define CONF_MCAN_FBTP_FTSEG1_VALUE 10
106 
107 #define CONF_MCAN_FBTP_FTSEG2_VALUE 3
108 
109 #endif


inertial_sense_ros
Author(s):
autogenerated on Sun Feb 28 2021 03:17:57