sensor_epsonV340.h
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1 //==============================================================================
2 //
3 // sensor_epsonV340.h - Epson V340 sensor specific definitions
4 //
5 //
6 // THE SOFTWARE IS RELEASED INTO THE PUBLIC DOMAIN.
7 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
8 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
9 // NONINFRINGEMENT, SECURITY, SATISFACTORY QUALITY, AND FITNESS FOR A
10 // PARTICULAR PURPOSE. IN NO EVENT SHALL EPSON BE LIABLE FOR ANY LOSS, DAMAGE
11 // OR CLAIM, ARISING FROM OR IN CONNECTION WITH THE SOFTWARE OR THE USE OF THE
12 // SOFTWARE.
13 //
14 //==============================================================================
15 #ifndef EPSONV340_H_
16 #define EPSONV340_H_
17 
18 #define EPSON_ACCL_SF (.180)
19 #define EPSON_GYRO_SF (.015)
20 #define EPSON_TEMP_SF (-0.0053964)
21 #define EPSON_ATTI_SF (0.0)
22 #define EPSON_COUNT_SF (21333)
23 
24 #define EPSON_DA_SF0 (0.0)
25 #define EPSON_DA_SF1 (0.0)
26 #define EPSON_DA_SF2 (0.0)
27 #define EPSON_DA_SF3 (0.0)
28 #define EPSON_DA_SF4 (0.0)
29 #define EPSON_DA_SF5 (0.0)
30 #define EPSON_DA_SF6 (0.0)
31 #define EPSON_DA_SF7 (0.0)
32 #define EPSON_DA_SF8 (0.0)
33 #define EPSON_DA_SF9 (0.0)
34 #define EPSON_DA_SF10 (0.0)
35 #define EPSON_DA_SF11 (0.0)
36 #define EPSON_DA_SF12 (0.0)
37 #define EPSON_DA_SF13 (0.0)
38 #define EPSON_DA_SF14 (0.0)
39 #define EPSON_DA_SF15 (0.0)
40 
41 #define EPSON_DV_SF0 (0.0)
42 #define EPSON_DV_SF1 (0.0)
43 #define EPSON_DV_SF2 (0.0)
44 #define EPSON_DV_SF3 (0.0)
45 #define EPSON_DV_SF4 (0.0)
46 #define EPSON_DV_SF5 (0.0)
47 #define EPSON_DV_SF6 (0.0)
48 #define EPSON_DV_SF7 (0.0)
49 #define EPSON_DV_SF8 (0.0)
50 #define EPSON_DV_SF9 (0.0)
51 #define EPSON_DV_SF10 (0.0)
52 #define EPSON_DV_SF11 (0.0)
53 #define EPSON_DV_SF12 (0.0)
54 #define EPSON_DV_SF13 (0.0)
55 #define EPSON_DV_SF14 (0.0)
56 #define EPSON_DV_SF15 (0.0)
57 
58 /* -- Commands --
59 - ADDR_ address byte of transfer to select the register to access
60 - CMD_ data byte of transfer to write to the register selected
61 
62 - All accesses are 16 bit transfers
63 - For SPI IF:
64  - For SPI write accesses - 8-bit address with msb=1b (can be even or
65  odd) + 8-bit write
66 data
67  - No response
68  - For SPI read accesses - 8-bit address with msb=0b(even only) + 8-bit
69  dummy data
70  - Response is
71 transferred on MOSI on next SPI access
72  - Return value is
73 16-bit read data (high byte + low byte)
74 - For UART IF:
75  - For UART write accesses - 8-bit address with msb=1b(can be even or
76  odd) + 8-bit write data + Delimiter Byte
77  - No response
78  - For UART read accesses - 8-bit address with msb=0b(even only) + 8-bit
79  dummy data + Delimiter Byte
80  - Response is
81 transferred immediately
82  - Return value
83 consists of Register Read Address + 16-bit read data (high byte + low byte) +
84 Delimiter Byte
85 
86 - NOTE: Register Address Maps that depend on the WINDOW_ID (page) */
87 
88 // WINDOW_ID 0 (This is for compatibility with other IMUS, WINDOW_ID is not used
89 // by G350)
90 #define ADDR_FLAG 0x00 // FLAG(ND/EA) (W0)
91 #define ADDR_TEMP_LOW 0x02 // TEMPC Byte0 (W0)
92 #define ADDR_TEMP_HIGH 0x02 // TEMPC Byte1 (W0)
93 #define ADDR_XGYRO_HIGH 0x04 // XGYRO Byte0 (W0)
94 #define ADDR_XGYRO_LOW 0x04 // XGYRO Byte1 (W0)
95 #define ADDR_YGYRO_HIGH 0x06 // YGYRO Byte0 (W0)
96 #define ADDR_YGYRO_LOW 0x06 // YGYRO Byte1 (W0)
97 #define ADDR_ZGYRO_HIGH 0x08 // ZGYRO Byte0 (W0)
98 #define ADDR_ZGYRO_LOW 0x08 // ZGYRO Byte1 (W0)
99 #define ADDR_XACCL_HIGH 0x0A // XACCL Byte0 (W0)
100 #define ADDR_XACCL_LOW 0x0A // XACCL Byte1 (W0)
101 #define ADDR_YACCL_HIGH 0x0C // YACCL Byte0 (W0)
102 #define ADDR_YACCL_LOW 0x0C // YACCL Byte1 (W0)
103 #define ADDR_ZACCL_HIGH 0x0E // ZACCL Byte0 (W0)
104 #define ADDR_ZACCL_LOW 0x0E // ZACCL Byte1 (W0)
105 #define ADDR_GPIO 0x10 // GPIO (W0)
106 #define ADDR_COUNT 0x12 // COUNT (W0)
107 #define ADDR_SIG_CTRL_LO 0x32 // SIG_CTRL Byte0 (W0)
108 #define ADDR_POL_CTRL_LO \
109  0x32 // This is mirror of SIG_CTRL Byte0 (W0) for compatibility for other IMU
110  // models
111 #define ADDR_SIG_CTRL_HI 0x33 // SIG_CTRL Byte1 (W0)
112 #define ADDR_MSC_CTRL_LO 0x34 // MSC_CTRL Byte0 (W0)
113 #define ADDR_MSC_CTRL_HI 0x35 // MSC_CTRL Byte1 (W0)
114 #define ADDR_SMPL_CTRL_LO 0x36 // SMPL_CTRL Byte0 (W0)
115 #define ADDR_SMPL_CTRL_HI 0x37 // SMPL_CTRL Byte1 (W0)
116 #define ADDR_FILTER_CTRL_LO 0x38 // FILTER_CTRL Byte0 (W0)
117 #define ADDR_MODE_CTRL_LO 0x38 // MODE_CTRL Byte0 (W0)
118 #define ADDR_MODE_CTRL_HI 0x39 // MODE_CTRL Byte1 (W0)
119 #define ADDR_UART_CTRL_LO 0x3A // UART_CTRL Byte0 (W0)
120 #define ADDR_UART_CTRL_HI 0x3B // UART_CTRL Byte1 (W0)
121 #define ADDR_DIAG_STAT 0x3C // DIAG_STAT Byte0 (W0)
122 #define ADDR_GLOB_CMD_LO 0x3E // GLOB_CMD Byte0 (W0)
123 #define ADDR_GLOB_CMD_HI 0x3F // GLOB_CMD Byte1 (W0)
124 #define ADDR_COUNT_CTRL_LO 0x50 // COUNT_CTRL Byte0 (W0)
125 
126 #define ADDR_PROD_ID1 0x6A // PROD_ID1(W0)
127 #define ADDR_PROD_ID2 0x6C // PROD_ID2(W0)
128 #define ADDR_PROD_ID3 0x6E // PROD_ID3(W0)
129 #define ADDR_PROD_ID4 0x70 // PROD_ID4(W0)
130 #define ADDR_VERSION 0x72 // VERSION(W0)
131 #define ADDR_SERIAL_NUM1 0x74 // SERIAL_NUM1(W0)
132 #define ADDR_SERIAL_NUM2 0x76 // SERIAL_NUM2(W0)
133 #define ADDR_SERIAL_NUM3 0x78 // SERIAL_NUM3(W0)
134 #define ADDR_SERIAL_NUM4 0x7A // SERIAL_NUM4(W0)
135 
136 #define ADDR_WIN_CTRL 0x7E // This is for compatibility for other IMU models
137 
138 #define CMD_BURST 0x20 // BURST
139 #define CMD_WINDOW0 0x00 // Write value for WIN_CTRL to change to Window 0
140 #define CMD_WINDOW1 0x01 // Write value for WIN_CTRL to change to Window 1
141 #define CMD_BEGIN_SAMPLING \
142  0x01 // Write value for MODE_CMD_HI to begin sampling
143 #define CMD_END_SAMPLING 0x02 // Write value for MODE_CMD_HI to stop sampling
144 #define CMD_SOFTRESET \
145  0x80 // Write value for GLOB_CMD_LO to issue Software Reset
146 #define CMD_FLASHTEST 0x08 // Write value for MSC_CTRL_HI to issue Flashtest
147 #define CMD_SELFTEST 0x04 // Write value for MSC_CTRL_HI to issue Selftest
148 
149 // Write values for ADDR_SMPL_CTRL_HI to set Output Rate
150 #define CMD_RATE1000 0x01 // TAP>=1
151 #define CMD_RATE500 0x02 // TAP>=2
152 #define CMD_RATE250 0x03 // TAP>=4
153 #define CMD_RATE125 0x04 // TAP>=8
154 #define CMD_RATE62_5 0x05 // TAP>=16
155 #define CMD_RATE31_25 0x06 // TAP>=32
156 
157 // Write values for FILTER_CTRL_LO to set Filter
158 #define CMD_FLTAP1 0x02
159 #define CMD_FLTAP2 0x03
160 #define CMD_FLTAP4 0x04
161 #define CMD_FLTAP8 0x05
162 #define CMD_FLTAP16 0x06
163 #define CMD_FLTAP32 0x07
164 
165 // MODE STAT
166 #define VAL_SAMPLING_MODE 0x00
167 #define VAL_CONFIG_MODE 0x04
168 
169 #endif /* EPSONV340_H_ */

ess_imu_ros1_uart_driver
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autogenerated on Sun Jun 4 2023 02:59:29