stm32h7xx_hal_ospi.c
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1 
260 /* Includes ------------------------------------------------------------------*/
261 #include "stm32h7xx_hal.h"
262 
263 #if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2)
264 
274 #ifdef HAL_OSPI_MODULE_ENABLED
275 
279 /* Private typedef -----------------------------------------------------------*/
280 
281 /* Private define ------------------------------------------------------------*/
282 #define OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000)
283 #define OSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)OCTOSPI_CR_FMODE_0)
284 #define OSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)OCTOSPI_CR_FMODE_1)
285 #define OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)OCTOSPI_CR_FMODE)
287 #define OSPI_CFG_STATE_MASK 0x00000004U
288 #define OSPI_BUSY_STATE_MASK 0x00000008U
289 
290 #define OSPI_NB_INSTANCE 2U
291 #define OSPI_IOM_NB_PORTS 2U
292 #define OSPI_IOM_PORT_MASK 0x1U
293 
294 /* Private macro -------------------------------------------------------------*/
295 #define IS_OSPI_FUNCTIONAL_MODE(MODE) (((MODE) == OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
296  ((MODE) == OSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \
297  ((MODE) == OSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \
298  ((MODE) == OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
299 
300 /* Private variables ---------------------------------------------------------*/
301 
302 /* Private function prototypes -----------------------------------------------*/
303 static void OSPI_DMACplt (MDMA_HandleTypeDef *hmdma);
304 static void OSPI_DMAError (MDMA_HandleTypeDef *hmdma);
305 static void OSPI_DMAAbortCplt (MDMA_HandleTypeDef *hmdma);
306 static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State,
307  uint32_t Tickstart, uint32_t Timeout);
308 static HAL_StatusTypeDef OSPI_ConfigCmd (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
309 static HAL_StatusTypeDef OSPIM_GetConfig (uint8_t instance_nb, OSPIM_CfgTypeDef *cfg);
314 /* Exported functions --------------------------------------------------------*/
315 
342 HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi)
343 {
344  HAL_StatusTypeDef status = HAL_OK;
345  uint32_t tickstart = HAL_GetTick();
346 
347  /* Check the OSPI handle allocation */
348  if (hospi == NULL)
349  {
350  status = HAL_ERROR;
351  /* No error code can be set set as the handler is null */
352  }
353  else
354  {
355  /* Check the parameters of the initialization structure */
356  assert_param(IS_OSPI_FIFO_THRESHOLD (hospi->Init.FifoThreshold));
357  assert_param(IS_OSPI_DUALQUAD_MODE (hospi->Init.DualQuad));
358  assert_param(IS_OSPI_MEMORY_TYPE (hospi->Init.MemoryType));
359  assert_param(IS_OSPI_DEVICE_SIZE (hospi->Init.DeviceSize));
360  assert_param(IS_OSPI_CS_HIGH_TIME (hospi->Init.ChipSelectHighTime));
361  assert_param(IS_OSPI_FREE_RUN_CLK (hospi->Init.FreeRunningClock));
362  assert_param(IS_OSPI_CLOCK_MODE (hospi->Init.ClockMode));
363  assert_param(IS_OSPI_WRAP_SIZE (hospi->Init.WrapSize));
364  assert_param(IS_OSPI_CLK_PRESCALER (hospi->Init.ClockPrescaler));
365  assert_param(IS_OSPI_SAMPLE_SHIFTING(hospi->Init.SampleShifting));
366  assert_param(IS_OSPI_DHQC (hospi->Init.DelayHoldQuarterCycle));
367  assert_param(IS_OSPI_CS_BOUNDARY (hospi->Init.ChipSelectBoundary));
368  assert_param(IS_OSPI_CKCSHT (hospi->Init.ClkChipSelectHighTime));
369  assert_param(IS_OSPI_DLYBYP (hospi->Init.DelayBlockBypass));
370  assert_param(IS_OSPI_MAXTRAN (hospi->Init.MaxTran));
371 
372  /* Initialize error code */
373  hospi->ErrorCode = HAL_OSPI_ERROR_NONE;
374 
375  /* Check if the state is the reset state */
376  if (hospi->State == HAL_OSPI_STATE_RESET)
377  {
378 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
379  /* Reset Callback pointers in HAL_OSPI_STATE_RESET only */
380  hospi->ErrorCallback = HAL_OSPI_ErrorCallback;
381  hospi->AbortCpltCallback = HAL_OSPI_AbortCpltCallback;
382  hospi->FifoThresholdCallback = HAL_OSPI_FifoThresholdCallback;
383  hospi->CmdCpltCallback = HAL_OSPI_CmdCpltCallback;
384  hospi->RxCpltCallback = HAL_OSPI_RxCpltCallback;
385  hospi->TxCpltCallback = HAL_OSPI_TxCpltCallback;
386  hospi->RxHalfCpltCallback = HAL_OSPI_RxHalfCpltCallback;
387  hospi->TxHalfCpltCallback = HAL_OSPI_TxHalfCpltCallback;
388  hospi->StatusMatchCallback = HAL_OSPI_StatusMatchCallback;
389  hospi->TimeOutCallback = HAL_OSPI_TimeOutCallback;
390 
391  if(hospi->MspInitCallback == NULL)
392  {
393  hospi->MspInitCallback = HAL_OSPI_MspInit;
394  }
395 
396  /* Init the low level hardware */
397  hospi->MspInitCallback(hospi);
398 #else
399  /* Initialization of the low level hardware */
400  HAL_OSPI_MspInit(hospi);
401 #endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
402 
403  /* Configure the default timeout for the OSPI memory access */
404  (void)HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
405 
406  /* Configure memory type, device size, chip select high time, clocked chip select high time, delay block bypass, free running clock, clock mode */
407  MODIFY_REG(hospi->Instance->DCR1,
408  (OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_CKCSHT |
409  OCTOSPI_DCR1_DLYBYP | OCTOSPI_DCR1_FRCK | OCTOSPI_DCR1_CKMODE),
410  (hospi->Init.MemoryType | ((hospi->Init.DeviceSize - 1U) << OCTOSPI_DCR1_DEVSIZE_Pos) |
411  ((hospi->Init.ChipSelectHighTime - 1U) << OCTOSPI_DCR1_CSHT_Pos) |
412  (hospi->Init.ClkChipSelectHighTime << OCTOSPI_DCR1_CKCSHT_Pos) |
413  hospi->Init.DelayBlockBypass | hospi->Init.ClockMode));
414 
415  /* Configure wrap size */
416  MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_WRAPSIZE, hospi->Init.WrapSize);
417 
418  /* Configure chip select boundary and maximum transfer */
419  hospi->Instance->DCR3 = ((hospi->Init.ChipSelectBoundary << OCTOSPI_DCR3_CSBOUND_Pos) |
420  (hospi->Init.MaxTran << OCTOSPI_DCR3_MAXTRAN_Pos));
421 
422  /* Configure refresh */
423  hospi->Instance->DCR4 = hospi->Init.Refresh;
424 
425  /* Configure FIFO threshold */
426  MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1U) << OCTOSPI_CR_FTHRES_Pos));
427 
428  /* Wait till busy flag is reset */
429  status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout);
430 
431  if (status == HAL_OK)
432  {
433  /* Configure clock prescaler */
434  MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER,
435  ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos));
436 
437  /* Configure Dual Quad mode */
438  MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad);
439 
440  /* Configure sample shifting and delay hold quarter cycle */
441  MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC),
442  (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle));
443 
444  /* Enable OctoSPI */
445  __HAL_OSPI_ENABLE(hospi);
446 
447  /* Enable free running clock if needed : must be done after OSPI enable */
448  if (hospi->Init.FreeRunningClock == HAL_OSPI_FREERUNCLK_ENABLE)
449  {
450  SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
451  }
452 
453  /* Initialize the OSPI state */
454  if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
455  {
456  hospi->State = HAL_OSPI_STATE_HYPERBUS_INIT;
457  }
458  else
459  {
460  hospi->State = HAL_OSPI_STATE_READY;
461  }
462  }
463  }
464  }
465 
466  /* Return function status */
467  return status;
468 }
469 
475 __weak void HAL_OSPI_MspInit(OSPI_HandleTypeDef *hospi)
476 {
477  /* Prevent unused argument(s) compilation warning */
478  UNUSED(hospi);
479 
480  /* NOTE : This function should not be modified, when the callback is needed,
481  the HAL_OSPI_MspInit can be implemented in the user file
482  */
483 }
484 
490 HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi)
491 {
492  HAL_StatusTypeDef status = HAL_OK;
493 
494  /* Check the OSPI handle allocation */
495  if (hospi == NULL)
496  {
497  status = HAL_ERROR;
498  /* No error code can be set set as the handler is null */
499  }
500  else
501  {
502  /* Disable OctoSPI */
503  __HAL_OSPI_DISABLE(hospi);
504 
505  /* Disable free running clock if needed : must be done after OSPI disable */
506  CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
507 
508 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
509  if(hospi->MspDeInitCallback == NULL)
510  {
511  hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
512  }
513 
514  /* DeInit the low level hardware */
515  hospi->MspDeInitCallback(hospi);
516 #else
517  /* De-initialize the low-level hardware */
518  HAL_OSPI_MspDeInit(hospi);
519 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
520 
521  /* Reset the driver state */
522  hospi->State = HAL_OSPI_STATE_RESET;
523  }
524 
525  return status;
526 }
527 
533 __weak void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi)
534 {
535  /* Prevent unused argument(s) compilation warning */
536  UNUSED(hospi);
537 
538  /* NOTE : This function should not be modified, when the callback is needed,
539  the HAL_OSPI_MspDeInit can be implemented in the user file
540  */
541 }
542 
573 void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi)
574 {
575  __IO uint32_t *data_reg = &hospi->Instance->DR;
576  uint32_t flag = hospi->Instance->SR;
577  uint32_t itsource = hospi->Instance->CR;
578  uint32_t currentstate = hospi->State;
579 
580  /* OctoSPI fifo threshold interrupt occurred -------------------------------*/
581  if (((flag & HAL_OSPI_FLAG_FT) != 0U) && ((itsource & HAL_OSPI_IT_FT) != 0U))
582  {
583  if (currentstate == HAL_OSPI_STATE_BUSY_TX)
584  {
585  /* Write a data in the fifo */
586  *((__IO uint8_t *)data_reg) = *hospi->pBuffPtr;
587  hospi->pBuffPtr++;
588  hospi->XferCount--;
589  }
590  else if (currentstate == HAL_OSPI_STATE_BUSY_RX)
591  {
592  /* Read a data from the fifo */
593  *hospi->pBuffPtr = *((__IO uint8_t *)data_reg);
594  hospi->pBuffPtr++;
595  hospi->XferCount--;
596  }
597  else
598  {
599  /* Nothing to do */
600  }
601 
602  if (hospi->XferCount == 0U)
603  {
604  /* All data have been received or transmitted for the transfer */
605  /* Disable fifo threshold interrupt */
606  __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_FT);
607  }
608 
609  /* Fifo threshold callback */
610 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
611  hospi->FifoThresholdCallback(hospi);
612 #else
613  HAL_OSPI_FifoThresholdCallback(hospi);
614 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
615  }
616  /* OctoSPI transfer complete interrupt occurred ----------------------------*/
617  else if (((flag & HAL_OSPI_FLAG_TC) != 0U) && ((itsource & HAL_OSPI_IT_TC) != 0U))
618  {
619  if (currentstate == HAL_OSPI_STATE_BUSY_RX)
620  {
621  if ((hospi->XferCount > 0U) && ((flag & OCTOSPI_SR_FLEVEL) != 0U))
622  {
623  /* Read the last data received in the fifo */
624  *hospi->pBuffPtr = *((__IO uint8_t *)data_reg);
625  hospi->pBuffPtr++;
626  hospi->XferCount--;
627  }
628  else if(hospi->XferCount == 0U)
629  {
630  /* Clear flag */
631  hospi->Instance->FCR = HAL_OSPI_FLAG_TC;
632 
633  /* Disable the interrupts */
634  __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE);
635 
636  /* Update state */
637  hospi->State = HAL_OSPI_STATE_READY;
638 
639  /* RX complete callback */
640 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
641  hospi->RxCpltCallback(hospi);
642 #else
643  HAL_OSPI_RxCpltCallback(hospi);
644 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
645  }
646  else
647  {
648  /* Nothing to do */
649  }
650  }
651  else
652  {
653  /* Clear flag */
654  hospi->Instance->FCR = HAL_OSPI_FLAG_TC;
655 
656  /* Disable the interrupts */
657  __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE);
658 
659  /* Update state */
660  hospi->State = HAL_OSPI_STATE_READY;
661 
662  if (currentstate == HAL_OSPI_STATE_BUSY_TX)
663  {
664  /* TX complete callback */
665 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
666  hospi->TxCpltCallback(hospi);
667 #else
668  HAL_OSPI_TxCpltCallback(hospi);
669 #endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
670  }
671  else if (currentstate == HAL_OSPI_STATE_BUSY_CMD)
672  {
673  /* Command complete callback */
674 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
675  hospi->CmdCpltCallback(hospi);
676 #else
677  HAL_OSPI_CmdCpltCallback(hospi);
678 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
679  }
680  else if (currentstate == HAL_OSPI_STATE_ABORT)
681  {
682  if (hospi->ErrorCode == HAL_OSPI_ERROR_NONE)
683  {
684  /* Abort called by the user */
685  /* Abort complete callback */
686 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
687  hospi->AbortCpltCallback(hospi);
688 #else
689  HAL_OSPI_AbortCpltCallback(hospi);
690 #endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
691  }
692  else
693  {
694  /* Abort due to an error (eg : DMA error) */
695  /* Error callback */
696 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
697  hospi->ErrorCallback(hospi);
698 #else
699  HAL_OSPI_ErrorCallback(hospi);
700 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
701  }
702  }
703  else
704  {
705  /* Nothing to do */
706  }
707  }
708  }
709  /* OctoSPI status match interrupt occurred ---------------------------------*/
710  else if (((flag & HAL_OSPI_FLAG_SM) != 0U) && ((itsource & HAL_OSPI_IT_SM) != 0U))
711  {
712  /* Clear flag */
713  hospi->Instance->FCR = HAL_OSPI_FLAG_SM;
714 
715  /* Check if automatic poll mode stop is activated */
716  if ((hospi->Instance->CR & OCTOSPI_CR_APMS) != 0U)
717  {
718  /* Disable the interrupts */
719  __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_SM | HAL_OSPI_IT_TE);
720 
721  /* Update state */
722  hospi->State = HAL_OSPI_STATE_READY;
723  }
724 
725  /* Status match callback */
726 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
727  hospi->StatusMatchCallback(hospi);
728 #else
729  HAL_OSPI_StatusMatchCallback(hospi);
730 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
731  }
732  /* OctoSPI transfer error interrupt occurred -------------------------------*/
733  else if (((flag & HAL_OSPI_FLAG_TE) != 0U) && ((itsource & HAL_OSPI_IT_TE) != 0U))
734  {
735  /* Clear flag */
736  hospi->Instance->FCR = HAL_OSPI_FLAG_TE;
737 
738  /* Disable all interrupts */
739  __HAL_OSPI_DISABLE_IT(hospi, (HAL_OSPI_IT_TO | HAL_OSPI_IT_SM | HAL_OSPI_IT_FT | HAL_OSPI_IT_TC | HAL_OSPI_IT_TE));
740 
741  /* Set error code */
742  hospi->ErrorCode = HAL_OSPI_ERROR_TRANSFER;
743 
744  /* Check if the DMA is enabled */
745  if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0U)
746  {
747  /* Disable the DMA transfer on the OctoSPI side */
748  CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
749 
750  /* Disable the DMA transfer on the DMA side */
751  hospi->hmdma->XferAbortCallback = OSPI_DMAAbortCplt;
752  if (HAL_MDMA_Abort_IT(hospi->hmdma) != HAL_OK)
753  {
754  /* Update state */
755  hospi->State = HAL_OSPI_STATE_READY;
756 
757  /* Error callback */
758 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
759  hospi->ErrorCallback(hospi);
760 #else
761  HAL_OSPI_ErrorCallback(hospi);
762 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
763  }
764  }
765  else
766  {
767  /* Update state */
768  hospi->State = HAL_OSPI_STATE_READY;
769 
770  /* Error callback */
771 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
772  hospi->ErrorCallback(hospi);
773 #else
774  HAL_OSPI_ErrorCallback(hospi);
775 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
776  }
777  }
778  /* OctoSPI timeout interrupt occurred --------------------------------------*/
779  else if (((flag & HAL_OSPI_FLAG_TO) != 0U) && ((itsource & HAL_OSPI_IT_TO) != 0U))
780  {
781  /* Clear flag */
782  hospi->Instance->FCR = HAL_OSPI_FLAG_TO;
783 
784  /* Timeout callback */
785 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
786  hospi->TimeOutCallback(hospi);
787 #else
788  HAL_OSPI_TimeOutCallback(hospi);
789 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
790  }
791  else
792  {
793  /* Nothing to do */
794  }
795 }
796 
804 HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout)
805 {
806  HAL_StatusTypeDef status;
807  uint32_t state;
808  uint32_t tickstart = HAL_GetTick();
809 
810  /* Check the parameters of the command structure */
811  assert_param(IS_OSPI_OPERATION_TYPE(cmd->OperationType));
812 
813  if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE)
814  {
815  assert_param(IS_OSPI_FLASH_ID(cmd->FlashId));
816  }
817 
818  assert_param(IS_OSPI_INSTRUCTION_MODE(cmd->InstructionMode));
819  if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE)
820  {
821  assert_param(IS_OSPI_INSTRUCTION_SIZE (cmd->InstructionSize));
822  assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode));
823  }
824 
825  assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode));
826  if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE)
827  {
828  assert_param(IS_OSPI_ADDRESS_SIZE (cmd->AddressSize));
829  assert_param(IS_OSPI_ADDRESS_DTR_MODE(cmd->AddressDtrMode));
830  }
831 
832  assert_param(IS_OSPI_ALT_BYTES_MODE(cmd->AlternateBytesMode));
833  if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE)
834  {
835  assert_param(IS_OSPI_ALT_BYTES_SIZE (cmd->AlternateBytesSize));
836  assert_param(IS_OSPI_ALT_BYTES_DTR_MODE(cmd->AlternateBytesDtrMode));
837  }
838 
839  assert_param(IS_OSPI_DATA_MODE(cmd->DataMode));
840  if (cmd->DataMode != HAL_OSPI_DATA_NONE)
841  {
842  if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG)
843  {
844  assert_param(IS_OSPI_NUMBER_DATA (cmd->NbData));
845  }
846  assert_param(IS_OSPI_DATA_DTR_MODE(cmd->DataDtrMode));
847  assert_param(IS_OSPI_DUMMY_CYCLES (cmd->DummyCycles));
848  }
849 
850  assert_param(IS_OSPI_DQS_MODE (cmd->DQSMode));
851  assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode));
852 
853  /* Check the state of the driver */
854  state = hospi->State;
855  if (((state == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) ||
856  ((state == HAL_OSPI_STATE_READ_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)
857  || (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))) ||
858  ((state == HAL_OSPI_STATE_WRITE_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG) ||
859  (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))))
860  {
861  /* Wait till busy flag is reset */
862  status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout);
863 
864  if (status == HAL_OK)
865  {
866  /* Initialize error code */
867  hospi->ErrorCode = HAL_OSPI_ERROR_NONE;
868 
869  /* Configure the registers */
870  status = OSPI_ConfigCmd(hospi, cmd);
871 
872  if (status == HAL_OK)
873  {
874  if (cmd->DataMode == HAL_OSPI_DATA_NONE)
875  {
876  /* When there is no data phase, the transfer start as soon as the configuration is done
877  so wait until TC flag is set to go back in idle state */
878  status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout);
879 
880  __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
881  }
882  else
883  {
884  /* Update the state */
885  if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG)
886  {
887  hospi->State = HAL_OSPI_STATE_CMD_CFG;
888  }
889  else if (cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG)
890  {
891  if (hospi->State == HAL_OSPI_STATE_WRITE_CMD_CFG)
892  {
893  hospi->State = HAL_OSPI_STATE_CMD_CFG;
894  }
895  else
896  {
897  hospi->State = HAL_OSPI_STATE_READ_CMD_CFG;
898  }
899  }
900  else if (cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)
901  {
902  if (hospi->State == HAL_OSPI_STATE_READ_CMD_CFG)
903  {
904  hospi->State = HAL_OSPI_STATE_CMD_CFG;
905  }
906  else
907  {
908  hospi->State = HAL_OSPI_STATE_WRITE_CMD_CFG;
909  }
910  }
911  else
912  {
913  /* Wrap configuration, no state change */
914  }
915  }
916  }
917  }
918  }
919  else
920  {
921  status = HAL_ERROR;
922  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
923  }
924 
925  /* Return function status */
926  return status;
927 }
928 
936 HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd)
937 {
938  HAL_StatusTypeDef status;
939  uint32_t tickstart = HAL_GetTick();
940 
941  /* Check the parameters of the command structure */
942  assert_param(IS_OSPI_OPERATION_TYPE(cmd->OperationType));
943 
944  if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE)
945  {
946  assert_param(IS_OSPI_FLASH_ID(cmd->FlashId));
947  }
948 
949  assert_param(IS_OSPI_INSTRUCTION_MODE(cmd->InstructionMode));
950  if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE)
951  {
952  assert_param(IS_OSPI_INSTRUCTION_SIZE (cmd->InstructionSize));
953  assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode));
954  }
955 
956  assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode));
957  if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE)
958  {
959  assert_param(IS_OSPI_ADDRESS_SIZE (cmd->AddressSize));
960  assert_param(IS_OSPI_ADDRESS_DTR_MODE(cmd->AddressDtrMode));
961  }
962 
963  assert_param(IS_OSPI_ALT_BYTES_MODE(cmd->AlternateBytesMode));
964  if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE)
965  {
966  assert_param(IS_OSPI_ALT_BYTES_SIZE (cmd->AlternateBytesSize));
967  assert_param(IS_OSPI_ALT_BYTES_DTR_MODE(cmd->AlternateBytesDtrMode));
968  }
969 
970  assert_param(IS_OSPI_DATA_MODE(cmd->DataMode));
971  if (cmd->DataMode != HAL_OSPI_DATA_NONE)
972  {
973  assert_param(IS_OSPI_NUMBER_DATA (cmd->NbData));
974  assert_param(IS_OSPI_DATA_DTR_MODE(cmd->DataDtrMode));
975  assert_param(IS_OSPI_DUMMY_CYCLES (cmd->DummyCycles));
976  }
977 
978  assert_param(IS_OSPI_DQS_MODE (cmd->DQSMode));
979  assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode));
980 
981  /* Check the state of the driver */
982  if ((hospi->State == HAL_OSPI_STATE_READY) && (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG) &&
983  (cmd->DataMode == HAL_OSPI_DATA_NONE) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS))
984  {
985  /* Wait till busy flag is reset */
986  status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout);
987 
988  if (status == HAL_OK)
989  {
990  /* Initialize error code */
991  hospi->ErrorCode = HAL_OSPI_ERROR_NONE;
992 
993  /* Clear flags related to interrupt */
994  __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC);
995 
996  /* Configure the registers */
997  status = OSPI_ConfigCmd(hospi, cmd);
998 
999  if (status == HAL_OK)
1000  {
1001  /* Update the state */
1002  hospi->State = HAL_OSPI_STATE_BUSY_CMD;
1003 
1004  /* Enable the transfer complete and transfer error interrupts */
1005  __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_TE);
1006  }
1007  }
1008  }
1009  else
1010  {
1011  status = HAL_ERROR;
1012  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
1013  }
1014 
1015  /* Return function status */
1016  return status;
1017 }
1018 
1026 HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout)
1027 {
1028  HAL_StatusTypeDef status;
1029  uint32_t state;
1030  uint32_t tickstart = HAL_GetTick();
1031 
1032  /* Check the parameters of the hyperbus configuration structure */
1033  assert_param(IS_OSPI_RW_RECOVERY_TIME (cfg->RWRecoveryTime));
1034  assert_param(IS_OSPI_ACCESS_TIME (cfg->AccessTime));
1035  assert_param(IS_OSPI_WRITE_ZERO_LATENCY(cfg->WriteZeroLatency));
1036  assert_param(IS_OSPI_LATENCY_MODE (cfg->LatencyMode));
1037 
1038  /* Check the state of the driver */
1039  state = hospi->State;
1040  if ((state == HAL_OSPI_STATE_HYPERBUS_INIT) || (state == HAL_OSPI_STATE_READY))
1041  {
1042  /* Wait till busy flag is reset */
1043  status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout);
1044 
1045  if (status == HAL_OK)
1046  {
1047  /* Configure Hyperbus configuration Latency register */
1048  WRITE_REG(hospi->Instance->HLCR, ((cfg->RWRecoveryTime << OCTOSPI_HLCR_TRWR_Pos) |
1049  (cfg->AccessTime << OCTOSPI_HLCR_TACC_Pos) |
1050  cfg->WriteZeroLatency | cfg->LatencyMode));
1051 
1052  /* Update the state */
1053  hospi->State = HAL_OSPI_STATE_READY;
1054  }
1055  }
1056  else
1057  {
1058  status = HAL_ERROR;
1059  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
1060  }
1061 
1062  /* Return function status */
1063  return status;
1064 }
1065 
1073 HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout)
1074 {
1075  HAL_StatusTypeDef status;
1076  uint32_t tickstart = HAL_GetTick();
1077 
1078  /* Check the parameters of the hyperbus command structure */
1079  assert_param(IS_OSPI_ADDRESS_SPACE(cmd->AddressSpace));
1080  assert_param(IS_OSPI_ADDRESS_SIZE (cmd->AddressSize));
1081  assert_param(IS_OSPI_NUMBER_DATA (cmd->NbData));
1082  assert_param(IS_OSPI_DQS_MODE (cmd->DQSMode));
1083 
1084  /* Check the state of the driver */
1085  if ((hospi->State == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS))
1086  {
1087  /* Wait till busy flag is reset */
1088  status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout);
1089 
1090  if (status == HAL_OK)
1091  {
1092  /* Re-initialize the value of the functional mode */
1093  MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0U);
1094 
1095  /* Configure the address space in the DCR1 register */
1096  MODIFY_REG(hospi->Instance->DCR1, OCTOSPI_DCR1_MTYP_0, cmd->AddressSpace);
1097 
1098  /* Configure the CCR and WCCR registers with the address size and the following configuration :
1099  - DQS signal enabled (used as RWDS)
1100  - DTR mode enabled on address and data
1101  - address and data on 8 lines */
1102  WRITE_REG(hospi->Instance->CCR, (cmd->DQSMode | OCTOSPI_CCR_DDTR | OCTOSPI_CCR_DMODE_2 |
1103  cmd->AddressSize | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADMODE_2));
1104  WRITE_REG(hospi->Instance->WCCR, (cmd->DQSMode | OCTOSPI_WCCR_DDTR | OCTOSPI_WCCR_DMODE_2 |
1105  cmd->AddressSize | OCTOSPI_WCCR_ADDTR | OCTOSPI_WCCR_ADMODE_2));
1106 
1107  /* Configure the DLR register with the number of data */
1108  WRITE_REG(hospi->Instance->DLR, (cmd->NbData - 1U));
1109 
1110  /* Configure the AR register with the address value */
1111  WRITE_REG(hospi->Instance->AR, cmd->Address);
1112 
1113  /* Update the state */
1114  hospi->State = HAL_OSPI_STATE_CMD_CFG;
1115  }
1116  }
1117  else
1118  {
1119  status = HAL_ERROR;
1120  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
1121  }
1122 
1123  /* Return function status */
1124  return status;
1125 }
1126 
1135 HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout)
1136 {
1137  HAL_StatusTypeDef status;
1138  uint32_t tickstart = HAL_GetTick();
1139  __IO uint32_t *data_reg = &hospi->Instance->DR;
1140 
1141  /* Check the data pointer allocation */
1142  if (pData == NULL)
1143  {
1144  status = HAL_ERROR;
1145  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
1146  }
1147  else
1148  {
1149  /* Check the state */
1150  if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
1151  {
1152  /* Configure counters and size */
1153  hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U;
1154  hospi->XferSize = hospi->XferCount;
1155  hospi->pBuffPtr = pData;
1156 
1157  /* Configure CR register with functional mode as indirect write */
1158  MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
1159 
1160  do
1161  {
1162  /* Wait till fifo threshold flag is set to send data */
1163  status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_FT, SET, tickstart, Timeout);
1164 
1165  if (status != HAL_OK)
1166  {
1167  break;
1168  }
1169 
1170  *((__IO uint8_t *)data_reg) = *hospi->pBuffPtr;
1171  hospi->pBuffPtr++;
1172  hospi->XferCount--;
1173  } while (hospi->XferCount > 0U);
1174 
1175  if (status == HAL_OK)
1176  {
1177  /* Wait till transfer complete flag is set to go back in idle state */
1178  status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout);
1179 
1180  if (status == HAL_OK)
1181  {
1182  /* Clear transfer complete flag */
1183  __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
1184 
1185  /* Update state */
1186  hospi->State = HAL_OSPI_STATE_READY;
1187  }
1188  }
1189  }
1190  else
1191  {
1192  status = HAL_ERROR;
1193  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
1194  }
1195  }
1196 
1197  /* Return function status */
1198  return status;
1199 }
1200 
1209 HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout)
1210 {
1211  HAL_StatusTypeDef status;
1212  uint32_t tickstart = HAL_GetTick();
1213  __IO uint32_t *data_reg = &hospi->Instance->DR;
1214  uint32_t addr_reg = hospi->Instance->AR;
1215  uint32_t ir_reg = hospi->Instance->IR;
1216 
1217  /* Check the data pointer allocation */
1218  if (pData == NULL)
1219  {
1220  status = HAL_ERROR;
1221  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
1222  }
1223  else
1224  {
1225  /* Check the state */
1226  if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
1227  {
1228  /* Configure counters and size */
1229  hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U;
1230  hospi->XferSize = hospi->XferCount;
1231  hospi->pBuffPtr = pData;
1232 
1233  /* Configure CR register with functional mode as indirect read */
1234  MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ);
1235 
1236  /* Trig the transfer by re-writing address or instruction register */
1237  if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
1238  {
1239  WRITE_REG(hospi->Instance->AR, addr_reg);
1240  }
1241  else
1242  {
1243  if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
1244  {
1245  WRITE_REG(hospi->Instance->AR, addr_reg);
1246  }
1247  else
1248  {
1249  WRITE_REG(hospi->Instance->IR, ir_reg);
1250  }
1251  }
1252 
1253  do
1254  {
1255  /* Wait till fifo threshold or transfer complete flags are set to read received data */
1256  status = OSPI_WaitFlagStateUntilTimeout(hospi, (HAL_OSPI_FLAG_FT | HAL_OSPI_FLAG_TC), SET, tickstart, Timeout);
1257 
1258  if (status != HAL_OK)
1259  {
1260  break;
1261  }
1262 
1263  *hospi->pBuffPtr = *((__IO uint8_t *)data_reg);
1264  hospi->pBuffPtr++;
1265  hospi->XferCount--;
1266  } while(hospi->XferCount > 0U);
1267 
1268  if (status == HAL_OK)
1269  {
1270  /* Wait till transfer complete flag is set to go back in idle state */
1271  status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout);
1272 
1273  if (status == HAL_OK)
1274  {
1275  /* Clear transfer complete flag */
1276  __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
1277 
1278  /* Update state */
1279  hospi->State = HAL_OSPI_STATE_READY;
1280  }
1281  }
1282  }
1283  else
1284  {
1285  status = HAL_ERROR;
1286  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
1287  }
1288  }
1289 
1290  /* Return function status */
1291  return status;
1292 }
1293 
1301 HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData)
1302 {
1303  HAL_StatusTypeDef status = HAL_OK;
1304 
1305  /* Check the data pointer allocation */
1306  if (pData == NULL)
1307  {
1308  status = HAL_ERROR;
1309  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
1310  }
1311  else
1312  {
1313  /* Check the state */
1314  if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
1315  {
1316  /* Configure counters and size */
1317  hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U;
1318  hospi->XferSize = hospi->XferCount;
1319  hospi->pBuffPtr = pData;
1320 
1321  /* Configure CR register with functional mode as indirect write */
1322  MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
1323 
1324  /* Clear flags related to interrupt */
1325  __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC);
1326 
1327  /* Update the state */
1328  hospi->State = HAL_OSPI_STATE_BUSY_TX;
1329 
1330  /* Enable the transfer complete, fifo threshold and transfer error interrupts */
1331  __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE);
1332  }
1333  else
1334  {
1335  status = HAL_ERROR;
1336  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
1337  }
1338  }
1339 
1340  /* Return function status */
1341  return status;
1342 }
1343 
1351 HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData)
1352 {
1353  HAL_StatusTypeDef status = HAL_OK;
1354  uint32_t addr_reg = hospi->Instance->AR;
1355  uint32_t ir_reg = hospi->Instance->IR;
1356 
1357  /* Check the data pointer allocation */
1358  if (pData == NULL)
1359  {
1360  status = HAL_ERROR;
1361  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
1362  }
1363  else
1364  {
1365  /* Check the state */
1366  if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
1367  {
1368  /* Configure counters and size */
1369  hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U;
1370  hospi->XferSize = hospi->XferCount;
1371  hospi->pBuffPtr = pData;
1372 
1373  /* Configure CR register with functional mode as indirect read */
1374  MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ);
1375 
1376  /* Clear flags related to interrupt */
1377  __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC);
1378 
1379  /* Update the state */
1380  hospi->State = HAL_OSPI_STATE_BUSY_RX;
1381 
1382  /* Enable the transfer complete, fifo threshold and transfer error interrupts */
1383  __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE);
1384 
1385  /* Trig the transfer by re-writing address or instruction register */
1386  if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
1387  {
1388  WRITE_REG(hospi->Instance->AR, addr_reg);
1389  }
1390  else
1391  {
1392  if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
1393  {
1394  WRITE_REG(hospi->Instance->AR, addr_reg);
1395  }
1396  else
1397  {
1398  WRITE_REG(hospi->Instance->IR, ir_reg);
1399  }
1400  }
1401  }
1402  else
1403  {
1404  status = HAL_ERROR;
1405  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
1406  }
1407  }
1408 
1409  /* Return function status */
1410  return status;
1411 }
1412 
1424 HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData)
1425 {
1426  HAL_StatusTypeDef status = HAL_OK;
1427  uint32_t data_size = hospi->Instance->DLR + 1U;
1428 
1429  /* Check the data pointer allocation */
1430  if (pData == NULL)
1431  {
1432  status = HAL_ERROR;
1433  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
1434  }
1435  else
1436  {
1437  /* Check the state */
1438  if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
1439  {
1440  hospi->XferCount = data_size;
1441 
1442  {
1443  hospi->XferSize = hospi->XferCount;
1444  hospi->pBuffPtr = pData;
1445 
1446  /* Configure CR register with functional mode as indirect write */
1447  MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
1448 
1449  /* Clear flags related to interrupt */
1450  __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC);
1451 
1452  /* Update the state */
1453  hospi->State = HAL_OSPI_STATE_BUSY_TX;
1454 
1455  /* Set the MDMA transfer complete callback */
1456  hospi->hmdma->XferCpltCallback = OSPI_DMACplt;
1457 
1458  /* Set the MDMA error callback */
1459  hospi->hmdma->XferErrorCallback = OSPI_DMAError;
1460 
1461  /* Clear the MDMA abort callback */
1462  hospi->hmdma->XferAbortCallback = NULL;
1463 
1464  /* In Transmit mode , the MDMA destination is the OSPI DR register : Force the MDMA Destination Increment to disable */
1465  MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) ,MDMA_DEST_INC_DISABLE);
1466 
1467  /* Update MDMA configuration with the correct SourceInc field for Write operation */
1468  if (hospi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE)
1469  {
1470  MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_BYTE);
1471  }
1472  else if (hospi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_HALFWORD)
1473  {
1474  MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_HALFWORD);
1475  }
1476  else if (hospi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_WORD)
1477  {
1478  MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_WORD);
1479  }
1480  else
1481  {
1482  /* in case of incorrect source data size */
1483  hospi->ErrorCode |= HAL_OSPI_ERROR_DMA;
1484  status = HAL_ERROR;
1485  }
1486 
1487  /* Enable the transmit MDMA Channel */
1488  if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)pData, (uint32_t)&hospi->Instance->DR, hospi->XferSize,1) == HAL_OK)
1489  {
1490  /* Enable the transfer error interrupt */
1491  __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
1492 
1493  /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
1494  }
1495  else
1496  {
1497  status = HAL_ERROR;
1498  hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
1499  hospi->State = HAL_OSPI_STATE_READY;
1500  }
1501  }
1502  }
1503  else
1504  {
1505  status = HAL_ERROR;
1506  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
1507  }
1508  }
1509 
1510  /* Return function status */
1511  return status;
1512 }
1513 
1525 HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData)
1526 {
1527  HAL_StatusTypeDef status = HAL_OK;
1528  uint32_t data_size = hospi->Instance->DLR + 1U;
1529  uint32_t addr_reg = hospi->Instance->AR;
1530  uint32_t ir_reg = hospi->Instance->IR;
1531 
1532  /* Check the data pointer allocation */
1533  if (pData == NULL)
1534  {
1535  status = HAL_ERROR;
1536  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
1537  }
1538  else
1539  {
1540  /* Check the state */
1541  if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
1542  {
1543  hospi->XferCount = data_size;
1544 
1545  {
1546  hospi->XferSize = hospi->XferCount;
1547  hospi->pBuffPtr = pData;
1548 
1549  /* Configure CR register with functional mode as indirect read */
1550  MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ);
1551 
1552  /* Clear flags related to interrupt */
1553  __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC);
1554 
1555  /* Update the state */
1556  hospi->State = HAL_OSPI_STATE_BUSY_RX;
1557 
1558  /* Set the DMA transfer complete callback */
1559  hospi->hmdma->XferCpltCallback = OSPI_DMACplt;
1560 
1561  /* Set the DMA error callback */
1562  hospi->hmdma->XferErrorCallback = OSPI_DMAError;
1563 
1564  /* Clear the DMA abort callback */
1565  hospi->hmdma->XferAbortCallback = NULL;
1566 
1567 /* In Receive mode , the MDMA source is the OSPI DR register : Force the MDMA Source Increment to disable */
1568  MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_DISABLE);
1569 
1570  /* Update MDMA configuration with the correct DestinationInc field for read operation */
1571  if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_BYTE)
1572  {
1573  MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_BYTE);
1574  }
1575  else if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_HALFWORD)
1576  {
1577  MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_HALFWORD);
1578  }
1579  else if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_WORD)
1580  {
1581  MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_WORD);
1582  }
1583  else
1584  {
1585  /* in case of incorrect destination data size */
1586  hospi->ErrorCode |= HAL_OSPI_ERROR_DMA;
1587  status = HAL_ERROR;
1588  }
1589 
1590  /* Enable the transmit MDMA Channel */
1591  if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)&hospi->Instance->DR, (uint32_t)pData, hospi->XferSize, 1) == HAL_OK)
1592  {
1593  /* Enable the transfer error interrupt */
1594  __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
1595 
1596  /* Trig the transfer by re-writing address or instruction register */
1597  if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
1598  {
1599  WRITE_REG(hospi->Instance->AR, addr_reg);
1600  }
1601  else
1602  {
1603  if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
1604  {
1605  WRITE_REG(hospi->Instance->AR, addr_reg);
1606  }
1607  else
1608  {
1609  WRITE_REG(hospi->Instance->IR, ir_reg);
1610  }
1611  }
1612 
1613  /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
1614  }
1615  else
1616  {
1617  status = HAL_ERROR;
1618  hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
1619  hospi->State = HAL_OSPI_STATE_READY;
1620  }
1621  }
1622  }
1623  else
1624  {
1625  status = HAL_ERROR;
1626  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
1627  }
1628  }
1629 
1630  /* Return function status */
1631  return status;
1632 }
1633 
1642 HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
1643 {
1644  HAL_StatusTypeDef status;
1645  uint32_t tickstart = HAL_GetTick();
1646  uint32_t addr_reg = hospi->Instance->AR;
1647  uint32_t ir_reg = hospi->Instance->IR;
1648 #ifdef USE_FULL_ASSERT
1649  uint32_t dlr_reg = hospi->Instance->DLR;
1650 #endif /* USE_FULL_ASSERT */
1651 
1652  /* Check the parameters of the autopolling configuration structure */
1653  assert_param(IS_OSPI_MATCH_MODE (cfg->MatchMode));
1654  assert_param(IS_OSPI_AUTOMATIC_STOP (cfg->AutomaticStop));
1655  assert_param(IS_OSPI_INTERVAL (cfg->Interval));
1656  assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg+1U));
1657 
1658  /* Check the state */
1659  if ((hospi->State == HAL_OSPI_STATE_CMD_CFG) && (cfg->AutomaticStop == HAL_OSPI_AUTOMATIC_STOP_ENABLE))
1660  {
1661  /* Wait till busy flag is reset */
1662  status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout);
1663 
1664  if (status == HAL_OK)
1665  {
1666  /* Configure registers */
1667  WRITE_REG (hospi->Instance->PSMAR, cfg->Match);
1668  WRITE_REG (hospi->Instance->PSMKR, cfg->Mask);
1669  WRITE_REG (hospi->Instance->PIR, cfg->Interval);
1670  MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE),
1671  (cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING));
1672 
1673  /* Trig the transfer by re-writing address or instruction register */
1674  if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
1675  {
1676  WRITE_REG(hospi->Instance->AR, addr_reg);
1677  }
1678  else
1679  {
1680  if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
1681  {
1682  WRITE_REG(hospi->Instance->AR, addr_reg);
1683  }
1684  else
1685  {
1686  WRITE_REG(hospi->Instance->IR, ir_reg);
1687  }
1688  }
1689 
1690  /* Wait till status match flag is set to go back in idle state */
1691  status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_SM, SET, tickstart, Timeout);
1692 
1693  if (status == HAL_OK)
1694  {
1695  /* Clear status match flag */
1696  __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_SM);
1697 
1698  /* Update state */
1699  hospi->State = HAL_OSPI_STATE_READY;
1700  }
1701  }
1702  }
1703  else
1704  {
1705  status = HAL_ERROR;
1706  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
1707  }
1708 
1709  /* Return function status */
1710  return status;
1711 }
1712 
1720 HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg)
1721 {
1722  HAL_StatusTypeDef status;
1723  uint32_t tickstart = HAL_GetTick();
1724  uint32_t addr_reg = hospi->Instance->AR;
1725  uint32_t ir_reg = hospi->Instance->IR;
1726 #ifdef USE_FULL_ASSERT
1727  uint32_t dlr_reg = hospi->Instance->DLR;
1728 #endif /* USE_FULL_ASSERT */
1729 
1730  /* Check the parameters of the autopolling configuration structure */
1731  assert_param(IS_OSPI_MATCH_MODE (cfg->MatchMode));
1732  assert_param(IS_OSPI_AUTOMATIC_STOP (cfg->AutomaticStop));
1733  assert_param(IS_OSPI_INTERVAL (cfg->Interval));
1734  assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg+1U));
1735 
1736  /* Check the state */
1737  if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
1738  {
1739  /* Wait till busy flag is reset */
1740  status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout);
1741 
1742  if (status == HAL_OK)
1743  {
1744  /* Configure registers */
1745  WRITE_REG (hospi->Instance->PSMAR, cfg->Match);
1746  WRITE_REG (hospi->Instance->PSMKR, cfg->Mask);
1747  WRITE_REG (hospi->Instance->PIR, cfg->Interval);
1748  MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE),
1749  (cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING));
1750 
1751  /* Clear flags related to interrupt */
1752  __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_SM);
1753 
1754  /* Update state */
1755  hospi->State = HAL_OSPI_STATE_BUSY_AUTO_POLLING;
1756 
1757  /* Enable the status match and transfer error interrupts */
1758  __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_SM | HAL_OSPI_IT_TE);
1759 
1760  /* Trig the transfer by re-writing address or instruction register */
1761  if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
1762  {
1763  WRITE_REG(hospi->Instance->AR, addr_reg);
1764  }
1765  else
1766  {
1767  if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
1768  {
1769  WRITE_REG(hospi->Instance->AR, addr_reg);
1770  }
1771  else
1772  {
1773  WRITE_REG(hospi->Instance->IR, ir_reg);
1774  }
1775  }
1776  }
1777  }
1778  else
1779  {
1780  status = HAL_ERROR;
1781  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
1782  }
1783 
1784  /* Return function status */
1785  return status;
1786 }
1787 
1795 HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg)
1796 {
1797  HAL_StatusTypeDef status;
1798  uint32_t tickstart = HAL_GetTick();
1799 
1800  /* Check the parameters of the memory-mapped configuration structure */
1801  assert_param(IS_OSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
1802 
1803  /* Check the state */
1804  if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
1805  {
1806  /* Wait till busy flag is reset */
1807  status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout);
1808 
1809  if (status == HAL_OK)
1810  {
1811  /* Update state */
1812  hospi->State = HAL_OSPI_STATE_BUSY_MEM_MAPPED;
1813 
1814  if (cfg->TimeOutActivation == HAL_OSPI_TIMEOUT_COUNTER_ENABLE)
1815  {
1816  assert_param(IS_OSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
1817 
1818  /* Configure register */
1819  WRITE_REG(hospi->Instance->LPTR, cfg->TimeOutPeriod);
1820 
1821  /* Clear flags related to interrupt */
1822  __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TO);
1823 
1824  /* Enable the timeout interrupt */
1825  __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TO);
1826  }
1827 
1828  /* Configure CR register with functional mode as memory-mapped */
1829  MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_TCEN | OCTOSPI_CR_FMODE),
1830  (cfg->TimeOutActivation | OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED));
1831  }
1832  }
1833  else
1834  {
1835  status = HAL_ERROR;
1836  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
1837  }
1838 
1839  /* Return function status */
1840  return status;
1841 }
1842 
1848 __weak void HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef *hospi)
1849 {
1850  /* Prevent unused argument(s) compilation warning */
1851  UNUSED(hospi);
1852 
1853  /* NOTE : This function should not be modified, when the callback is needed,
1854  the HAL_OSPI_ErrorCallback could be implemented in the user file
1855  */
1856 }
1857 
1863 __weak void HAL_OSPI_AbortCpltCallback(OSPI_HandleTypeDef *hospi)
1864 {
1865  /* Prevent unused argument(s) compilation warning */
1866  UNUSED(hospi);
1867 
1868  /* NOTE: This function should not be modified, when the callback is needed,
1869  the HAL_OSPI_AbortCpltCallback could be implemented in the user file
1870  */
1871 }
1872 
1878 __weak void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi)
1879 {
1880  /* Prevent unused argument(s) compilation warning */
1881  UNUSED(hospi);
1882 
1883  /* NOTE : This function should not be modified, when the callback is needed,
1884  the HAL_OSPI_FIFOThresholdCallback could be implemented in the user file
1885  */
1886 }
1887 
1893 __weak void HAL_OSPI_CmdCpltCallback(OSPI_HandleTypeDef *hospi)
1894 {
1895  /* Prevent unused argument(s) compilation warning */
1896  UNUSED(hospi);
1897 
1898  /* NOTE: This function should not be modified, when the callback is needed,
1899  the HAL_OSPI_CmdCpltCallback could be implemented in the user file
1900  */
1901 }
1902 
1908 __weak void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi)
1909 {
1910  /* Prevent unused argument(s) compilation warning */
1911  UNUSED(hospi);
1912 
1913  /* NOTE: This function should not be modified, when the callback is needed,
1914  the HAL_OSPI_RxCpltCallback could be implemented in the user file
1915  */
1916 }
1917 
1923  __weak void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi)
1924 {
1925  /* Prevent unused argument(s) compilation warning */
1926  UNUSED(hospi);
1927 
1928  /* NOTE: This function should not be modified, when the callback is needed,
1929  the HAL_OSPI_TxCpltCallback could be implemented in the user file
1930  */
1931 }
1932 
1938 __weak void HAL_OSPI_RxHalfCpltCallback(OSPI_HandleTypeDef *hospi)
1939 {
1940  /* Prevent unused argument(s) compilation warning */
1941  UNUSED(hospi);
1942 
1943  /* NOTE: This function should not be modified, when the callback is needed,
1944  the HAL_OSPI_RxHalfCpltCallback could be implemented in the user file
1945  */
1946 }
1947 
1953 __weak void HAL_OSPI_TxHalfCpltCallback(OSPI_HandleTypeDef *hospi)
1954 {
1955  /* Prevent unused argument(s) compilation warning */
1956  UNUSED(hospi);
1957 
1958  /* NOTE: This function should not be modified, when the callback is needed,
1959  the HAL_OSPI_TxHalfCpltCallback could be implemented in the user file
1960  */
1961 }
1962 
1968 __weak void HAL_OSPI_StatusMatchCallback(OSPI_HandleTypeDef *hospi)
1969 {
1970  /* Prevent unused argument(s) compilation warning */
1971  UNUSED(hospi);
1972 
1973  /* NOTE : This function should not be modified, when the callback is needed,
1974  the HAL_OSPI_StatusMatchCallback could be implemented in the user file
1975  */
1976 }
1977 
1983 __weak void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi)
1984 {
1985  /* Prevent unused argument(s) compilation warning */
1986  UNUSED(hospi);
1987 
1988  /* NOTE : This function should not be modified, when the callback is needed,
1989  the HAL_OSPI_TimeOutCallback could be implemented in the user file
1990  */
1991 }
1992 
1993 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
1994 
2015 HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID,
2016  pOSPI_CallbackTypeDef pCallback)
2017 {
2018  HAL_StatusTypeDef status = HAL_OK;
2019 
2020  if(pCallback == NULL)
2021  {
2022  /* Update the error code */
2023  hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
2024  return HAL_ERROR;
2025  }
2026 
2027  if(hospi->State == HAL_OSPI_STATE_READY)
2028  {
2029  switch (CallbackID)
2030  {
2031  case HAL_OSPI_ERROR_CB_ID :
2032  hospi->ErrorCallback = pCallback;
2033  break;
2034  case HAL_OSPI_ABORT_CB_ID :
2035  hospi->AbortCpltCallback = pCallback;
2036  break;
2037  case HAL_OSPI_FIFO_THRESHOLD_CB_ID :
2038  hospi->FifoThresholdCallback = pCallback;
2039  break;
2040  case HAL_OSPI_CMD_CPLT_CB_ID :
2041  hospi->CmdCpltCallback = pCallback;
2042  break;
2043  case HAL_OSPI_RX_CPLT_CB_ID :
2044  hospi->RxCpltCallback = pCallback;
2045  break;
2046  case HAL_OSPI_TX_CPLT_CB_ID :
2047  hospi->TxCpltCallback = pCallback;
2048  break;
2049  case HAL_OSPI_RX_HALF_CPLT_CB_ID :
2050  hospi->RxHalfCpltCallback = pCallback;
2051  break;
2052  case HAL_OSPI_TX_HALF_CPLT_CB_ID :
2053  hospi->TxHalfCpltCallback = pCallback;
2054  break;
2055  case HAL_OSPI_STATUS_MATCH_CB_ID :
2056  hospi->StatusMatchCallback = pCallback;
2057  break;
2058  case HAL_OSPI_TIMEOUT_CB_ID :
2059  hospi->TimeOutCallback = pCallback;
2060  break;
2061  case HAL_OSPI_MSP_INIT_CB_ID :
2062  hospi->MspInitCallback = pCallback;
2063  break;
2064  case HAL_OSPI_MSP_DEINIT_CB_ID :
2065  hospi->MspDeInitCallback = pCallback;
2066  break;
2067  default :
2068  /* Update the error code */
2069  hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
2070  /* update return status */
2071  status = HAL_ERROR;
2072  break;
2073  }
2074  }
2075  else if (hospi->State == HAL_OSPI_STATE_RESET)
2076  {
2077  switch (CallbackID)
2078  {
2079  case HAL_OSPI_MSP_INIT_CB_ID :
2080  hospi->MspInitCallback = pCallback;
2081  break;
2082  case HAL_OSPI_MSP_DEINIT_CB_ID :
2083  hospi->MspDeInitCallback = pCallback;
2084  break;
2085  default :
2086  /* Update the error code */
2087  hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
2088  /* update return status */
2089  status = HAL_ERROR;
2090  break;
2091  }
2092  }
2093  else
2094  {
2095  /* Update the error code */
2096  hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
2097  /* update return status */
2098  status = HAL_ERROR;
2099  }
2100 
2101  return status;
2102 }
2103 
2124 HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID)
2125 {
2126  HAL_StatusTypeDef status = HAL_OK;
2127 
2128  if(hospi->State == HAL_OSPI_STATE_READY)
2129  {
2130  switch (CallbackID)
2131  {
2132  case HAL_OSPI_ERROR_CB_ID :
2133  hospi->ErrorCallback = HAL_OSPI_ErrorCallback;
2134  break;
2135  case HAL_OSPI_ABORT_CB_ID :
2136  hospi->AbortCpltCallback = HAL_OSPI_AbortCpltCallback;
2137  break;
2138  case HAL_OSPI_FIFO_THRESHOLD_CB_ID :
2139  hospi->FifoThresholdCallback = HAL_OSPI_FifoThresholdCallback;
2140  break;
2141  case HAL_OSPI_CMD_CPLT_CB_ID :
2142  hospi->CmdCpltCallback = HAL_OSPI_CmdCpltCallback;
2143  break;
2144  case HAL_OSPI_RX_CPLT_CB_ID :
2145  hospi->RxCpltCallback = HAL_OSPI_RxCpltCallback;
2146  break;
2147  case HAL_OSPI_TX_CPLT_CB_ID :
2148  hospi->TxCpltCallback = HAL_OSPI_TxCpltCallback;
2149  break;
2150  case HAL_OSPI_RX_HALF_CPLT_CB_ID :
2151  hospi->RxHalfCpltCallback = HAL_OSPI_RxHalfCpltCallback;
2152  break;
2153  case HAL_OSPI_TX_HALF_CPLT_CB_ID :
2154  hospi->TxHalfCpltCallback = HAL_OSPI_TxHalfCpltCallback;
2155  break;
2156  case HAL_OSPI_STATUS_MATCH_CB_ID :
2157  hospi->StatusMatchCallback = HAL_OSPI_StatusMatchCallback;
2158  break;
2159  case HAL_OSPI_TIMEOUT_CB_ID :
2160  hospi->TimeOutCallback = HAL_OSPI_TimeOutCallback;
2161  break;
2162  case HAL_OSPI_MSP_INIT_CB_ID :
2163  hospi->MspInitCallback = HAL_OSPI_MspInit;
2164  break;
2165  case HAL_OSPI_MSP_DEINIT_CB_ID :
2166  hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
2167  break;
2168  default :
2169  /* Update the error code */
2170  hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
2171  /* update return status */
2172  status = HAL_ERROR;
2173  break;
2174  }
2175  }
2176  else if (hospi->State == HAL_OSPI_STATE_RESET)
2177  {
2178  switch (CallbackID)
2179  {
2180  case HAL_OSPI_MSP_INIT_CB_ID :
2181  hospi->MspInitCallback = HAL_OSPI_MspInit;
2182  break;
2183  case HAL_OSPI_MSP_DEINIT_CB_ID :
2184  hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
2185  break;
2186  default :
2187  /* Update the error code */
2188  hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
2189  /* update return status */
2190  status = HAL_ERROR;
2191  break;
2192  }
2193  }
2194  else
2195  {
2196  /* Update the error code */
2197  hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
2198  /* update return status */
2199  status = HAL_ERROR;
2200  }
2201 
2202  return status;
2203 }
2204 #endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
2205 
2234 HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi)
2235 {
2236  HAL_StatusTypeDef status = HAL_OK;
2237  uint32_t state;
2238  uint32_t tickstart = HAL_GetTick();
2239 
2240  /* Check if the state is in one of the busy or configured states */
2241  state = hospi->State;
2242  if (((state & OSPI_BUSY_STATE_MASK) != 0U) || ((state & OSPI_CFG_STATE_MASK) != 0U))
2243  {
2244  /* Check if the DMA is enabled */
2245  if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0U)
2246  {
2247  /* Disable the DMA transfer on the OctoSPI side */
2248  CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
2249 
2250  /* Disable the DMA transfer on the DMA side */
2251  status = HAL_MDMA_Abort(hospi->hmdma);
2252  if (status != HAL_OK)
2253  {
2254  hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
2255  }
2256  }
2257 
2258  if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET)
2259  {
2260  /* Perform an abort of the OctoSPI */
2261  SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT);
2262 
2263  /* Wait until the transfer complete flag is set to go back in idle state */
2264  status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, hospi->Timeout);
2265 
2266  if (status == HAL_OK)
2267  {
2268  /* Clear transfer complete flag */
2269  __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
2270 
2271  /* Wait until the busy flag is reset to go back in idle state */
2272  status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout);
2273 
2274  if (status == HAL_OK)
2275  {
2276  /* Update state */
2277  hospi->State = HAL_OSPI_STATE_READY;
2278  }
2279  }
2280  }
2281  else
2282  {
2283  /* Update state */
2284  hospi->State = HAL_OSPI_STATE_READY;
2285  }
2286  }
2287  else
2288  {
2289  status = HAL_ERROR;
2290  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
2291  }
2292 
2293  /* Return function status */
2294  return status;
2295 }
2296 
2302 HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi)
2303 {
2304  HAL_StatusTypeDef status = HAL_OK;
2305  uint32_t state;
2306 
2307  /* Check if the state is in one of the busy or configured states */
2308  state = hospi->State;
2309  if (((state & OSPI_BUSY_STATE_MASK) != 0U) || ((state & OSPI_CFG_STATE_MASK) != 0U))
2310  {
2311  /* Disable all interrupts */
2312  __HAL_OSPI_DISABLE_IT(hospi, (HAL_OSPI_IT_TO | HAL_OSPI_IT_SM | HAL_OSPI_IT_FT | HAL_OSPI_IT_TC | HAL_OSPI_IT_TE));
2313 
2314  /* Update state */
2315  hospi->State = HAL_OSPI_STATE_ABORT;
2316 
2317  /* Check if the DMA is enabled */
2318  if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0U)
2319  {
2320  /* Disable the DMA transfer on the OctoSPI side */
2321  CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
2322 
2323  /* Disable the DMA transfer on the DMA side */
2324  hospi->hmdma->XferAbortCallback = OSPI_DMAAbortCplt;
2325  if (HAL_MDMA_Abort_IT(hospi->hmdma) != HAL_OK)
2326  {
2327  /* Update state */
2328  hospi->State = HAL_OSPI_STATE_READY;
2329 
2330  /* Abort callback */
2331 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
2332  hospi->AbortCpltCallback(hospi);
2333 #else
2334  HAL_OSPI_AbortCpltCallback(hospi);
2335 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
2336  }
2337  }
2338  else
2339  {
2340  if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET)
2341  {
2342  /* Clear transfer complete flag */
2343  __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
2344 
2345  /* Enable the transfer complete interrupts */
2346  __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC);
2347 
2348  /* Perform an abort of the OctoSPI */
2349  SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT);
2350  }
2351  else
2352  {
2353  /* Update state */
2354  hospi->State = HAL_OSPI_STATE_READY;
2355 
2356  /* Abort callback */
2357 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
2358  hospi->AbortCpltCallback(hospi);
2359 #else
2360  HAL_OSPI_AbortCpltCallback(hospi);
2361 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
2362  }
2363  }
2364  }
2365  else
2366  {
2367  status = HAL_ERROR;
2368  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
2369  }
2370 
2371  /* Return function status */
2372  return status;
2373 }
2374 
2380 HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t Threshold)
2381 {
2382  HAL_StatusTypeDef status = HAL_OK;
2383 
2384  /* Check the state */
2385  if ((hospi->State & OSPI_BUSY_STATE_MASK) == 0U)
2386  {
2387  /* Synchronize initialization structure with the new fifo threshold value */
2388  hospi->Init.FifoThreshold = Threshold;
2389 
2390  /* Configure new fifo threshold */
2391  MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold-1U) << OCTOSPI_CR_FTHRES_Pos));
2392 
2393  }
2394  else
2395  {
2396  status = HAL_ERROR;
2397  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
2398  }
2399 
2400  /* Return function status */
2401  return status;
2402 }
2403 
2408 uint32_t HAL_OSPI_GetFifoThreshold(OSPI_HandleTypeDef *hospi)
2409 {
2410  return ((READ_BIT(hospi->Instance->CR, OCTOSPI_CR_FTHRES) >> OCTOSPI_CR_FTHRES_Pos) + 1U);
2411 }
2412 
2418 HAL_StatusTypeDef HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeout)
2419 {
2420  hospi->Timeout = Timeout;
2421  return HAL_OK;
2422 }
2423 
2429 uint32_t HAL_OSPI_GetError(OSPI_HandleTypeDef *hospi)
2430 {
2431  return hospi->ErrorCode;
2432 }
2433 
2439 uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi)
2440 {
2441  /* Return OSPI handle state */
2442  return hospi->State;
2443 }
2444 
2471 HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout)
2472 {
2473  HAL_StatusTypeDef status = HAL_OK;
2474  uint32_t instance;
2475  uint8_t index;
2476  uint8_t ospi_enabled = 0U;
2477  uint8_t other_instance;
2478  OSPIM_CfgTypeDef IOM_cfg[OSPI_NB_INSTANCE];
2479 
2480  /* Prevent unused argument(s) compilation warning */
2481  UNUSED(Timeout);
2482 
2483  /* Check the parameters of the OctoSPI IO Manager configuration structure */
2484  assert_param(IS_OSPIM_PORT(cfg->ClkPort));
2485  assert_param(IS_OSPIM_DQS_PORT(cfg->DQSPort));
2486  assert_param(IS_OSPIM_PORT(cfg->NCSPort));
2487  assert_param(IS_OSPIM_IO_PORT(cfg->IOLowPort));
2488  assert_param(IS_OSPIM_IO_PORT(cfg->IOHighPort));
2489  assert_param(IS_OSPIM_REQ2ACKTIME(cfg->Req2AckTime));
2490 
2491  if (hospi->Instance == OCTOSPI1)
2492  {
2493  instance = 0U;
2494  other_instance = 1U;
2495  }
2496  else
2497  {
2498  instance = 1U;
2499  other_instance = 0U;
2500  }
2501 
2502  /**************** Get current configuration of the instances ****************/
2503  for (index = 0U; index < OSPI_NB_INSTANCE; index++)
2504  {
2505  if (OSPIM_GetConfig(index+1U, &(IOM_cfg[index])) != HAL_OK)
2506  {
2507  status = HAL_ERROR;
2508  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
2509  }
2510  }
2511 
2512  if (status == HAL_OK)
2513  {
2514  /********** Disable both OctoSPI to configure OctoSPI IO Manager **********/
2515  if ((OCTOSPI1->CR & OCTOSPI_CR_EN) != 0U)
2516  {
2517  CLEAR_BIT(OCTOSPI1->CR, OCTOSPI_CR_EN);
2518  ospi_enabled |= 0x1U;
2519  }
2520  if ((OCTOSPI2->CR & OCTOSPI_CR_EN) != 0U)
2521  {
2522  CLEAR_BIT(OCTOSPI2->CR, OCTOSPI_CR_EN);
2523  ospi_enabled |= 0x2U;
2524  }
2525 
2526  /***************** Deactivation of previous configuration *****************/
2527  CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN);
2528  if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U)
2529  {
2530  /* De-multiplexing should be performed */
2531  CLEAR_BIT(OCTOSPIM->CR, OCTOSPIM_CR_MUXEN);
2532 
2533  if (other_instance == 1U)
2534  {
2535  SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKSRC);
2536  if (IOM_cfg[other_instance].DQSPort != 0U)
2537  {
2538  SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSSRC);
2539  }
2540  if (IOM_cfg[other_instance].IOLowPort != HAL_OSPIM_IOPORT_NONE)
2541  {
2542  SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLSRC_1);
2543  }
2544  if (IOM_cfg[other_instance].IOHighPort != HAL_OSPIM_IOPORT_NONE)
2545  {
2546  SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHSRC_1);
2547  }
2548  }
2549  }
2550  else
2551  {
2552  if (IOM_cfg[instance].ClkPort != 0U)
2553  {
2554  CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN);
2555  if (IOM_cfg[instance].DQSPort != 0U)
2556  {
2557  CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN);
2558  }
2559  if (IOM_cfg[instance].IOLowPort != HAL_OSPIM_IOPORT_NONE)
2560  {
2561  CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN);
2562  }
2563  if (IOM_cfg[instance].IOHighPort != HAL_OSPIM_IOPORT_NONE)
2564  {
2565  CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
2566  }
2567  }
2568  }
2569 
2570  /********************* Deactivation of other instance *********************/
2571  if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) ||
2572  (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) ||
2573  (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
2574  {
2575  if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) &&
2576  (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) &&
2577  (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) &&
2578  (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
2579  {
2580  /* Multiplexing should be performed */
2581  SET_BIT(OCTOSPIM->CR, OCTOSPIM_CR_MUXEN);
2582  }
2583  else
2584  {
2585  CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN);
2586  if (IOM_cfg[other_instance].DQSPort != 0U)
2587  {
2588  CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN);
2589  }
2590  CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN);
2591  if (IOM_cfg[other_instance].IOLowPort != HAL_OSPIM_IOPORT_NONE)
2592  {
2593  CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
2594  OCTOSPIM_PCR_IOLEN);
2595  }
2596  if (IOM_cfg[other_instance].IOHighPort != HAL_OSPIM_IOPORT_NONE)
2597  {
2598  CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
2599  OCTOSPIM_PCR_IOHEN);
2600  }
2601  }
2602  }
2603 
2604  /******************** Activation of new configuration *********************/
2605  MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort - 1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC),
2606  (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos)));
2607 
2608  if ((cfg->Req2AckTime - 1U) > ((OCTOSPIM->CR & OCTOSPIM_CR_REQ2ACK_TIME) >> OCTOSPIM_CR_REQ2ACK_TIME_Pos))
2609  {
2610  MODIFY_REG(OCTOSPIM->CR, OCTOSPIM_CR_REQ2ACK_TIME, ((cfg->Req2AckTime - 1U) << OCTOSPIM_CR_REQ2ACK_TIME_Pos));
2611  }
2612 
2613  if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U)
2614  {
2615  MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), OCTOSPIM_PCR_CLKEN);
2616  if (cfg->DQSPort != 0U)
2617  {
2618  MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), OCTOSPIM_PCR_DQSEN);
2619  }
2620 
2621  if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
2622  {
2623  MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
2624  (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), OCTOSPIM_PCR_IOLEN);
2625  }
2626  else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE)
2627  {
2628  MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
2629  (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), OCTOSPIM_PCR_IOHEN);
2630  }
2631  else
2632  {
2633  /* Nothing to do */
2634  }
2635 
2636  if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
2637  {
2638  MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
2639  (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0));
2640  }
2641  else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE)
2642  {
2643  MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
2644  (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0));
2645  }
2646  else
2647  {
2648  /* Nothing to do */
2649  }
2650  }
2651  else
2652  {
2653  MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC),
2654  (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos)));
2655  if (cfg->DQSPort != 0U)
2656  {
2657  MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC),
2658  (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos)));
2659  }
2660 
2661  if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
2662  {
2663  MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
2664  (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
2665  (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
2666  }
2667  else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE)
2668  {
2669  MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
2670  (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
2671  (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
2672  }
2673  else
2674  {
2675  /* Nothing to do */
2676  }
2677 
2678  if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
2679  {
2680  MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
2681  (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
2682  (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
2683  }
2684  else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE)
2685  {
2686  MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
2687  (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
2688  (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
2689  }
2690  else
2691  {
2692  /* Nothing to do */
2693  }
2694  }
2695 
2696  /******* Re-enable both OctoSPI after configure OctoSPI IO Manager ********/
2697  if ((ospi_enabled & 0x1U) != 0U)
2698  {
2699  SET_BIT(OCTOSPI1->CR, OCTOSPI_CR_EN);
2700  }
2701  if ((ospi_enabled & 0x2U) != 0U)
2702  {
2703  SET_BIT(OCTOSPI2->CR, OCTOSPI_CR_EN);
2704  }
2705  }
2706 
2707  /* Return function status */
2708  return status;
2709 }
2710 
2723 static void OSPI_DMACplt(MDMA_HandleTypeDef *hmdma)
2724 {
2725  OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hmdma->Parent);
2726  hospi->XferCount = 0;
2727 
2728  /* Disable the DMA transfer on the OctoSPI side */
2729  CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
2730 
2731  /* Disable the DMA channel */
2732  __HAL_MDMA_DISABLE(hmdma);
2733 
2734  /* Enable the OSPI transfer complete Interrupt */
2735  __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC);
2736 }
2737 
2743 static void OSPI_DMAError(MDMA_HandleTypeDef *hmdma)
2744 {
2745  OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hmdma->Parent);
2746  hospi->XferCount = 0;
2747  hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
2748 
2749  /* Disable the DMA transfer on the OctoSPI side */
2750  CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
2751 
2752  /* Abort the OctoSPI */
2753  if (HAL_OSPI_Abort_IT(hospi) != HAL_OK)
2754  {
2755  /* Disable the interrupts */
2756  __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE);
2757 
2758  /* Update state */
2759  hospi->State = HAL_OSPI_STATE_READY;
2760 
2761  /* Error callback */
2762 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
2763  hospi->ErrorCallback(hospi);
2764 #else
2765  HAL_OSPI_ErrorCallback(hospi);
2766 #endif /*(USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
2767  }
2768 }
2769 
2775 static void OSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma)
2776 {
2777  OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hmdma->Parent);
2778  hospi->XferCount = 0;
2779 
2780  /* Check the state */
2781  if (hospi->State == HAL_OSPI_STATE_ABORT)
2782  {
2783  /* DMA abort called by OctoSPI abort */
2784  if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET)
2785  {
2786  /* Clear transfer complete flag */
2787  __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
2788 
2789  /* Enable the transfer complete interrupts */
2790  __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC);
2791 
2792  /* Perform an abort of the OctoSPI */
2793  SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT);
2794  }
2795  else
2796  {
2797  /* Update state */
2798  hospi->State = HAL_OSPI_STATE_READY;
2799 
2800  /* Abort callback */
2801 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
2802  hospi->AbortCpltCallback(hospi);
2803 #else
2804  HAL_OSPI_AbortCpltCallback(hospi);
2805 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
2806  }
2807  }
2808  else
2809  {
2810  /* DMA abort called due to a transfer error interrupt */
2811  /* Update state */
2812  hospi->State = HAL_OSPI_STATE_READY;
2813 
2814  /* Error callback */
2815 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
2816  hospi->ErrorCallback(hospi);
2817 #else
2818  HAL_OSPI_ErrorCallback(hospi);
2819 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
2820  }
2821 }
2822 
2832 static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag,
2833  FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
2834 {
2835  /* Wait until flag is in expected state */
2836  while((__HAL_OSPI_GET_FLAG(hospi, Flag)) != State)
2837  {
2838  /* Check for the Timeout */
2839  if (Timeout != HAL_MAX_DELAY)
2840  {
2841  if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
2842  {
2843  hospi->State = HAL_OSPI_STATE_ERROR;
2844  hospi->ErrorCode |= HAL_OSPI_ERROR_TIMEOUT;
2845 
2846  return HAL_ERROR;
2847  }
2848  }
2849  }
2850  return HAL_OK;
2851 }
2852 
2859 static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd)
2860 {
2861  HAL_StatusTypeDef status = HAL_OK;
2862  __IO uint32_t *ccr_reg;
2863  __IO uint32_t *tcr_reg;
2864  __IO uint32_t *ir_reg;
2865  __IO uint32_t *abr_reg;
2866 
2867  /* Re-initialize the value of the functional mode */
2868  MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0U);
2869 
2870  /* Configure the flash ID */
2871  if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE)
2872  {
2873  MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FSEL, cmd->FlashId);
2874  }
2875 
2876  if (cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)
2877  {
2878  ccr_reg = &(hospi->Instance->WCCR);
2879  tcr_reg = &(hospi->Instance->WTCR);
2880  ir_reg = &(hospi->Instance->WIR);
2881  abr_reg = &(hospi->Instance->WABR);
2882  }
2883  else if (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG)
2884  {
2885  ccr_reg = &(hospi->Instance->WPCCR);
2886  tcr_reg = &(hospi->Instance->WPTCR);
2887  ir_reg = &(hospi->Instance->WPIR);
2888  abr_reg = &(hospi->Instance->WPABR);
2889  }
2890  else
2891  {
2892  ccr_reg = &(hospi->Instance->CCR);
2893  tcr_reg = &(hospi->Instance->TCR);
2894  ir_reg = &(hospi->Instance->IR);
2895  abr_reg = &(hospi->Instance->ABR);
2896  }
2897 
2898  /* Configure the CCR register with DQS and SIOO modes */
2899  *ccr_reg = (cmd->DQSMode | cmd->SIOOMode);
2900 
2901  if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE)
2902  {
2903  /* Configure the ABR register with alternate bytes value */
2904  *abr_reg = cmd->AlternateBytes;
2905 
2906  /* Configure the CCR register with alternate bytes communication parameters */
2907  MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ABMODE | OCTOSPI_CCR_ABDTR | OCTOSPI_CCR_ABSIZE),
2908  (cmd->AlternateBytesMode | cmd->AlternateBytesDtrMode | cmd->AlternateBytesSize));
2909  }
2910 
2911  /* Configure the TCR register with the number of dummy cycles */
2912  MODIFY_REG((*tcr_reg), OCTOSPI_TCR_DCYC, cmd->DummyCycles);
2913 
2914  if (cmd->DataMode != HAL_OSPI_DATA_NONE)
2915  {
2916  if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG)
2917  {
2918  /* Configure the DLR register with the number of data */
2919  hospi->Instance->DLR = (cmd->NbData - 1U);
2920  }
2921  }
2922 
2923  if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE)
2924  {
2925  if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE)
2926  {
2927  if (cmd->DataMode != HAL_OSPI_DATA_NONE)
2928  {
2929  /* ---- Command with instruction, address and data ---- */
2930 
2931  /* Configure the CCR register with all communication parameters */
2932  MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE |
2933  OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE |
2934  OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR),
2935  (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
2936  cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize |
2937  cmd->DataMode | cmd->DataDtrMode));
2938  }
2939  else
2940  {
2941  /* ---- Command with instruction and address ---- */
2942 
2943  /* Configure the CCR register with all communication parameters */
2944  MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE |
2945  OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE),
2946  (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
2947  cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize));
2948 
2949  /* The DHQC bit is linked with DDTR bit which should be activated */
2950  if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) &&
2951  (cmd->InstructionDtrMode == HAL_OSPI_INSTRUCTION_DTR_ENABLE))
2952  {
2953  MODIFY_REG((*ccr_reg), OCTOSPI_CCR_DDTR, HAL_OSPI_DATA_DTR_ENABLE);
2954  }
2955  }
2956 
2957  /* Configure the IR register with the instruction value */
2958  *ir_reg = cmd->Instruction;
2959 
2960  /* Configure the AR register with the address value */
2961  hospi->Instance->AR = cmd->Address;
2962  }
2963  else
2964  {
2965  if (cmd->DataMode != HAL_OSPI_DATA_NONE)
2966  {
2967  /* ---- Command with instruction and data ---- */
2968 
2969  /* Configure the CCR register with all communication parameters */
2970  MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE |
2971  OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR),
2972  (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
2973  cmd->DataMode | cmd->DataDtrMode));
2974  }
2975  else
2976  {
2977  /* ---- Command with only instruction ---- */
2978 
2979  /* Configure the CCR register with all communication parameters */
2980  MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE),
2981  (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize));
2982 
2983  /* The DHQC bit is linked with DDTR bit which should be activated */
2984  if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) &&
2985  (cmd->InstructionDtrMode == HAL_OSPI_INSTRUCTION_DTR_ENABLE))
2986  {
2987  MODIFY_REG((*ccr_reg), OCTOSPI_CCR_DDTR, HAL_OSPI_DATA_DTR_ENABLE);
2988  }
2989  }
2990 
2991  /* Configure the IR register with the instruction value */
2992  *ir_reg = cmd->Instruction;
2993 
2994  }
2995  }
2996  else
2997  {
2998  if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE)
2999  {
3000  if (cmd->DataMode != HAL_OSPI_DATA_NONE)
3001  {
3002  /* ---- Command with address and data ---- */
3003 
3004  /* Configure the CCR register with all communication parameters */
3005  MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE |
3006  OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR),
3007  (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize |
3008  cmd->DataMode | cmd->DataDtrMode));
3009  }
3010  else
3011  {
3012  /* ---- Command with only address ---- */
3013 
3014  /* Configure the CCR register with all communication parameters */
3015  MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE),
3016  (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize));
3017  }
3018 
3019  /* Configure the AR register with the instruction value */
3020  hospi->Instance->AR = cmd->Address;
3021  }
3022  else
3023  {
3024  /* ---- Invalid command configuration (no instruction, no address) ---- */
3025  status = HAL_ERROR;
3026  hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
3027  }
3028  }
3029 
3030  /* Return function status */
3031  return status;
3032 }
3033 
3040 static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg)
3041 {
3042  HAL_StatusTypeDef status = HAL_OK;
3043  uint32_t reg;
3044  uint32_t value = 0U;
3045  uint32_t index;
3046 
3047  if ((instance_nb == 0U) || (instance_nb > OSPI_NB_INSTANCE) || (cfg == NULL))
3048  {
3049  /* Invalid parameter -> error returned */
3050  status = HAL_ERROR;
3051  }
3052  else
3053  {
3054  /* Initialize the structure */
3055  cfg->ClkPort = 0U;
3056  cfg->DQSPort = 0U;
3057  cfg->NCSPort = 0U;
3058  cfg->IOLowPort = 0U;
3059  cfg->IOHighPort = 0U;
3060 
3061  if (instance_nb == 2U)
3062  {
3063  if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) == 0U)
3064  {
3065  value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC
3066  | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1);
3067  }
3068  else
3069  {
3070  value = OCTOSPIM_PCR_NCSSRC;
3071  }
3072  }
3073 
3074  /* Get the information about the instance */
3075  for (index = 0U; index < OSPI_IOM_NB_PORTS; index ++)
3076  {
3077  reg = OCTOSPIM->PCR[index];
3078 
3079  if ((reg & OCTOSPIM_PCR_CLKEN) != 0U)
3080  {
3081  /* The clock is enabled on this port */
3082  if ((reg & OCTOSPIM_PCR_CLKSRC) == (value & OCTOSPIM_PCR_CLKSRC))
3083  {
3084  /* The clock correspond to the instance passed as parameter */
3085  cfg->ClkPort = index+1U;
3086  }
3087  }
3088 
3089  if ((reg & OCTOSPIM_PCR_DQSEN) != 0U)
3090  {
3091  /* The DQS is enabled on this port */
3092  if ((reg & OCTOSPIM_PCR_DQSSRC) == (value & OCTOSPIM_PCR_DQSSRC))
3093  {
3094  /* The DQS correspond to the instance passed as parameter */
3095  cfg->DQSPort = index+1U;
3096  }
3097  }
3098 
3099  if ((reg & OCTOSPIM_PCR_NCSEN) != 0U)
3100  {
3101  /* The nCS is enabled on this port */
3102  if ((reg & OCTOSPIM_PCR_NCSSRC) == (value & OCTOSPIM_PCR_NCSSRC))
3103  {
3104  /* The nCS correspond to the instance passed as parameter */
3105  cfg->NCSPort = index+1U;
3106  }
3107  }
3108 
3109  if ((reg & OCTOSPIM_PCR_IOLEN) != 0U)
3110  {
3111  /* The IO Low is enabled on this port */
3112  if ((reg & OCTOSPIM_PCR_IOLSRC_1) == (value & OCTOSPIM_PCR_IOLSRC_1))
3113  {
3114  /* The IO Low correspond to the instance passed as parameter */
3115  if ((reg & OCTOSPIM_PCR_IOLSRC_0) == 0U)
3116  {
3117  cfg->IOLowPort = (OCTOSPIM_PCR_IOLEN | (index+1U));
3118  }
3119  else
3120  {
3121  cfg->IOLowPort = (OCTOSPIM_PCR_IOHEN | (index+1U));
3122  }
3123  }
3124  }
3125 
3126  if ((reg & OCTOSPIM_PCR_IOHEN) != 0U)
3127  {
3128  /* The IO High is enabled on this port */
3129  if ((reg & OCTOSPIM_PCR_IOHSRC_1) == (value & OCTOSPIM_PCR_IOHSRC_1))
3130  {
3131  /* The IO High correspond to the instance passed as parameter */
3132  if ((reg & OCTOSPIM_PCR_IOHSRC_0) == 0U)
3133  {
3134  cfg->IOHighPort = (OCTOSPIM_PCR_IOLEN | (index+1U));
3135  }
3136  else
3137  {
3138  cfg->IOHighPort = (OCTOSPIM_PCR_IOHEN | (index+1U));
3139  }
3140  }
3141  }
3142  }
3143  }
3144 
3145  /* Return function status */
3146  return status;
3147 }
3148 
3157 #endif /* HAL_OSPI_MODULE_ENABLED */
3158 
3167 #endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */
3168 
3169 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
OCTOSPI_DCR1_FRCK
#define OCTOSPI_DCR1_FRCK
Definition: stm32h735xx.h:20824
assert_param
#define assert_param(expr)
Include module's header file.
Definition: stm32f407/stm32f407g-disc1/Inc/stm32f4xx_hal_conf.h:353
OCTOSPI_CR_DMAEN
#define OCTOSPI_CR_DMAEN
Definition: stm32h735xx.h:20778
__IO
#define __IO
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:237
OCTOSPI_CCR_ADSIZE
#define OCTOSPI_CCR_ADSIZE
Definition: stm32h735xx.h:20961
OCTOSPIM_PCR_DQSSRC_Pos
#define OCTOSPIM_PCR_DQSSRC_Pos
Definition: stm32h735xx.h:21227
OCTOSPI_CCR_ADDTR
#define OCTOSPI_CCR_ADDTR
Definition: stm32h735xx.h:20958
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
MDMA_DEST_DATASIZE_BYTE
#define MDMA_DEST_DATASIZE_BYTE
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:431
OCTOSPI_CR_ABORT
#define OCTOSPI_CR_ABORT
Definition: stm32h735xx.h:20775
MDMA_DEST_DATASIZE_HALFWORD
#define MDMA_DEST_DATASIZE_HALFWORD
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:432
OCTOSPI_DCR1_MTYP
#define OCTOSPI_DCR1_MTYP
Definition: stm32h735xx.h:20839
MDMA_DEST_INC_BYTE
#define MDMA_DEST_INC_BYTE
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:401
NULL
#define NULL
Definition: porcupine/demo/c/dr_libs/tests/external/miniaudio/extras/speex_resampler/thirdparty/resample.c:92
OCTOSPI_WCCR_DMODE_2
#define OCTOSPI_WCCR_DMODE_2
Definition: stm32h735xx.h:21148
OCTOSPI_CCR_DDTR
#define OCTOSPI_CCR_DDTR
Definition: stm32h735xx.h:20986
OCTOSPIM_PCR_IOHSRC_1
#define OCTOSPIM_PCR_IOHSRC_1
Definition: stm32h735xx.h:21251
MDMA_SRC_DATASIZE_WORD
#define MDMA_SRC_DATASIZE_WORD
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:420
OCTOSPI_WCCR_ADMODE_2
#define OCTOSPI_WCCR_ADMODE_2
Definition: stm32h735xx.h:21120
MDMA_SRC_INC_HALFWORD
#define MDMA_SRC_INC_HALFWORD
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:384
OCTOSPI_CR_TCEN
#define OCTOSPI_CR_TCEN
Definition: stm32h735xx.h:20781
OCTOSPIM_CR_REQ2ACK_TIME_Pos
#define OCTOSPIM_CR_REQ2ACK_TIME_Pos
Definition: stm32h735xx.h:21213
MDMA_DEST_INC_HALFWORD
#define MDMA_DEST_INC_HALFWORD
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:402
MDMA_DEST_INC_WORD
#define MDMA_DEST_INC_WORD
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:403
OCTOSPIM_PCR_IOHSRC
#define OCTOSPIM_PCR_IOHSRC
Definition: stm32h735xx.h:21249
OCTOSPI_DCR1_DEVSIZE_Pos
#define OCTOSPI_DCR1_DEVSIZE_Pos
Definition: stm32h735xx.h:20834
OCTOSPI_WCCR_ADDTR
#define OCTOSPI_WCCR_ADDTR
Definition: stm32h735xx.h:21123
OCTOSPI_DCR1_DLYBYP
#define OCTOSPI_DCR1_DLYBYP
Definition: stm32h735xx.h:20827
HAL_ERROR
@ HAL_ERROR
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:43
MDMA_SRC_DATASIZE_HALFWORD
#define MDMA_SRC_DATASIZE_HALFWORD
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:419
CLEAR_BIT
#define CLEAR_BIT(REG, BIT)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:214
HAL_GetTick
uint32_t HAL_GetTick(void)
Provides a tick value in millisecond.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:323
MDMA_SRC_INC_BYTE
#define MDMA_SRC_INC_BYTE
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:383
OCTOSPI_TCR_DCYC
#define OCTOSPI_TCR_DCYC
Definition: stm32h735xx.h:20997
OCTOSPI_CR_PMM
#define OCTOSPI_CR_PMM
Definition: stm32h735xx.h:20811
OCTOSPI_WCCR_DDTR
#define OCTOSPI_WCCR_DDTR
Definition: stm32h735xx.h:21151
OCTOSPI_DCR1_DEVSIZE
#define OCTOSPI_DCR1_DEVSIZE
Definition: stm32h735xx.h:20836
HAL_OK
@ HAL_OK
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:42
OCTOSPI_CCR_IDTR
#define OCTOSPI_CCR_IDTR
Definition: stm32h735xx.h:20944
OCTOSPI_DCR1_CKCSHT
#define OCTOSPI_DCR1_CKCSHT
Definition: stm32h735xx.h:20830
OCTOSPI_TCR_SSHIFT
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Definition: stm32h735xx.h:21003
OCTOSPI_CR_FSEL
#define OCTOSPI_CR_FSEL
Definition: stm32h735xx.h:20787
UNUSED
#define UNUSED(x)
Definition: porcupine/demo/c/dr_libs/old/dr.h:92
OCTOSPI_DCR2_PRESCALER_Pos
#define OCTOSPI_DCR2_PRESCALER_Pos
Definition: stm32h735xx.h:20845
OCTOSPI_CCR_IMODE
#define OCTOSPI_CCR_IMODE
Definition: stm32h735xx.h:20938
OCTOSPIM_PCR_NCSSRC_Pos
#define OCTOSPIM_PCR_NCSSRC_Pos
Definition: stm32h735xx.h:21233
MDMA_CTCR_SINCOS
#define MDMA_CTCR_SINCOS
Definition: stm32h735xx.h:14028
OCTOSPIM_PCR_NCSEN
#define OCTOSPIM_PCR_NCSEN
Definition: stm32h735xx.h:21232
OCTOSPI_DCR2_PRESCALER
#define OCTOSPI_DCR2_PRESCALER
Definition: stm32h735xx.h:20847
MDMA_SRC_INC_DISABLE
#define MDMA_SRC_INC_DISABLE
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:382
OCTOSPIM
#define OCTOSPIM
Definition: stm32h735xx.h:2775
MDMA_CTCR_DINC
#define MDMA_CTCR_DINC
Definition: stm32h735xx.h:14013
MDMA_CTCR_DINCOS
#define MDMA_CTCR_DINCOS
Definition: stm32h735xx.h:14033
OCTOSPI_DCR2_WRAPSIZE
#define OCTOSPI_DCR2_WRAPSIZE
Definition: stm32h735xx.h:20850
HAL_MDMA_Abort_IT
HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma)
OCTOSPI_HLCR_TRWR_Pos
#define OCTOSPI_HLCR_TRWR_Pos
Definition: stm32h735xx.h:21184
OCTOSPI_CR_APMS
#define OCTOSPI_CR_APMS
Definition: stm32h735xx.h:20808
OCTOSPI2
#define OCTOSPI2
Definition: stm32h735xx.h:2773
OCTOSPI_TCR_DHQC
#define OCTOSPI_TCR_DHQC
Definition: stm32h735xx.h:21000
MODIFY_REG
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:224
OCTOSPIM_PCR_IOLSRC_0
#define OCTOSPIM_PCR_IOLSRC_0
Definition: stm32h735xx.h:21242
OCTOSPI_HLCR_TACC_Pos
#define OCTOSPI_HLCR_TACC_Pos
Definition: stm32h735xx.h:21181
OCTOSPIM_PCR_CLKSRC
#define OCTOSPIM_PCR_CLKSRC
Definition: stm32h735xx.h:21223
RESET
@ RESET
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:187
OCTOSPIM_PCR_CLKSRC_Pos
#define OCTOSPIM_PCR_CLKSRC_Pos
Definition: stm32h735xx.h:21221
MDMA_CTCR_SINC
#define MDMA_CTCR_SINC
Definition: stm32h735xx.h:14008
HAL_MDMA_Abort
HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma)
OCTOSPI_CCR_ADMODE
#define OCTOSPI_CCR_ADMODE
Definition: stm32h735xx.h:20952
OCTOSPIM_PCR_IOLEN
#define OCTOSPIM_PCR_IOLEN
Definition: stm32h735xx.h:21238
OCTOSPI_CR_FTHRES_Pos
#define OCTOSPI_CR_FTHRES_Pos
Definition: stm32h735xx.h:20788
OCTOSPI_CR_FMODE
#define OCTOSPI_CR_FMODE
Definition: stm32h735xx.h:20814
OCTOSPI_DCR1_CKMODE
#define OCTOSPI_DCR1_CKMODE
Definition: stm32h735xx.h:20821
OCTOSPIM_PCR_IOHSRC_Pos
#define OCTOSPIM_PCR_IOHSRC_Pos
Definition: stm32h735xx.h:21247
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:216
__MDMA_HandleTypeDef
MDMA handle Structure definition.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:203
HAL_MAX_DELAY
#define HAL_MAX_DELAY
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:61
OCTOSPI_CR_DQM
#define OCTOSPI_CR_DQM
Definition: stm32h735xx.h:20784
OCTOSPIM_PCR_CLKEN
#define OCTOSPIM_PCR_CLKEN
Definition: stm32h735xx.h:21220
OCTOSPIM_PCR_NCSSRC
#define OCTOSPIM_PCR_NCSSRC
Definition: stm32h735xx.h:21235
OCTOSPI_CCR_ISIZE
#define OCTOSPI_CCR_ISIZE
Definition: stm32h735xx.h:20947
OCTOSPIM_PCR_IOHSRC_0
#define OCTOSPIM_PCR_IOHSRC_0
Definition: stm32h735xx.h:21250
OCTOSPI_SR_FLEVEL
#define OCTOSPI_SR_FLEVEL
Definition: stm32h735xx.h:20889
OCTOSPIM_PCR_IOLSRC_Pos
#define OCTOSPIM_PCR_IOLSRC_Pos
Definition: stm32h735xx.h:21239
OCTOSPI_CCR_ABSIZE
#define OCTOSPI_CCR_ABSIZE
Definition: stm32h735xx.h:20975
OCTOSPI_CCR_ADMODE_2
#define OCTOSPI_CCR_ADMODE_2
Definition: stm32h735xx.h:20955
OCTOSPIM_CR_MUXEN
#define OCTOSPIM_CR_MUXEN
Definition: stm32h735xx.h:21212
OCTOSPI_CR_EN
#define OCTOSPI_CR_EN
Definition: stm32h735xx.h:20772
OCTOSPIM_PCR_DQSSRC
#define OCTOSPIM_PCR_DQSSRC
Definition: stm32h735xx.h:21229
SET
@ SET
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:188
OCTOSPI_DCR1_MTYP_0
#define OCTOSPI_DCR1_MTYP_0
Definition: stm32h735xx.h:20840
OCTOSPIM_PCR_IOHEN
#define OCTOSPIM_PCR_IOHEN
Definition: stm32h735xx.h:21246
OCTOSPI_CCR_DMODE
#define OCTOSPI_CCR_DMODE
Definition: stm32h735xx.h:20980
OCTOSPI_CCR_DMODE_2
#define OCTOSPI_CCR_DMODE_2
Definition: stm32h735xx.h:20983
FlagStatus
FlagStatus
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:185
OCTOSPI_CCR_ABMODE
#define OCTOSPI_CCR_ABMODE
Definition: stm32h735xx.h:20966
OCTOSPIM_PCR_DQSEN
#define OCTOSPIM_PCR_DQSEN
Definition: stm32h735xx.h:21226
OCTOSPI_CCR_ABDTR
#define OCTOSPI_CCR_ABDTR
Definition: stm32h735xx.h:20972
OCTOSPIM_PCR_IOLSRC_1
#define OCTOSPIM_PCR_IOLSRC_1
Definition: stm32h735xx.h:21243
OCTOSPI_DCR1_CSHT_Pos
#define OCTOSPI_DCR1_CSHT_Pos
Definition: stm32h735xx.h:20831
WRITE_REG
#define WRITE_REG(REG, VAL)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:220
MDMA_DEST_DATASIZE_WORD
#define MDMA_DEST_DATASIZE_WORD
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:433
__MDMA_HandleTypeDef::Parent
void * Parent
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:213
READ_REG
#define READ_REG(REG)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:222
SET_BIT
#define SET_BIT(REG, BIT)
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:212
OCTOSPI1
#define OCTOSPI1
Definition: stm32h735xx.h:2771
OCTOSPIM_PCR_IOLSRC
#define OCTOSPIM_PCR_IOLSRC
Definition: stm32h735xx.h:21241
cmd
string cmd
MDMA_DEST_INC_DISABLE
#define MDMA_DEST_INC_DISABLE
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:400
__HAL_MDMA_DISABLE
#define __HAL_MDMA_DISABLE(__HANDLE__)
Disable the specified MDMA Channel.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:540
OCTOSPI_DCR3_MAXTRAN_Pos
#define OCTOSPI_DCR3_MAXTRAN_Pos
Definition: stm32h735xx.h:20856
OCTOSPI_DCR1_CKCSHT_Pos
#define OCTOSPI_DCR1_CKCSHT_Pos
Definition: stm32h735xx.h:20828
HAL_MDMA_Start_IT
HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
OCTOSPI_DCR3_CSBOUND_Pos
#define OCTOSPI_DCR3_CSBOUND_Pos
Definition: stm32h735xx.h:20859
OCTOSPI_DCR1_CSHT
#define OCTOSPI_DCR1_CSHT
Definition: stm32h735xx.h:20833
OCTOSPI_CR_FTHRES
#define OCTOSPI_CR_FTHRES
Definition: stm32h735xx.h:20790
OCTOSPIM_CR_REQ2ACK_TIME
#define OCTOSPIM_CR_REQ2ACK_TIME
Definition: stm32h735xx.h:21215
MDMA_SRC_DATASIZE_BYTE
#define MDMA_SRC_DATASIZE_BYTE
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:418
MDMA_SRC_INC_WORD
#define MDMA_SRC_INC_WORD
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:385

picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:14:54